//! Initializes the nand flash memory driver.
//!
//! The device identification is performed to initialize the
//! driver accordingly
//!
//! @param none
//!
//! @return none
//!
void nf_init ( void )
{
trace("NF init\n\r");
g_nf_init=FALSE;
// s_pending_write=FALSE;
#if (NF_GENERIC_DRIVER==TRUE)
#error Check this init...
g_n_zones = NF_N_ZONES;
g_n_blocks = NF_N_BLOCKS;
g_shift_block_page = NF_SHIFT_BLOCK_PAGE;
g_shift_page_byte = NF_SHIFT_PAGE_BYTE;
s_shift_sector_byte = NF_SHIFT_SECTOR_BYTE;
g_n_row_cycles = NF_N_ROW_CYCLES;
if ( Is_nf_2k() ) // 2KB pages
{
g_ofst_blk_status = 0;
}
if ( Is_nf_512() ) // 512B pages
{
g_ofst_blk_status = 5;
}
s_shift_log_page_sector = G_SHIFT_PAGE_BYTE - S_SHIFT_SECTOR_BYTE + NF_SHIFT_N_DEVICES;
s_shift_log_block_sector = s_shift_log_page_sector + G_SHIFT_BLOCK_PAGE;
#endif
g_cache_lut.ctrl.valid = FALSE; g_cache_lut.ctrl.dirty = FALSE;
g_cache_fbb.ctrl.valid = FALSE; g_cache_fbb.ctrl.dirty = FALSE;
g_last_log_sector= 0xFFFFFFFF;
}
//! \brief Tests the true busy. Note that we test twice the ready, since there is
//! an hardware minimum requirement between the end of the busy and the first
//! read cycle. Since the busy is not wired, the ready is tested twice.
//!
void nf_wait_busy( void )
{
ecchrs_freeze(&AVR32_ECCHRS);
nf_wr_cmd(NF_READ_STATUS_CMD);
if( Is_nf_2k() )
{
if( G_CACHE_PROG )
{
while( (nf_rd_data() & NF_MASK_STATUS_T_RDY_2KB )==0 );
while( (nf_rd_data() & NF_MASK_STATUS_T_RDY_2KB )==0 );
}
else
{
while( (nf_rd_data() & NF_MASK_STATUS_READY )==0 );
while( (nf_rd_data() & NF_MASK_STATUS_READY )==0 );
}
}
if( Is_nf_512() )
{
while( (nf_rd_data() & NF_MASK_STATUS_T_RDY_512B )==0 );
while( (nf_rd_data() & NF_MASK_STATUS_T_RDY_512B )==0 );
}
ecchrs_unfreeze(&AVR32_ECCHRS);
}
