static void brcm_intc_disable(unsigned int irq) { unsigned int shift; if (irq > 0 && irq <= 32) { shift = irq - 1; L1_WR_ALL(W0, MASK_SET, (1UL << shift)); } else if (irq > 32 && irq <= 32+32) { shift = irq - 32 - 1; L1_WR_ALL(W1, MASK_SET, (1UL << shift)); } else if (irq > 64 && irq <= 32+32+32) { shift = irq - 64 - 1; L1_WR_ALL(W2, MASK_SET, (1UL << shift)); } else BUG(); }
void __init arch_init_irq(void) { int irq; mips_cpu_irq_init(); L1_WR_ALL(W0, MASK_SET, 0xffffffff); L1_WR_ALL(W1, MASK_SET, 0xffffffff); L1_WR_ALL(W2, MASK_SET, 0xffffffff); clear_c0_status(ST0_IE | ST0_IM); /* Set up all L1 IRQs */ for (irq = 1; irq < BRCM_VIRTIRQ_BASE; irq++) set_irq_chip_and_handler(irq, &brcm_intc_type, handle_level_irq); #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) /* default affinity: 1 (TP0 only) */ cpumask_clear(irq_default_affinity); cpumask_set_cpu(0, irq_default_affinity); #endif /* enable IRQ2 (this runs on TP0). IRQ3 enabled during TP1 boot. */ set_c0_status(STATUSF_IP2); #if ! defined(CONFIG_BRCM_SHARED_UART_IRQ) /* enable non-shared UART interrupts in the L2 */ #if defined(BCHP_IRQ0_UART_IRQEN_uarta_MASK) /* 3548 style - separate register */ BDEV_WR(BCHP_IRQ0_UART_IRQEN, BCHP_IRQ0_UART_IRQEN_uarta_MASK | BCHP_IRQ0_UART_IRQEN_uartb_MASK | BCHP_IRQ0_UART_IRQEN_uartc_MASK); BDEV_WR(BCHP_IRQ0_IRQEN, 0); #elif defined(BCHP_IRQ0_IRQEN_uarta_irqen_MASK) /* 7405 style - shared with L2 */ BDEV_WR(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_MASK | BCHP_IRQ0_IRQEN_uartb_irqen_MASK #if defined(BCHP_IRQ0_IRQEN_uartc_irqen_MASK) | BCHP_IRQ0_IRQEN_uartc_irqen_MASK #endif ); #endif #if defined(CONFIG_BRCM_HAS_PCU_UARTS) BDEV_WR(BCHP_TVM_MAIN_INT_CNTL, 0); BDEV_WR_F(TVM_MAIN_INT_CNTL, MAIN_UART1_INT_EN, 1); #endif #else /* CONFIG_BRCM_SHARED_UART_IRQ */ /* Set up all UPG L2 interrupts */ BDEV_WR_RB(BCHP_IRQ0_IRQEN, 0); for (irq = BRCM_UPG_L2_BASE; irq <= BRCM_UPG_L2_LAST; irq++) set_irq_chip_and_handler(irq, &brcm_upg_type, handle_level_irq); #endif /* CONFIG_BRCM_SHARED_UART_IRQ */ #if defined(BCHP_HIF_INTR2_CPU_MASK_SET) /* mask and clear all HIF L2 interrupts */ BDEV_WR_RB(BCHP_HIF_INTR2_CPU_MASK_SET, 0xffffffff); BDEV_WR_RB(BCHP_HIF_INTR2_CPU_CLEAR, 0xffffffff); #endif }