static void
ping_thread_simulated (void)
{
volatile L4_Word_t x;
/* Wait for pong thread to come up */
L4_Msg_t msg;
L4_MsgTag_t tag;
for (int i=0; i < num_iterations; i++) {
L4_Fpage_t ppage = L4_Fpage((L4_Word_t)&fault_area[i*1024], 4096);
L4_Set_Rights(&ppage, L4_FullyAccessible);
/* accept fpages */
L4_Accept(L4_UntypedWordsAcceptor);
/* send it to our pager */
L4_MsgClear(&msg);
L4_MsgAppendWord(&msg, (L4_Word_t) ppage.raw);
L4_MsgAppendWord(&msg, (L4_Word_t) 0);
L4_Set_Label(&msg.tag, L4_PAGEFAULT);
L4_MsgLoad(&msg);
/* make the call */
tag = L4_Call(pager_tid);
x = fault_area[i*1024];
}
/* Tell master that we're finished */
L4_Set_MsgTag (L4_Niltag);
L4_Send (master_tid);
for (;;)
L4_WaitForever();
/* NOTREACHED */
}
static inline L4_Word_t
pingpong_ipc_async (void)
{
/* Wait for ping thread to send async ipc */
//L4_ThreadId_t from;
L4_Set_NotifyBits(0x55550000UL);
//L4_Set_NotifyMask(0xaaaaffffUL);
L4_Accept(L4_NotifyMsgAcceptor);
L4_MsgTag_t tag;
/*
tag.raw = 0;
tag.X.flags = (4 | 8); //SRBLOCK
tag = L4_Ipc(L4_nilthread, L4_anythread, tag, &from);
*/
tag = L4_WaitNotify(0x0L);
//if (getTagE(tag))
// printf("Open L4_call error %lx\n", L4_ErrorCode());
//L4_Word_t data = 0;
//L4_StoreMR(1, &data);
//printf("Get message %lx, notifybits %lx\n", data, L4_Get_NotifyBits());
//L4_Receive(pong_tid);
return tag.raw;
}
int
main(int argc, char **argv)
{
struct driver_ops *ops;
objref_t obj;
/*
* XXX: Should we be inserting the timer device into naming here?
*/
main_tid = thread_l4tid(env_thread(iguana_getenv("MAIN")));
obj = device_create_impl(main_tid, 0UL, NULL);
naming_insert("timer", obj);
ops = TIMER_DRIVER.ops.d_ops;
iguana_cb_handle = cb_attach(__callback_buffer);
#ifdef ENABLE_PM_THREAD
{
L4_ThreadId_t unused;
pm_thread = thread_create_priority(1, &unused);
L4_KDB_SetThreadName(unused, "PwrMgmt");
}
#endif
L4_Accept(L4_AsynchItemsAcceptor);
L4_Set_NotifyMask(1UL << 31);
timer_server_loop();
assert(!"Should reach here\n");
return 0;
}
/*
* Get current value, request timeout in the future for main thread, check
* notified correctly.
*/
static void
test01(void)
{
uint32_t cur_value;
L4_Word_t result;
L4_Word_t notifybits = 0x1;
L4_MsgTag_t tag;
L4_Word_t mask;
printf("%s: ", __func__);
result = counter_current_value(&cur_value);
if (result == 0) {
FAILED();
return;
}
result = counter_request(cur_value + 10, main_tid, notifybits);
if (result == 0) {
FAILED();
return;
}
L4_Set_NotifyMask(notifybits);
L4_Accept(L4_NotifyMsgAcceptor);
tag = L4_WaitNotify(&mask);
if (L4_IpcFailed(tag)) {
FAILED();
return;
}
PASSED();
}
static void
waiting_notify_thread(void *arg)
{
L4_Word_t notifybits;
L4_MsgTag_t tag;
L4_Word_t mask;
tag = L4_Receive(main_tid);
notifybits = L4_Label(tag);
L4_Set_NotifyMask(notifybits);
L4_Accept(L4_NotifyMsgAcceptor);
L4_LoadMR(0, 0);
L4_Send(main_tid);
tag = L4_WaitNotify(&mask);
if (L4_IpcFailed(tag)) {
FAILED();
return;
}
L4_Set_Label(&tag, notifybits);
L4_Set_MsgTag(tag);
L4_Call(main_tid);
while (1) { }
}
void
sys$sigma0_map_fpage(L4_Fpage_t virt_page, L4_Fpage_t phys_page,
unsigned int priv)
{
L4_ThreadId_t tid;
L4_MsgTag_t tag;
L4_Msg_t msg;
L4_MapItem_t map;
// Find Pager's ID
tid = L4_Pager();
L4_Set_Rights(&phys_page, priv);
L4_Accept(L4_MapGrantItems(virt_page));
L4_MsgClear(&msg);
L4_MsgAppendWord(&msg, (L4_Word_t) phys_page.raw);
L4_MsgAppendWord(&msg, (L4_Word_t) 0);
L4_Set_Label(&msg.tag, SIGMA0_REQUEST_LABEL);
L4_MsgLoad(&msg);
tag = L4_Call(tid);
PANIC(L4_IpcFailed(tag), notice(IPC_F_FAILED "IPC failed (error %ld: %s)\n",
L4_ErrorCode(), L4_ErrorCode_String(L4_ErrorCode())));
L4_MsgStore(tag, &msg);
L4_MsgGetMapItem(&msg, 0, &map);
if (dbg$virtual_memory == 1)
{
if (map.X.snd_fpage.raw == L4_Nilpage.raw)
{
notice(MEM_I_REJMAP "rejecting mapping\n");
notice(MEM_I_REJMAP "virtual $%016lX - $%016lX\n",
L4_Address(virt_page), L4_Address(virt_page)
+ (L4_Size(virt_page) - 1));
notice(MEM_I_REJMAP "physical $%016lX - $%016lX\n",
L4_Address(phys_page), L4_Address(phys_page)
+ (L4_Size(phys_page) - 1));
}
else
{
notice(MEM_I_ACCMAP "accepting mapping\n");
notice(MEM_I_ACCMAP "virtual $%016lX - $%016lX\n",
L4_Address(virt_page), L4_Address(virt_page)
+ (L4_Size(virt_page) - 1));
notice(MEM_I_ACCMAP "physical $%016lX - $%016lX\n",
L4_Address(phys_page), L4_Address(phys_page)
+ (L4_Size(phys_page) - 1));
}
}
return;
}
static inline L4_Word_t
pingpong_ipc_async_ovh (void)
{
L4_Set_NotifyBits(0x55550000UL);
L4_Accept(L4_NotifyMsgAcceptor);
L4_MsgTag_t tag;
tag = L4_WaitNotify(0x0L);
return tag.raw;
}
void
block_myself(void)
{
L4_MsgTag_t tag;
L4_Word_t mask;
L4_Accept(L4_NotifyMsgAcceptor);
L4_Set_NotifyMask(0x4);
do {
tag = L4_WaitNotify(&mask);
} while (mask != NOTIFY_MASK);
}
/*
* Entry point
*/
int
main(int argc, char * argv[])
{
int i;
for (i = 0; i < MAX_EVENTS; i++)
events[i].l = NULL;
whead = wtail = NULL; /* OK, probably not necessary; I like it */
L4_Accept(L4_NotifyMsgAcceptor);
L4_Set_NotifyMask(~0);
event_server_loop();
}
static void
utimer(void)
{
L4_KDB_SetThreadName(sos_my_tid(), "utimer");
L4_Accept(L4_UntypedWordsAcceptor);
List *entryq;
entryq = list_empty();
for (;;) {
L4_Yield();
// Walk the timer list
L4_Word_t now = L4_KDB_GetTick();
list_delete(entryq, processExpired, &now);
// Wait for a new packet either blocking or non-blocking
L4_MsgTag_t tag = L4_Niltag;
if (list_null(entryq))
L4_Set_ReceiveBlock(&tag);
else
L4_Clear_ReceiveBlock(&tag);
L4_ThreadId_t wait_tid = L4_nilthread;
tag = L4_Ipc(L4_nilthread, L4_anythread, tag, &wait_tid);
if (!L4_IpcFailed(tag)) {
// Received a time out request queue it
L4_Msg_t msg; L4_MsgStore(tag, &msg); // Get the message
utimer_entry_t *entry = (utimer_entry_t *) L4_MsgWord(&msg, 0);
entry->fTid = wait_tid;
list_shift(entryq, entry);
}
else if (3 == L4_ErrorCode()) // Receive error # 1
continue; // no-partner - non-blocking
else
assert(!"Unhandled IPC error");
}
}
int
l4e_sigma0_map_fpage(L4_Fpage_t virt_page, L4_Fpage_t phys_page)
{
/*
* XXX: These two special cases are workarounds for broken superpage
* support in pistachio. On ARM, 1M superpages are disabled by
* pistachio to reduce the size of the mapping database, however due to
* bugs in the mapping code, any mappings >= 1M get converted into 4K
* mappings (rather than 64K). For MIPS, the tlb refill code assumes
* only 4K mappings are used, even the the pagetable building code will
* use superpages where possible. -- alexw
*/
#if defined(ARCH_ARM)
uintptr_t virt_base = L4_Address(virt_page);
uintptr_t phys_base = L4_Address(phys_page);
uintptr_t offset = 0;
uintptr_t step = L4_Size(virt_page) > 0x10000 ? 0x10000 : L4_Size(virt_page);
uintptr_t limit = L4_Size(virt_page) - 1;
for (virt_page = L4_Fpage(virt_base + offset, step),
phys_page = L4_Fpage(phys_base + offset, step);
offset < limit;
offset += step,
virt_page = L4_Fpage(virt_base + offset, step),
phys_page = L4_Fpage(phys_base + offset, step))
#elif defined(ARCH_MIPS64)
uintptr_t virt_base = L4_Address(virt_page);
uintptr_t phys_base = L4_Address(phys_page);
uintptr_t offset = 0;
uintptr_t step = 0x1000;
uintptr_t limit = L4_Size(virt_page) - 1;
for (virt_page = L4_Fpage(virt_base + offset, step),
phys_page = L4_Fpage(phys_base + offset, step);
offset < limit;
offset += step,
virt_page = L4_Fpage(virt_base + offset, step),
phys_page = L4_Fpage(phys_base + offset, step))
#endif
{
L4_ThreadId_t tid;
L4_MsgTag_t tag;
L4_Msg_t msg;
L4_MapItem_t map;
/*
* find our pager's ID
*/
tid = L4_Pager();
L4_Set_Rights(&phys_page, L4_FullyAccessible);
/* accept fpages */
L4_Accept(L4_MapGrantItems(virt_page));
/* send it to our pager */
L4_MsgClear(&msg);
L4_MsgAppendWord(&msg, (L4_Word_t) phys_page.raw);
L4_MsgAppendWord(&msg, (L4_Word_t) 0);
L4_Set_Label(&msg.tag, SIGMA0_REQUEST_LABEL);
L4_MsgLoad(&msg);
/* make the call */
tag = L4_Call(tid);
/* check for an error */
if (L4_IpcFailed(tag)) {
return 2;
}
L4_MsgStore(tag, &msg);
L4_MsgGetMapItem(&msg, 0, &map);
/*
* rejected mapping?
*/
if (map.X.snd_fpage.raw == L4_Nilpage.raw) {
return 1;
}
}
return 0;
}
static void
handler(void)
{
int i;
L4_Word_t irq, control;
irq = interrupt;
//L4_MsgTag_t tag;
L4_Call(master_tid);
/* Accept interrupts */
L4_Accept(L4_NotifyMsgAcceptor);
L4_Set_NotifyMask(~0UL);
/* Handle interrupts */
for (i=0; i < num_iterations + 2; i++)
{
int k,j;
struct counter **count;
uint64_t cnt = 0;
L4_Word_t mask;
#if defined(CONFIG_CPU_ARM_XSCALE) || defined(CONFIG_CPU_ARM_ARM1136JS) || defined(CONFIG_CPU_ARM_ARM1176JZS)
//Setup pmu irq
L4_KDB_PMN_Write(REG_CCNT, 0xFF800000); //At least leave 0x100000 cycles
L4_Word_t PMNC = L4_KDB_PMN_Read(REG_PMNC) & ~PMNC_CCNT_64DIV;
L4_KDB_PMN_Write(REG_PMNC, (PMNC | PMNC_CCNT_OFL | PMNC_CCNT_ENABLE) & ~PMNC_CCNT_RESET);
L4_KDB_PMN_Ofl_Write(REG_CCNT, ~0UL);
#endif
// ack/wait IRQ
control = 0 | (3 << 6);
L4_LoadMR(0, irq);
(void)L4_InterruptControl(L4_nilthread, control);
L4_StoreMR(1, &mask);
irq = __L4_TCR_PlatformReserved(0);
//tag.raw = 0x0000C000;
//tag = L4_Ipc(from, thread_tid, tag, &from);
//if (getTagE(tag))
// printf("ipc error %lx\n", L4_ErrorCode());
//printf("Receive irq ipc from %lx\n", from.raw);
#if defined(CONFIG_CPU_ARM_XSCALE) || defined(CONFIG_CPU_ARM_ARM1136JS) || defined(CONFIG_CPU_ARM_ARM1176JZS)
//Get CCNT count
cnt = L4_KDB_PMN_Read(REG_CCNT);
PMNC = L4_KDB_PMN_Read(REG_PMNC);
assert(PMNC & ~PMNC_CCNT_OFL);
//Since on ARM11, PMNC IRQ can only be deasserted when PMU is enabled,
//need to clear overflow flag and disable IRQ before disable PMU.
L4_KDB_PMN_Write(REG_PMNC, (PMNC | PMNC_CCNT_OFL) & ~PMNC_CCNT_ENIRQ);
//Stop CCNT.
L4_KDB_PMN_Write(REG_PMNC, PMNC & ~PMNC_CCNT_ENABLE);
//printf("CNT is %016lld\n", cnt);
#endif
//Write result back.
for (k = 0, count = irq_ipc_counters; *count != NULL; count++, k++)
{
for (j = 0; j < (*count)->get_num_counters(*count); j++)
{
results[k] += cnt;
if ( i == 0 || i == 1) //we don't count the first 2 run, since they contain page fault and cache miss latency.
results[k] -= cnt;
}
}
}
/* Tell master that we're finished */
L4_Set_MsgTag (L4_Niltag);
L4_Send (master_tid);
for (;;)
L4_WaitForever();
/* NOTREACHED */
}
