void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
gd->used_laws |= (1 << idx);
out_be32(LAWAR_ADDR(idx), 0);
set_law_base_addr(idx, addr);
out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz);
/* Read back so that we sync the writes */
in_be32(LAWAR_ADDR(idx));
}
void disable_law(u8 idx)
{
gd->used_laws &= ~(1 << idx);
out_be32(LAWAR_ADDR(idx), 0);
set_law_base_addr(idx, 0);
/* Read back so that we sync the writes */
in_be32(LAWAR_ADDR(idx));
return;
}
static int get_law_entry(u8 i, struct law_entry *e)
{
u32 lawar;
lawar = in_be32(LAWAR_ADDR(i));
if (!(lawar & LAW_EN))
return 0;
e->addr = get_law_base_addr(i);
e->size = lawar & 0x3f;
e->trgt_id = (lawar >> 20) & 0xff;
return 1;
}
void init_laws(void)
{
int i;
#if FSL_HW_NUM_LAWS < 32
gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
#elif FSL_HW_NUM_LAWS == 32
gd->used_laws = 0;
#else
#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
#endif
/*
* Any LAWs that were set up before we booted assume they are meant to
* be around and mark them used.
*/
for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
u32 lawar = in_be32(LAWAR_ADDR(i));
if (lawar & LAW_EN)
gd->used_laws |= (1 << i);
}
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*
* in NAND boot we've already parsed the law_table and setup those LAWs
* so don't do it again.
*/
return;
#endif
for (i = 0; i < num_law_entries; i++) {
if (law_table[i].index == -1)
set_next_law(law_table[i].addr, law_table[i].size,
law_table[i].trgt_id);
else
set_law(law_table[i].index, law_table[i].addr,
law_table[i].size, law_table[i].trgt_id);
}
return ;
}
void print_laws(void)
{
int i;
u32 lawar;
printf("\nLocal Access Window Configuration\n");
for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
lawar = in_be32(LAWAR_ADDR(i));
#ifdef CONFIG_FSL_CORENET
printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x",
i, in_be32(LAWBARH_ADDR(i)),
i, in_be32(LAWBARL_ADDR(i)));
#else
printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i)));
#endif
printf(" LAWAR%02d: 0x%08x\n", i, lawar);
printf("\t(EN: %d TGT: 0x%02x SIZE: ",
(lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff);
print_size(lawar_size(lawar), ")\n");
}
return;
}
void disable_non_ddr_laws(void)
{
int i;
int id;
for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
u32 lawar = in_be32(LAWAR_ADDR(i));
if (lawar & LAW_EN) {
id = (lawar & ~LAW_EN) >> 20;
switch (id) {
case LAW_TRGT_IF_DDR_1:
case LAW_TRGT_IF_DDR_2:
case LAW_TRGT_IF_DDR_3:
case LAW_TRGT_IF_DDR_4:
case LAW_TRGT_IF_DDR_INTRLV:
case LAW_TRGT_IF_DDR_INTLV_34:
case LAW_TRGT_IF_DDR_INTLV_123:
case LAW_TRGT_IF_DDR_INTLV_1234:
continue;
default:
disable_law(i);
}
}
}
void init_laws(void)
{
int i;
#if FSL_HW_NUM_LAWS < 32
gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
#elif FSL_HW_NUM_LAWS == 32
gd->used_laws = 0;
#else
#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
#endif
/*
* Any LAWs that were set up before we booted assume they are meant to
* be around and mark them used.
*/
for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
u32 lawar = in_be32(LAWAR_ADDR(i));
if (lawar & LAW_EN)
gd->used_laws |= (1 << i);
}
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*
* in NAND boot we've already parsed the law_table and setup those LAWs
* so don't do it again.
*/
return;
#endif
for (i = 0; i < num_law_entries; i++) {
if (law_table[i].index == -1)
set_next_law(law_table[i].addr, law_table[i].size,
law_table[i].trgt_id);
else
set_law(law_table[i].index, law_table[i].addr,
law_table[i].size, law_table[i].trgt_id);
}
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* check RCW to get which port is used for boot */
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 bootloc = in_be32(&gur->rcwsr[6]);
/*
* in SRIO or PCIE boot we need to set specail LAWs for
* SRIO or PCIE interfaces.
*/
switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
case 0x0: /* boot from PCIE1 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_1);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_1);
break;
case 0x1: /* boot from PCIE2 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_2);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_2);
break;
case 0x2: /* boot from PCIE3 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_3);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_3);
break;
case 0x8: /* boot from SRIO1 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_RIO_1);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_RIO_1);
break;
case 0x9: /* boot from SRIO2 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_RIO_2);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_RIO_2);
break;
default:
break;
}
#endif
return ;
}
