static void
fsl_nand_init_regs(struct fsl_nand_softc *sc)
{
uint32_t or_v, br_v;
device_t dev;
dev = sc->dev;
sc->fcm.reg_fmr = (15 << FMR_CWTO_SHIFT);
/*
* Setup 4 row cycles and hope that chip ignores superfluous address
* bytes.
*/
sc->fcm.reg_fmr |= (2 << FMR_AL_SHIFT);
/* Reprogram BR(x) */
br_v = lbc_read_reg(dev, LBC85XX_BR(sc->dinfo->di_bank));
br_v &= 0xffff8000;
br_v |= 1 << 11; /* 8-bit port size */
br_v |= 0 << 9; /* No ECC checking and generation */
br_v |= 1 << 5; /* FCM machine */
br_v |= 1; /* Valid */
lbc_write_reg(dev, LBC85XX_BR(sc->dinfo->di_bank), br_v);
/* Reprogram OR(x) */
or_v = lbc_read_reg(dev, LBC85XX_OR(sc->dinfo->di_bank));
or_v &= 0xfffffc00;
or_v |= 0x03AE; /* Default POR timing */
lbc_write_reg(dev, LBC85XX_OR(sc->dinfo->di_bank), or_v);
if (or_v & OR_FCM_PAGESIZE) {
sc->pgsz = FSL_LARGE_PAGE_SIZE;
sc->col_cycles = 2;
nand_debug(NDBG_DRV, "%s: large page NAND device at #%d",
device_get_nameunit(dev), sc->dinfo->di_bank);
} else {
sc->pgsz = FSL_SMALL_PAGE_SIZE;
sc->col_cycles = 1;
nand_debug(NDBG_DRV, "%s: small page NAND device at #%d",
device_get_nameunit(dev), sc->dinfo->di_bank);
}
}
static int
lbc_attach(device_t dev)
{
struct lbc_softc *sc;
struct lbc_devinfo *di;
struct rman *rm;
u_long offset, start, size;
device_t cdev;
phandle_t node, child;
pcell_t *ranges, *rangesptr;
int tuple_size, tuples;
int par_addr_cells;
int bank, error, i;
sc = device_get_softc(dev);
sc->sc_dev = dev;
sc->sc_mrid = 0;
sc->sc_mres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_mrid,
RF_ACTIVE);
if (sc->sc_mres == NULL)
return (ENXIO);
sc->sc_bst = rman_get_bustag(sc->sc_mres);
sc->sc_bsh = rman_get_bushandle(sc->sc_mres);
for (bank = 0; bank < LBC_DEV_MAX; bank++) {
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_BR(bank), 0);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_OR(bank), 0);
}
/*
* Initialize configuration register:
* - enable Local Bus
* - set data buffer control signal function
* - disable parity byte select
* - set ECC parity type
* - set bus monitor timing and timer prescale
*/
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LBCR, 0);
/*
* Initialize clock ratio register:
* - disable PLL bypass mode
* - configure LCLK delay cycles for the assertion of LALE
* - set system clock divider
*/
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LCRR, 0x00030008);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LTEDR, 0);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LTESR, ~0);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LTEIR, 0x64080001);
sc->sc_irid = 0;
sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
RF_ACTIVE | RF_SHAREABLE);
if (sc->sc_ires != NULL) {
error = bus_setup_intr(dev, sc->sc_ires,
INTR_TYPE_MISC | INTR_MPSAFE, NULL, lbc_intr, sc,
&sc->sc_icookie);
if (error) {
device_printf(dev, "could not activate interrupt\n");
bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
sc->sc_ires);
sc->sc_ires = NULL;
}
}
sc->sc_ltesr = ~0;
rangesptr = NULL;
rm = &sc->sc_rman;
rm->rm_type = RMAN_ARRAY;
rm->rm_descr = "Local Bus Space";
rm->rm_start = 0UL;
rm->rm_end = ~0UL;
error = rman_init(rm);
if (error)
goto fail;
error = rman_manage_region(rm, rm->rm_start, rm->rm_end);
if (error) {
rman_fini(rm);
goto fail;
}
/*
* Process 'ranges' property.
*/
node = ofw_bus_get_node(dev);
if ((fdt_addrsize_cells(node, &sc->sc_addr_cells,
&sc->sc_size_cells)) != 0) {
error = ENXIO;
goto fail;
}
par_addr_cells = fdt_parent_addr_cells(node);
if (par_addr_cells > 2) {
device_printf(dev, "unsupported parent #addr-cells\n");
error = ERANGE;
goto fail;
}
tuple_size = sizeof(pcell_t) * (sc->sc_addr_cells + par_addr_cells +
sc->sc_size_cells);
tuples = OF_getprop_alloc(node, "ranges", tuple_size,
(void **)&ranges);
if (tuples < 0) {
device_printf(dev, "could not retrieve 'ranges' property\n");
error = ENXIO;
goto fail;
}
rangesptr = ranges;
debugf("par addr_cells = %d, addr_cells = %d, size_cells = %d, "
"tuple_size = %d, tuples = %d\n", par_addr_cells,
sc->sc_addr_cells, sc->sc_size_cells, tuple_size, tuples);
start = 0;
size = 0;
for (i = 0; i < tuples; i++) {
/* The first cell is the bank (chip select) number. */
bank = fdt_data_get((void *)ranges, 1);
if (bank < 0 || bank > LBC_DEV_MAX) {
device_printf(dev, "bank out of range: %d\n", bank);
error = ERANGE;
goto fail;
}
ranges += 1;
/*
* Remaining cells of the child address define offset into
* this CS.
*/
offset = fdt_data_get((void *)ranges, sc->sc_addr_cells - 1);
ranges += sc->sc_addr_cells - 1;
/* Parent bus start address of this bank. */
start = fdt_data_get((void *)ranges, par_addr_cells);
ranges += par_addr_cells;
size = fdt_data_get((void *)ranges, sc->sc_size_cells);
ranges += sc->sc_size_cells;
debugf("bank = %d, start = %lx, size = %lx\n", bank,
start, size);
sc->sc_banks[bank].addr = start + offset;
sc->sc_banks[bank].size = size;
/*
* Attributes for the bank.
*
* XXX Note there are no DT bindings defined for them at the
* moment, so we need to provide some defaults.
*/
sc->sc_banks[bank].width = 16;
sc->sc_banks[bank].msel = LBCRES_MSEL_GPCM;
sc->sc_banks[bank].decc = LBCRES_DECC_DISABLED;
sc->sc_banks[bank].atom = LBCRES_ATOM_DISABLED;
sc->sc_banks[bank].wp = 0;
}
/*
* Initialize mem-mappings for the LBC banks (i.e. chip selects).
*/
error = lbc_banks_map(sc);
if (error)
goto fail;
/*
* Walk the localbus and add direct subordinates as our children.
*/
for (child = OF_child(node); child != 0; child = OF_peer(child)) {
di = malloc(sizeof(*di), M_LBC, M_WAITOK | M_ZERO);
if (ofw_bus_gen_setup_devinfo(&di->di_ofw, child) != 0) {
free(di, M_LBC);
device_printf(dev, "could not set up devinfo\n");
continue;
}
resource_list_init(&di->di_res);
if (fdt_lbc_reg_decode(child, sc, di)) {
device_printf(dev, "could not process 'reg' "
"property\n");
ofw_bus_gen_destroy_devinfo(&di->di_ofw);
free(di, M_LBC);
continue;
}
fdt_lbc_fixup(child, sc, di);
/* Add newbus device for this FDT node */
cdev = device_add_child(dev, NULL, -1);
if (cdev == NULL) {
device_printf(dev, "could not add child: %s\n",
di->di_ofw.obd_name);
resource_list_free(&di->di_res);
ofw_bus_gen_destroy_devinfo(&di->di_ofw);
free(di, M_LBC);
continue;
}
debugf("added child name='%s', node=%p\n", di->di_ofw.obd_name,
(void *)child);
device_set_ivars(cdev, di);
}
/*
* Enable the LBC.
*/
lbc_banks_enable(sc);
free(rangesptr, M_OFWPROP);
return (bus_generic_attach(dev));
fail:
free(rangesptr, M_OFWPROP);
bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mrid, sc->sc_mres);
return (error);
}
static int
lbc_banks_enable(struct lbc_softc *sc)
{
u_long size;
uint32_t regval;
int error, i;
for (i = 0; i < LBC_DEV_MAX; i++) {
size = sc->sc_banks[i].size;
if (size == 0)
continue;
/*
* Compute and program BR value.
*/
regval = sc->sc_banks[i].addr;
switch (sc->sc_banks[i].width) {
case 8:
regval |= (1 << 11);
break;
case 16:
regval |= (2 << 11);
break;
case 32:
regval |= (3 << 11);
break;
default:
error = EINVAL;
goto fail;
}
regval |= (sc->sc_banks[i].decc << 9);
regval |= (sc->sc_banks[i].wp << 8);
regval |= (sc->sc_banks[i].msel << 5);
regval |= (sc->sc_banks[i].atom << 2);
regval |= 1;
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
LBC85XX_BR(i), regval);
/*
* Compute and program OR value.
*/
regval = lbc_address_mask(size);
switch (sc->sc_banks[i].msel) {
case LBCRES_MSEL_GPCM:
/* TODO Add flag support for option registers */
regval |= 0x0ff7;
break;
case LBCRES_MSEL_FCM:
/* TODO Add flag support for options register */
regval |= 0x0796;
break;
case LBCRES_MSEL_UPMA:
case LBCRES_MSEL_UPMB:
case LBCRES_MSEL_UPMC:
printf("UPM mode not supported yet!");
error = ENOSYS;
goto fail;
}
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
LBC85XX_OR(i), regval);
}
return (0);
fail:
lbc_banks_unmap(sc);
return (error);
}
static int
lbc_banks_enable(struct lbc_softc *sc)
{
u_long size;
uint32_t regval;
int error, i;
for (i = 0; i < LBC_DEV_MAX; i++) {
size = sc->sc_banks[i].size;
if (size == 0) {
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
LBC85XX_BR(i), 0);
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
LBC85XX_OR(i), 0);
continue;
}
/*
* Compute and program BR value.
*/
regval = sc->sc_banks[i].addr;
switch (sc->sc_banks[i].width) {
case 8:
regval |= (1 << 11);
break;
case 16:
regval |= (2 << 11);
break;
case 32:
regval |= (3 << 11);
break;
default:
error = EINVAL;
goto fail;
}
regval |= (sc->sc_banks[i].decc << 9);
regval |= (sc->sc_banks[i].wp << 8);
regval |= (sc->sc_banks[i].msel << 5);
regval |= (sc->sc_banks[i].atom << 2);
regval |= 1;
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
LBC85XX_BR(i), regval);
/*
* Compute and program OR value.
*/
regval = lbc_address_mask(size);
switch (sc->sc_banks[i].msel) {
case LBCRES_MSEL_GPCM:
/* TODO Add flag support for option registers */
regval |= 0x0ff7;
break;
case LBCRES_MSEL_FCM:
/* TODO Add flag support for options register */
regval |= 0x0796;
break;
case LBCRES_MSEL_UPMA:
case LBCRES_MSEL_UPMB:
case LBCRES_MSEL_UPMC:
printf("UPM mode not supported yet!");
error = ENOSYS;
goto fail;
}
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
LBC85XX_OR(i), regval);
}
/*
* Initialize configuration register:
* - enable Local Bus
* - set data buffer control signal function
* - disable parity byte select
* - set ECC parity type
* - set bus monitor timing and timer prescale
*/
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LBCR, 0);
/*
* Initialize clock ratio register:
* - disable PLL bypass mode
* - configure LCLK delay cycles for the assertion of LALE
* - set system clock divider
*/
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LCRR, 0x00030008);
return (0);
fail:
lbc_banks_unmap(sc);
return (error);
}
static int
lbc_init_child(device_t dev, device_t child)
{
struct lbc_softc *sc;
struct lbc_devinfo *dinfo;
const struct lbc_resource *res;
u_long start, size;
uint32_t regbuff;
int error, unit;
sc = device_get_softc(dev);
dinfo = device_get_ivars(child);
res = mpc85xx_lbc_resources;
regbuff = 0;
unit = -1;
for (; res->lbr_devtype; res++) {
if (res->lbr_unit != dinfo->lbc_unit)
continue;
start = res->lbr_base_addr;
size = res->lbr_size;
unit = res->lbr_unit;
/*
* Configure LAW for this LBC device and map its physical
* memory region into KVA
*/
error = law_enable(OCP85XX_TGTIF_LBC, start, size);
if (error)
return (error);
sc->sc_kva[unit] = (vm_offset_t)pmap_mapdev(start, size);
if (sc->sc_kva[unit] == 0) {
law_disable(OCP85XX_TGTIF_LBC, start, size);
return (ENOSPC);
}
/*
* Compute and program BR value
*/
regbuff |= start;
switch (res->lbr_port_size) {
case 8:
regbuff |= (1 << 11);
break;
case 16:
regbuff |= (2 << 11);
break;
case 32:
regbuff |= (3 << 11);
break;
default:
error = EINVAL;
goto fail;
}
regbuff |= (res->lbr_decc << 9);
regbuff |= (res->lbr_wp << 8);
regbuff |= (res->lbr_msel << 5);
regbuff |= (res->lbr_atom << 2);
regbuff |= 1;
lbc_write_reg(sc, LBC85XX_BR(unit), regbuff);
/*
* Compute and program OR value
*/
regbuff = 0;
regbuff |= lbc_address_mask(size);
switch (res->lbr_msel) {
case LBCRES_MSEL_GPCM:
/* TODO Add flag support for option registers */
regbuff |= 0x00000ff7;
break;
case LBCRES_MSEL_FCM:
printf("FCM mode not supported yet!");
error = ENOSYS;
goto fail;
case LBCRES_MSEL_UPMA:
case LBCRES_MSEL_UPMB:
case LBCRES_MSEL_UPMC:
printf("UPM mode not supported yet!");
error = ENOSYS;
goto fail;
}
lbc_write_reg(sc, LBC85XX_OR(unit), regbuff);
return (0);
}
fail:
if (unit != -1) {
law_disable(OCP85XX_TGTIF_LBC, start, size);
pmap_unmapdev(sc->sc_kva[unit], size);
return (error);
} else
return (ENOENT);
}