/** * @brief De-initialize USART registers (Registers restored to their default values). * @param USARTx USART Instance * @retval An ErrorStatus enumeration value: * - SUCCESS: USART registers are de-initialized * - ERROR: USART registers are not de-initialized */ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_UART_INSTANCE(USARTx)); if (USARTx == USART1) { /* Force reset of USART clock */ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1); /* Release reset of USART clock */ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1); } else if (USARTx == USART2) { /* Force reset of USART clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); /* Release reset of USART clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); } #if defined(USART3) else if (USARTx == USART3) { /* Force reset of USART clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3); /* Release reset of USART clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3); } #endif /* USART3 */ #if defined(UART4) else if (USARTx == UART4) { /* Force reset of UART clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4); /* Release reset of UART clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4); } #endif /* UART4 */ #if defined(UART5) else if (USARTx == UART5) { /* Force reset of UART clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5); /* Release reset of UART clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5); } #endif /* UART5 */ else { status = ERROR; } return (status); }
/** * @brief De-initialize registers of the selected DAC instance * to their default reset values. * @param DACx DAC instance * @retval An ErrorStatus enumeration value: * - SUCCESS: DAC registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) { /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(DACx)); if(DACx == DAC1) { /* Force reset of DAC clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1); /* Release reset of DAC clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1); } #if defined(DAC2) else { /* Force reset of DAC clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC2); /* Release reset of DAC clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC2); } #endif return SUCCESS; }
/** * @brief De-initialize the I2C registers to their default reset values. * @param I2Cx I2C Instance. * @retval An ErrorStatus enumeration value: * - SUCCESS: I2C registers are de-initialized * - ERROR: I2C registers are not de-initialized */ uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx) { ErrorStatus status = SUCCESS; /* Check the I2C Instance I2Cx */ assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); if (I2Cx == I2C1) { /* Force reset of I2C clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1); /* Release reset of I2C clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1); } #if defined(I2C2) else if (I2Cx == I2C2) { /* Force reset of I2C clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2); /* Release reset of I2C clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2); } #endif else { status = ERROR; } return status; }
/** * @brief Set TIMx registers to their reset values. * @param TIMx Timer instance * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: invalid TIMx instance */ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) { ErrorStatus result = SUCCESS; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(TIMx)); if (TIMx == TIM2) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); } #if defined(TIM3) else if (TIMx == TIM3) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); } #endif /* TIM3 */ #if defined(TIM6) else if (TIMx == TIM6) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); } #endif /* TIM6 */ #if defined(TIM7) else if (TIMx == TIM7) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); } #endif /* TIM7 */ else if (TIMx == TIM21) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM21); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM21); } #if defined(TIM22) else if (TIMx == TIM22) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM22); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM22); } #endif /* TIM22 */ else { result = ERROR; } return result; }
/** * @brief De-initialize the SPI registers to their default reset values. * @param SPIx SPI Instance * @retval An ErrorStatus enumeration value: * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) { ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_SPI_ALL_INSTANCE(SPIx)); #if defined(SPI1) if (SPIx == SPI1) { /* Force reset of SPI clock */ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); /* Release reset of SPI clock */ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); status = SUCCESS; } #endif /* SPI1 */ #if defined(SPI2) if (SPIx == SPI2) { /* Force reset of SPI clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); /* Release reset of SPI clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); status = SUCCESS; } #endif /* SPI2 */ return status; }
/** * @brief Set LPTIMx registers to their reset values. * @param LPTIMx LP Timer instance * @retval An ErrorStatus enumeration value: * - SUCCESS: LPTIMx registers are de-initialized * - ERROR: invalid LPTIMx instance */ ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx) { ErrorStatus result = SUCCESS; /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(LPTIMx)); if (LPTIMx == LPTIM1) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1); } #if defined(LPTIM2) else if (LPTIMx == LPTIM2) { LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2); LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2); } #endif else { result = ERROR; } return result; }
/** * @brief De-Initializes CRS peripheral registers to their default reset values. * @retval An ErrorStatus enumeration value: * - SUCCESS: CRS registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_CRS_DeInit(void) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS); return SUCCESS; }
/** * @brief De-initialize the PWR registers to their default reset values. * @retval An ErrorStatus enumeration value: * - SUCCESS: PWR registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_PWR_DeInit(void) { /* Force reset of PWR clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR); /* Release reset of PWR clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR); return SUCCESS; }
/** * @brief De-initialize the PWR registers to their default reset values. * @retval An ErrorStatus enumeration value: * - SUCCESS: PWR registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_PWR_DeInit(void) { /* Force reset of PWR clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR); /* Release reset of PWR clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR); WRITE_REG(PWR->CR2, (PWR_CR2_CWUPF1 | PWR_CR2_CWUPF2 | PWR_CR2_CWUPF3 | PWR_CR2_CWUPF4 | PWR_CR2_CWUPF5 | PWR_CR2_CWUPF6)); return SUCCESS; }
/** * @brief De-initialize the UCPD registers to their default reset values. * @param UCPDx ucpd Instance * @retval An ErrorStatus enumeration value: * - SUCCESS: ucpd registers are de-initialized * - ERROR: ucpd registers are not de-initialized */ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx) { ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_UCPD_ALL_INSTANCE(UCPDx)); LL_UCPD_Disable(UCPDx); if (UCPD1 == UCPDx) { /* Force reset of ucpd clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UCPD1); /* Release reset of ucpd clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UCPD1); /* Disbale ucpd clock */ LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UCPD1); status = SUCCESS; } if (UCPD2 == UCPDx) { /* Force reset of ucpd clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UCPD2); /* Release reset of ucpd clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UCPD2); /* Disbale ucpd clock */ LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UCPD2); status = SUCCESS; } return status; }
/** * @brief De-initialize registers of the selected DAC instance * to their default reset values. * @param DACx DAC instance * @retval An ErrorStatus enumeration value: * - SUCCESS: DAC registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) { /* Prevent unused argument(s) compilation warning */ UNUSED(DACx); /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(DACx)); /* Force reset of DAC1 clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1); /* Release reset of DAC1 clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1); return SUCCESS; }
/** * @brief De-initialize LPUART registers (Registers restored to their default values). * @param LPUARTx LPUART Instance * @retval An ErrorStatus enumeration value: * - SUCCESS: LPUART registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_LPUART_INSTANCE(LPUARTx)); if (LPUARTx == LPUART1) { /* Force reset of LPUART peripheral */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPUART1); /* Release reset of LPUART peripheral */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPUART1); } else { status = ERROR; } return (status); }