/** * @brief Return I2Cx clock frequency * @param I2CxSource This parameter can be one of the following values: * @arg @ref LL_RCC_I2C1_CLKSOURCE * @arg @ref LL_RCC_I2C3_CLKSOURCE (*) * * (*) value not defined in all devices * @retval I2C clock frequency (in Hz) * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready */ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) { uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); /* I2C1 CLK clock frequency */ if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) { switch (LL_RCC_GetI2CClockSource(I2CxSource)) { case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ i2c_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { i2c_frequency = HSI_VALUE; } break; case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */ default: i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } } #if defined(RCC_CCIPR_I2C3SEL) /* I2C3 CLK clock frequency */ if (I2CxSource == LL_RCC_I2C3_CLKSOURCE) { switch (LL_RCC_GetI2CClockSource(I2CxSource)) { case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ i2c_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { i2c_frequency = HSI_VALUE; } break; case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */ default: i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } } #endif /*RCC_CCIPR_I2C3SEL*/ return i2c_frequency; }
/** * @brief Return SWPMIx clock frequency * @param SWPMIxSource This parameter can be one of the following values: * @arg @ref LL_RCC_SWPMI1_CLKSOURCE * @retval SWPMI clock frequency (in Hz) * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready */ uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource) { uint32_t swpmi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_SWPMI_CLKSOURCE(SWPMIxSource)); /* SWPMI1CLK clock frequency */ switch (LL_RCC_GetSWPMIClockSource(SWPMIxSource)) { case LL_RCC_SWPMI1_CLKSOURCE_HSI: /* SWPMI1 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { swpmi_frequency = HSI_VALUE; } break; case LL_RCC_SWPMI1_CLKSOURCE_PCLK: /* SWPMI1 Clock is PCLK1 */ default: swpmi_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } return swpmi_frequency; }
/** * @brief Return CEC clock frequency * @param CECxSource This parameter can be one of the following values: * @arg @ref LL_RCC_CEC_CLKSOURCE * @retval CEC clock frequency (in Hz) * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready */ uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) { uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); /* CECCLK clock frequency */ switch (LL_RCC_GetCECClockSource(CECxSource)) { case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */ if (LL_RCC_LSE_IsReady()) { cec_frequency = LSE_VALUE; } break; case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */ default: if (LL_RCC_HSI_IsReady()) { cec_frequency = HSI_VALUE/488U; } break; } return cec_frequency; }
/** * @brief Return I2Cx clock frequency * @param I2CxSource This parameter can be one of the following values: * @arg @ref LL_RCC_I2C1_CLKSOURCE * @retval I2C clock frequency (in Hz) * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready */ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) { uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); /* I2C1 CLK clock frequency */ if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) { switch (LL_RCC_GetI2CClockSource(I2CxSource)) { case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ i2c_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ default: if (LL_RCC_HSI_IsReady()) { i2c_frequency = HSI_VALUE; } break; } } return i2c_frequency; }
/** * @brief Reset the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source * - HSE, PLL, PLLI2S, PLLSAI OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval An ErrorStatus enumeration value: * - SUCCESS: RCC registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_RCC_DeInit(void) { uint32_t vl_mask = 0xFFFFFFFFU; /* Set HSION bit */ LL_RCC_HSI_Enable(); /* Wait for HSI READY bit */ while(LL_RCC_HSI_IsReady() != 1U) {} /* Reset CFGR register */ LL_RCC_WriteReg(CFGR, 0x00000000U); /* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */ CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_PLLSAION | RCC_CR_PLLI2SON)); /* Write new mask in CR register */ LL_RCC_WriteReg(CR, vl_mask); /* Set HSITRIM bits to the reset value*/ LL_RCC_HSI_SetCalibTrimming(0x10U); /* Wait for PLL READY bit to be reset */ while(LL_RCC_PLL_IsReady() != 0U) {} /* Wait for PLLI2S READY bit to be reset */ while(LL_RCC_PLLI2S_IsReady() != 0U) {} /* Wait for PLLSAI READY bit to be reset */ while(LL_RCC_PLLSAI_IsReady() != 0U) {} /* Reset PLLCFGR register */ LL_RCC_WriteReg(PLLCFGR, 0x24003010U); /* Reset PLLI2SCFGR register */ LL_RCC_WriteReg(PLLI2SCFGR, 0x24003000U); /* Reset PLLSAICFGR register */ LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U); /* Disable all interrupts */ CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE); /* Clear all interrupt flags */ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC); /* Clear LSION bit */ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); /* Reset all CSR flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); return SUCCESS; }
/* * Unconditionally switch the system clock source to HSI. */ __unused static void stm32_clock_switch_to_hsi(u32_t ahb_prescaler) { /* Enable HSI if not enabled */ if (LL_RCC_HSI_IsReady() != 1) { /* Enable HSI */ LL_RCC_HSI_Enable(); while (LL_RCC_HSI_IsReady() != 1) { /* Wait for HSI ready */ } } /* Set HSI as SYSCLCK source */ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI); LL_RCC_SetAHBPrescaler(ahb_prescaler); while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) { } }
/** * @brief Return LPTIMx clock frequency * @param LPTIMxSource This parameter can be one of the following values: * @arg @ref LL_RCC_LPTIM1_CLKSOURCE * @retval LPTIM clock frequency (in Hz) * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready */ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) { uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE) { /* LPTIM1CLK clock frequency */ switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) { case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ if (LL_RCC_LSI_IsReady()) { lptim_frequency = LSI_VALUE; } break; case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { lptim_frequency = HSI_VALUE; } break; case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ if (LL_RCC_LSE_IsReady()) { lptim_frequency = LSE_VALUE; } break; case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ default: lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } } return lptim_frequency; }
/** * @brief Return USARTx clock frequency * @param USARTxSource This parameter can be one of the following values: * @arg @ref LL_RCC_USART1_CLKSOURCE * @arg @ref LL_RCC_USART2_CLKSOURCE (*) * * (*) value not defined in all devices. * @retval USART clock frequency (in Hz) * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready */ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) { uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); #if defined(RCC_CCIPR_USART1SEL) if (USARTxSource == LL_RCC_USART1_CLKSOURCE) { /* USART1CLK clock frequency */ switch (LL_RCC_GetUSARTClockSource(USARTxSource)) { case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ usart_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { usart_frequency = HSI_VALUE; } break; case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ if (LL_RCC_LSE_IsReady()) { usart_frequency = LSE_VALUE; } break; case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */ default: usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } } #endif /* RCC_CCIPR_USART1SEL */ #if defined(RCC_CCIPR_USART2SEL) if (USARTxSource == LL_RCC_USART2_CLKSOURCE) { /* USART2CLK clock frequency */ switch (LL_RCC_GetUSARTClockSource(USARTxSource)) { case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ usart_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { usart_frequency = HSI_VALUE; } break; case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ if (LL_RCC_LSE_IsReady()) { usart_frequency = LSE_VALUE; } break; case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ default: usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } } #endif /* RCC_CCIPR_USART2SEL */ return usart_frequency; }
/** * @brief Return SAIx clock frequency * @param SAIxSource This parameter can be one of the following values: * @arg @ref LL_RCC_SAI1_CLKSOURCE * @arg @ref LL_RCC_SAI2_CLKSOURCE * @retval SAI clock frequency (in Hz) * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used */ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) { uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource)); if (SAIxSource == LL_RCC_SAI1_CLKSOURCE) { /* SAI1CLK clock frequency */ switch (LL_RCC_GetSAIClockSource(SAIxSource)) { case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */ if (LL_RCC_PLLSAI_IsReady()) { sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI(); } break; case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */ if (LL_RCC_PLLI2S_IsReady()) { sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI(); } break; #if defined(RCC_SAI1SEL_PLLSRC_SUPPORT) case LL_RCC_SAI1_CLKSOURCE_PLLSRC: switch (LL_RCC_PLL_GetMainSource()) { case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 clock source */ if (LL_RCC_HSE_IsReady()) { sai_frequency = HSE_VALUE; } break; case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 clock source */ default: if (LL_RCC_HSI_IsReady()) { sai_frequency = HSI_VALUE; } break; } break; #endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */ case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */ default: sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA; break; } } else { if (SAIxSource == LL_RCC_SAI2_CLKSOURCE) { /* SAI2CLK clock frequency */ switch (LL_RCC_GetSAIClockSource(SAIxSource)) { case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */ if (LL_RCC_PLLSAI_IsReady()) { sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI(); } break; case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */ if (LL_RCC_PLLI2S_IsReady()) { sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI(); } break; #if defined(RCC_SAI2SEL_PLLSRC_SUPPORT) case LL_RCC_SAI2_CLKSOURCE_PLLSRC: switch (LL_RCC_PLL_GetMainSource()) { case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */ if (LL_RCC_HSE_IsReady()) { sai_frequency = HSE_VALUE; } break; case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */ default: if (LL_RCC_HSI_IsReady()) { sai_frequency = HSI_VALUE; } break; } break; #endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */ case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */ default: sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA; break; } } } return sai_frequency; }
/** * @brief Return UARTx clock frequency * @param UARTxSource This parameter can be one of the following values: * @arg @ref LL_RCC_UART4_CLKSOURCE * @arg @ref LL_RCC_UART5_CLKSOURCE * @arg @ref LL_RCC_UART7_CLKSOURCE * @arg @ref LL_RCC_UART8_CLKSOURCE * @retval UART clock frequency (in Hz) * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready */ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) { uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource)); if (UARTxSource == LL_RCC_UART4_CLKSOURCE) { /* UART4CLK clock frequency */ switch (LL_RCC_GetUARTClockSource(UARTxSource)) { case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */ uart_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { uart_frequency = HSI_VALUE; } break; case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */ if (LL_RCC_LSE_IsReady()) { uart_frequency = LSE_VALUE; } break; case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */ default: uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } } else if (UARTxSource == LL_RCC_UART5_CLKSOURCE) { /* UART5CLK clock frequency */ switch (LL_RCC_GetUARTClockSource(UARTxSource)) { case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */ uart_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { uart_frequency = HSI_VALUE; } break; case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */ if (LL_RCC_LSE_IsReady()) { uart_frequency = LSE_VALUE; } break; case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */ default: uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } } else if (UARTxSource == LL_RCC_UART7_CLKSOURCE) { /* UART7CLK clock frequency */ switch (LL_RCC_GetUARTClockSource(UARTxSource)) { case LL_RCC_UART7_CLKSOURCE_SYSCLK: /* UART7 Clock is System Clock */ uart_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_UART7_CLKSOURCE_HSI: /* UART7 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { uart_frequency = HSI_VALUE; } break; case LL_RCC_UART7_CLKSOURCE_LSE: /* UART7 Clock is LSE Osc. */ if (LL_RCC_LSE_IsReady()) { uart_frequency = LSE_VALUE; } break; case LL_RCC_UART7_CLKSOURCE_PCLK1: /* UART7 Clock is PCLK1 */ default: uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } } else { if (UARTxSource == LL_RCC_UART8_CLKSOURCE) { /* UART8CLK clock frequency */ switch (LL_RCC_GetUARTClockSource(UARTxSource)) { case LL_RCC_UART8_CLKSOURCE_SYSCLK: /* UART8 Clock is System Clock */ uart_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_UART8_CLKSOURCE_HSI: /* UART8 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { uart_frequency = HSI_VALUE; } break; case LL_RCC_UART8_CLKSOURCE_LSE: /* UART8 Clock is LSE Osc. */ if (LL_RCC_LSE_IsReady()) { uart_frequency = LSE_VALUE; } break; case LL_RCC_UART8_CLKSOURCE_PCLK1: /* UART8 Clock is PCLK1 */ default: uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } } } return uart_frequency; }