/**
* @brief Reset the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - HSI ON and used as system clock source
* - HSE, PLL, PLLI2S, PLLSAI OFF
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS, MCO OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RCC registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_RCC_DeInit(void)
{
uint32_t vl_mask = 0xFFFFFFFFU;
/* Set HSION bit */
LL_RCC_HSI_Enable();
/* Wait for HSI READY bit */
while(LL_RCC_HSI_IsReady() != 1U)
{}
/* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000U);
/* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */
CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_PLLSAION | RCC_CR_PLLI2SON));
/* Write new mask in CR register */
LL_RCC_WriteReg(CR, vl_mask);
/* Set HSITRIM bits to the reset value*/
LL_RCC_HSI_SetCalibTrimming(0x10U);
/* Wait for PLL READY bit to be reset */
while(LL_RCC_PLL_IsReady() != 0U)
{}
/* Wait for PLLI2S READY bit to be reset */
while(LL_RCC_PLLI2S_IsReady() != 0U)
{}
/* Wait for PLLSAI READY bit to be reset */
while(LL_RCC_PLLSAI_IsReady() != 0U)
{}
/* Reset PLLCFGR register */
LL_RCC_WriteReg(PLLCFGR, 0x24003010U);
/* Reset PLLI2SCFGR register */
LL_RCC_WriteReg(PLLI2SCFGR, 0x24003000U);
/* Reset PLLSAICFGR register */
LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U);
/* Disable all interrupts */
CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE);
/* Clear all interrupt flags */
SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC);
/* Clear LSION bit */
CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
/* Reset all CSR flags */
SET_BIT(RCC->CSR, RCC_CSR_RMVF);
return SUCCESS;
}
/**
* @brief Reset the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - HSI ON and used as system clock source
* - HSE and PLL OFF
* - AHB and APB1 prescaler set to 1.
* - CSS, MCO OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RCC registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_RCC_DeInit(void)
{
uint32_t vl_mask = 0U;
/* Set HSION bit */
LL_RCC_HSI_Enable();
/* Set HSITRIM bits to the reset value*/
LL_RCC_HSI_SetCalibTrimming(0x10U);
/* Reset SW, HPRE, PPRE and MCOSEL bits */
vl_mask = 0xFFFFFFFFU;
CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCOSEL));
LL_RCC_WriteReg(CFGR, vl_mask);
/* Reset HSEON, CSSON, PLLON bits */
vl_mask = 0xFFFFFFFFU;
CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON));
LL_RCC_WriteReg(CR, vl_mask);
/* Reset HSEBYP bit */
LL_RCC_HSE_DisableBypass();
/* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000U);
#if defined(RCC_HSI48_SUPPORT)
/* Reset CR2 register */
LL_RCC_WriteReg(CR2, 0x00000000U);
/* Disable HSI48 */
LL_RCC_HSI48_Disable();
#endif /*RCC_HSI48_SUPPORT*/
/* Set HSI14TRIM/HSI14ON/HSI14DIS bits to the reset value*/
LL_RCC_HSI14_SetCalibTrimming(0x10U);
LL_RCC_HSI14_Disable();
LL_RCC_HSI14_EnableADCControl();
/* Reset CFGR2 register */
LL_RCC_WriteReg(CFGR2, 0x00000000U);
/* Reset CFGR3 register */
LL_RCC_WriteReg(CFGR3, 0x00000000U);
/* Clear pending flags */
#if defined(RCC_HSI48_SUPPORT)
vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC);
#else
vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC);
#endif /* RCC_HSI48_SUPPORT */
SET_BIT(RCC->CIR, vl_mask);
/* Disable all interrupts */
LL_RCC_WriteReg(CIR, 0x00000000U);
return SUCCESS;
}
/**
* @brief Reset the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - MSI ON and used as system clock source
* - HSE, HSI, PLL and PLLSAIxSource OFF
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS, MCO OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RCC registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_RCC_DeInit(void)
{
uint32_t vl_mask = 0;
/* Set MSION bit */
LL_RCC_MSI_Enable();
/* Insure MSIRDY bit is set before writing default MSIRANGE value */
while (LL_RCC_MSI_IsReady() == 0)
{
__NOP();
}
/* Set MSIRANGE default value */
LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
/* Set MSITRIM bits to the reset value*/
LL_RCC_MSI_SetCalibTrimming(0);
/* Set HSITRIM bits to the reset value*/
LL_RCC_HSI_SetCalibTrimming(0x10);
/* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000);
vl_mask = 0xFFFFFFFFU;
/* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLSYSON bits */
CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON |
RCC_CR_PLLON));
/* Reset PLLSAI1ON bit */
CLEAR_BIT(vl_mask, RCC_CR_PLLSAI1ON);
#if defined(RCC_PLLSAI2_SUPPORT)
/* Reset PLLSAI2ON bit */
CLEAR_BIT(vl_mask, RCC_CR_PLLSAI2ON);
#endif /*RCC_PLLSAI2_SUPPORT*/
/* Write new mask in CR register */
LL_RCC_WriteReg(CR, vl_mask);
/* Reset PLLCFGR register */
LL_RCC_WriteReg(PLLCFGR, 16 << RCC_POSITION_PLLN);
/* Reset PLLSAI1CFGR register */
LL_RCC_WriteReg(PLLSAI1CFGR, 16 << RCC_POSITION_PLLSAI1N);
#if defined(RCC_PLLSAI2_SUPPORT)
/* Reset PLLSAI2CFGR register */
LL_RCC_WriteReg(PLLSAI2CFGR, 16 << RCC_POSITION_PLLSAI2N);
#endif /*RCC_PLLSAI2_SUPPORT*/
/* Reset HSEBYP bit */
LL_RCC_HSE_DisableBypass();
/* Disable all interrupts */
LL_RCC_WriteReg(CIER, 0x00000000);
return SUCCESS;
}
/**
* @brief Reset the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - MSI ON and used as system clock source
* - HSE, HSI and PLL OFF
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS, MCO OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RCC registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_RCC_DeInit(void)
{
uint32_t vl_mask = 0U;
/* Set MSION bit */
LL_RCC_MSI_Enable();
/* Insure MSIRDY bit is set before writing default MSIRANGE value */
while (LL_RCC_MSI_IsReady() == 0U)
{
__NOP();
}
/* Set MSIRANGE default value */
LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5);
/* Set MSITRIM bits to the reset value*/
LL_RCC_MSI_SetCalibTrimming(0U);
/* Set HSITRIM bits to the reset value*/
LL_RCC_HSI_SetCalibTrimming(0x10U);
/* Reset SW, HPRE, PPRE and MCOSEL bits */
vl_mask = 0xFFFFFFFFU;
CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL));
LL_RCC_WriteReg(CFGR, vl_mask);
/* Reset HSI, HSE, PLL */
vl_mask = LL_RCC_ReadReg(CR);
#if defined(RCC_CR_HSIOUTEN)
CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
RCC_CR_HSEON | RCC_CR_PLLON);
#else
CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \
RCC_CR_HSEON | RCC_CR_PLLON);
#endif
LL_RCC_WriteReg(CR, vl_mask);
/* Delay after an RCC peripheral clock */
vl_mask = LL_RCC_ReadReg(CR);
/* Reset HSEBYP bit */
LL_RCC_HSE_DisableBypass();
/* Set RCC_CR_RTCPRE to 0b00*/
CLEAR_BIT(vl_mask, RCC_CR_RTCPRE);
LL_RCC_WriteReg(CR, vl_mask);
/* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000U);
#if defined(RCC_HSI48_SUPPORT)
/* Reset CRRCR register */
LL_RCC_WriteReg(CRRCR, 0x00000000U);
/* Disable HSI48 */
LL_RCC_HSI48_Disable();
#endif /*RCC_HSI48_SUPPORT*/
/* Disable all interrupts */
LL_RCC_WriteReg(CIER, 0x00000000U);
return SUCCESS;
}
