/**
* Update microcode patch in current processor for Family14h ON.
*
* This function acts as a wrapper for calling the LoadMicrocodePatch
* routine at AmdInitEarly.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[in] EarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F14OnLoadMicrocodePatchAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrValue;
AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);
// To load a microcode patch while using the cache as general storage,
// the following steps are followed:
// 1. Program MSRC001_102B[L2AllocDcFlushVictim]=1.
// 2. Load the microcode patch.
// 3. Program MSRC001_102B[L2AllocDcFlushVictim]=0.
LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
MsrValue = MsrValue | BIT7;
LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);
LoadMicrocodePatch (StdHeader);
LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
MsrValue = MsrValue & ~((UINT64)BIT7);
LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);
}
/**
* Reload microcode patch after memory is initialized.
*
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
ReloadMicrocodePatchAfterMemInit (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
LoadMicrocodePatch (StdHeader);
}
/**
* Performs CPU related initialization at the recovery entry point
*
* This function processes the MSR and PCI register tables.
*
* @param[in] CpuRecoveryParams Required input parameters for recovery CPU
* initialization.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
AmdCpuRecovery (
IN AMD_CPU_RECOVERY_PARAMS *CpuRecoveryParams
)
{
SetRegistersFromTables (&CpuRecoveryParams->PlatformConfig, &CpuRecoveryParams->StdHeader);
LoadMicrocodePatch (&CpuRecoveryParams->StdHeader);
return (AGESA_SUCCESS);
}
/**
* Performs CPU related initialization at the recovery entry point
*
* This function processes the MSR and PCI register tables.
*
* @param[in] CpuRecoveryParams Required input parameters for recovery CPU
* initialization.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
AmdCpuRecovery (
IN AMD_CPU_RECOVERY_PARAMS *CpuRecoveryParams
)
{
SetRegistersFromTablesAtGivenTimePoint ((VOID *) &CpuRecoveryParams->PlatformConfig, AmdRegisterTableTpBeforeApLaunch, &CpuRecoveryParams->StdHeader);
SetRegistersFromTablesAtGivenTimePoint ((VOID *) &CpuRecoveryParams->PlatformConfig, AmdRegisterTableTpAfterApLaunch, &CpuRecoveryParams->StdHeader);
LoadMicrocodePatch (&CpuRecoveryParams->StdHeader);
return (AGESA_SUCCESS);
}
/**
* Update microcode patch in current processor for Family16h ML.
*
* This function acts as a wrapper for calling the LoadMicrocodePatch
* routine at AmdInitEarly.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[in] EarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F16MlLoadMicrocodePatchAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
if (!IsFeatureEnabled (C6Cstate, &EarlyParams->PlatformConfig, StdHeader)) {
AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);
LoadMicrocodePatch (StdHeader);
}
}
/**
* Performs CPU related initialization at the recovery entry point
*
* This function processes the MSR and PCI register tables.
*
* @param[in] CpuRecoveryParams Required input parameters for recovery CPU
* initialization.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
AmdCpuRecovery (
IN AMD_CPU_RECOVERY_PARAMS *CpuRecoveryParams
)
{
UINT8 i;
CPU_LOGICAL_ID CpuLogicalId;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
REGISTER_TABLE **RegisterTableList[2];
REGISTER_TABLE **RegisterTable;
TABLE_CORE_SELECTOR Selector;
REGISTER_TABLE **TableHandle;
GetLogicalIdOfCurrentCore (&CpuLogicalId, &CpuRecoveryParams->StdHeader);
GetCpuServicesFromLogicalId (&CpuLogicalId, &FamilySpecificServices, &CpuRecoveryParams->StdHeader);
RegisterTableList[0] = FamilySpecificServices->RegisterTableListBeforeApLaunch;
RegisterTableList[1] = FamilySpecificServices->RegisterTableListAfterApLaunch;
for (i = 0; i < 2; i++) {
for (Selector = AllCores; Selector < TableCoreSelectorMax; Selector++) {
if (IsCoreSelector (Selector, &CpuRecoveryParams->StdHeader)) {
// If the current core is the selected type of core, work the table list for tables for that type of core.
TableHandle = NULL;
RegisterTable = GetNextRegisterTable (Selector, RegisterTableList[i], &TableHandle, &CpuRecoveryParams->StdHeader);
while (*RegisterTable != NULL) {
SetRegistersFromTable (&CpuRecoveryParams->PlatformConfig, RegisterTable, &CpuRecoveryParams->StdHeader);
RegisterTable = GetNextRegisterTable (Selector, RegisterTableList[i], &TableHandle, &CpuRecoveryParams->StdHeader);
}
} else {
// Once a selector does not match the current core, quit looking.
break;
}
}
}
LoadMicrocodePatch (&CpuRecoveryParams->StdHeader);
return (AGESA_SUCCESS);
}
/**
* Reload microcode patch for a family 14h CPU after memory is initialized.
*
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F14ReloadMicrocodePatchAfterMemInit (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrValue;
// To load a microcode patch while using the cache as general storage,
// the following steps are followed:
// 1. Program MSRC001_102B[L2AllocDcFlushVictim]=1.
// 2. Load the microcode patch.
// 3. Program MSRC001_102B[L2AllocDcFlushVictim]=0.
LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
MsrValue = MsrValue | BIT7;
LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);
// Reload microcode patches.
LoadMicrocodePatch (StdHeader);
LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
MsrValue = MsrValue & ~((UINT64)BIT7);
LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);
}
