static void enable_macepci_irq(unsigned int irq) { macepci_mask |= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ); mace->pci.control = macepci_mask; crime_mask |= 1 << (irq - CRIME_IRQ_BASE); crime->imask = crime_mask; }
static void enable_macepci_irq(struct irq_data *d) { macepci_mask |= MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ); mace->pci.control = macepci_mask; crime_mask |= 1 << (d->irq - CRIME_IRQ_BASE); crime->imask = crime_mask; }
static void enable_macepci_irq(unsigned int irq) { unsigned long flags; spin_lock_irqsave(&ip32_irq_lock, flags); macepci_mask |= MACEPCI_CONTROL_INT(irq - 9); mace->pci.control = macepci_mask; crime_mask |= 1 << (irq - 1); crime->imask = crime_mask; spin_unlock_irqrestore(&ip32_irq_lock, flags); }
static void enable_macepci_irq(unsigned int irq) { u32 mace_mask; u64 crime_mask; unsigned long flags; save_and_cli(flags); mace_mask = mace_read_32(MACEPCI_CONTROL); mace_mask |= MACEPCI_CONTROL_INT(irq - 9); mace_write_32(MACEPCI_CONTROL, mace_mask); /* * In case the CRIME interrupt isn't enabled, we must enable it; * however, we never disable interrupts at that level. */ crime_mask = crime_read_64(CRIME_INT_MASK); crime_mask |= 1 << (irq - 1); crime_write_64(CRIME_INT_MASK, crime_mask); restore_flags(flags); }