static int __init armctrl_of_init(struct device_node *node,
struct device_node *parent)
{
void __iomem *base;
int irq, b, i;
base = of_iomap(node, 0);
if (!base)
panic("%s: unable to map IC registers\n",
node->full_name);
intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
&armctrl_ops, NULL);
if (!intc.domain)
panic("%s: unable to create IRQ domain\n", node->full_name);
for (b = 0; b < NR_BANKS; b++) {
intc.pending[b] = base + reg_pending[b];
intc.enable[b] = base + reg_enable[b];
intc.disable[b] = base + reg_disable[b];
for (i = 0; i < bank_irqs[b]; i++) {
irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
BUG_ON(irq <= 0);
irq_set_chip_and_handler(irq, &armctrl_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}
set_handle_irq(bcm2835_handle_irq);
return 0;
}
static u32 bcm283x_intc_active_irq(u32 cpu_irq_no)
{
register u32 stat, hwirq;
if ((stat = vmm_readl(intc.pending[0]))) {
if (stat & BANK0_HWIRQ_MASK) {
stat = stat & BANK0_HWIRQ_MASK;
hwirq = MAKE_HWIRQ(0, ffs(stat) - 1);
} else if (stat & SHORTCUT1_MASK) {
stat = (stat & SHORTCUT1_MASK) >> SHORTCUT_SHIFT;
hwirq = MAKE_HWIRQ(1, shortcuts[ffs(stat) - 1]);
} else if (stat & SHORTCUT2_MASK) {
static int __init armctrl_of_init(struct device_node *node,
struct device_node *parent,
bool is_2836)
{
void __iomem *base;
int irq, b, i;
base = of_iomap(node, 0);
if (!base)
panic("%s: unable to map IC registers\n",
node->full_name);
intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
&armctrl_ops, NULL);
if (!intc.domain)
panic("%s: unable to create IRQ domain\n", node->full_name);
for (b = 0; b < NR_BANKS; b++) {
intc.pending[b] = base + reg_pending[b];
intc.enable[b] = base + reg_enable[b];
intc.disable[b] = base + reg_disable[b];
for (i = 0; i < bank_irqs[b]; i++) {
irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
BUG_ON(irq <= 0);
irq_set_chip_and_handler(irq, &armctrl_chip,
handle_level_irq);
irq_set_probe(irq);
}
}
if (is_2836) {
int parent_irq = irq_of_parse_and_map(node, 0);
if (!parent_irq) {
panic("%s: unable to get parent interrupt.\n",
node->full_name);
}
irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
} else {
set_handle_irq(bcm2835_handle_irq);
}
return 0;
}
static void armctrl_handle_bank(int bank, struct pt_regs *regs)
{
u32 stat, irq;
while ((stat = readl_relaxed(intc.pending[bank]))) {
irq = MAKE_HWIRQ(bank, ffs(stat) - 1);
handle_IRQ(irq_linear_revmap(intc.domain, irq), regs);
}
}
static u32 get_next_armctrl_hwirq(void)
{
u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;
if (stat == 0)
return ~0;
else if (stat & BANK0_HWIRQ_MASK)
return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
else if (stat & SHORTCUT1_MASK)
return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
else if (stat & SHORTCUT2_MASK)
return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
else if (stat & BANK1_HWIRQ)
return armctrl_translate_bank(1);
else if (stat & BANK2_HWIRQ)
return armctrl_translate_bank(2);
else
BUG();
}
static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq, unsigned int *out_type)
{
if (WARN_ON(intsize != 2))
return -EINVAL;
if (WARN_ON(intspec[0] >= NR_BANKS))
return -EINVAL;
if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
return -EINVAL;
if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
return -EINVAL;
*out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
*out_type = IRQ_TYPE_NONE;
return 0;
}
};
static u32 bcm283x_intc_active_irq(u32 cpu_irq_no)
{
register u32 stat, hwirq;
if ((stat = vmm_readl(intc.pending[0]))) {
if (stat & BANK0_HWIRQ_MASK) {
stat = stat & BANK0_HWIRQ_MASK;
hwirq = MAKE_HWIRQ(0, ffs(stat) - 1);
} else if (stat & SHORTCUT1_MASK) {
stat = (stat & SHORTCUT1_MASK) >> SHORTCUT_SHIFT;
hwirq = MAKE_HWIRQ(1, shortcuts[ffs(stat) - 1]);
} else if (stat & SHORTCUT2_MASK) {
stat = (stat & SHORTCUT2_MASK) >> SHORTCUT_SHIFT;
hwirq = MAKE_HWIRQ(2, shortcuts[ffs(stat) - 1]);
} else if (stat & BANK1_HWIRQ) {
stat = vmm_readl(intc.pending[1]);
hwirq = MAKE_HWIRQ(1, ffs(stat) - 1);
} else if (stat & BANK2_HWIRQ) {
stat = vmm_readl(intc.pending[2]);
hwirq = MAKE_HWIRQ(2, ffs(stat) - 1);
} else {
BUG();
}
} else {
hwirq = UINT_MAX;
}
return vmm_host_irqdomain_find_mapping(intc.domain, hwirq);
}
static u32 armctrl_translate_bank(int bank)
{
u32 stat = readl_relaxed(intc.pending[bank]);
return MAKE_HWIRQ(bank, ffs(stat) - 1);
}
