#define MALI_GP_IRQ EXYNOS4_IRQ_GP_3D
#define MALI_PP0_IRQ EXYNOS4_IRQ_PP0_3D
#define MALI_PP1_IRQ EXYNOS4_IRQ_PP1_3D
#define MALI_PP2_IRQ EXYNOS4_IRQ_PP2_3D
#define MALI_PP3_IRQ EXYNOS4_IRQ_PP3_3D
#define MALI_GP_MMU_IRQ EXYNOS4_IRQ_GPMMU_3D
#define MALI_PP0_MMU_IRQ EXYNOS4_IRQ_PPMMU0_3D
#define MALI_PP1_MMU_IRQ EXYNOS4_IRQ_PPMMU1_3D
#define MALI_PP2_MMU_IRQ EXYNOS4_IRQ_PPMMU2_3D
#define MALI_PP3_MMU_IRQ EXYNOS4_IRQ_PPMMU3_3D
static struct resource mali_gpu_resources[] =
{
MALI_GPU_RESOURCES_MALI400_MP4(0x13000000,
MALI_GP_IRQ, MALI_GP_MMU_IRQ,
MALI_PP0_IRQ, MALI_PP0_MMU_IRQ,
MALI_PP1_IRQ, MALI_PP1_MMU_IRQ,
MALI_PP2_IRQ, MALI_PP2_MMU_IRQ,
MALI_PP3_IRQ, MALI_PP3_MMU_IRQ)
};
static struct dev_pm_ops mali_gpu_device_type_pm_ops =
{
.suspend = mali_os_suspend,
.resume = mali_os_resume,
.freeze = mali_os_freeze,
.thaw = mali_os_thaw,
#ifdef CONFIG_PM_RUNTIME
.runtime_suspend = mali_runtime_suspend,
.runtime_resume = mali_runtime_resume,
.runtime_idle = mali_runtime_idle,
#endif
#ifndef CONFIG_MALI400_4_PP
static struct resource meson_mali_resources[] =
{
MALI_GPU_RESOURCES_MALI400_MP2(0xd0060000,
INT_MALI_GP, INT_MALI_GP_MMU,
INT_MALI_PP, INT_MALI_PP_MMU,
INT_MALI_PP2, INT_MALI_PP2_MMU)
};
#else
static struct resource meson_mali_resources[] =
{
MALI_GPU_RESOURCES_MALI400_MP4(0xd0060000,
INT_MALI_GP, INT_MALI_GP_MMU,
INT_MALI_PP, INT_MALI_PP_MMU,
INT_MALI_PP2, INT_MALI_PP2_MMU,
INT_MALI_PP3, INT_MALI_PP3_MMU,
INT_MALI_PP4, INT_MALI_PP4_MMU
)
};
#endif
#elif MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
int static_pp_mmu_cnt;
#define INT_MALI_GP (48+32)
#define INT_MALI_GP_MMU (49+32)
#define INT_MALI_PP (50+32)
#define INT_MALI_PP_MMU (51+32)
#define INT_MALI_PP2_MMU ( 6+32)
