//*****************************************************************************
//
//! \InterruptTestTerm
//! Performs termination processing.
//! This function is called once the test completes to tidy up as required.
//!
//! \param None.
//!
//! \return None.
//
//*****************************************************************************
static void
InterruptTestTerm(void)
{
//
// Unhook our interrupt handlers if they are still hooked.
//
TimerIntUnregister(TIMERA0_BASE, TIMER_A);
TimerIntUnregister(TIMERA1_BASE, TIMER_A);
TimerIntUnregister(TIMERA2_BASE, TIMER_A);
//
// Restore the original timer interrupt priorities and priority group
// settings.
//
MAP_IntPriorityGroupingSet(g_lPriorityGrouping);
MAP_IntPrioritySet(INT_TIMERA0A, (unsigned char)g_ulTimer0APriority);
MAP_IntPrioritySet(INT_TIMERA1A, (unsigned char)g_ulTimer1APriority);
//
// Reset and Disable the timer blocks
//
MAP_PRCMPeripheralReset(PRCM_TIMERA0);
MAP_PRCMPeripheralReset(PRCM_TIMERA1);
MAP_PRCMPeripheralReset(PRCM_TIMERA2);
MAP_PRCMPeripheralClkDisable(PRCM_TIMERA0, PRCM_RUN_MODE_CLK);
MAP_PRCMPeripheralClkDisable(PRCM_TIMERA1, PRCM_RUN_MODE_CLK);
MAP_PRCMPeripheralClkDisable(PRCM_TIMERA2, PRCM_RUN_MODE_CLK);
}
//****************************************************************************
//
//! Implements Sleep followed by wakeup using WDT timeout
//!
//! \param none
//!
//! This function
//! 1. Implements Sleep followed by wakeup using WDT
//!
//! \return None.
//
//****************************************************************************
void PerformPRCMSleepWDTWakeup()
{
//
// Initialize the WDT
//
WDT_IF_Init(AppWDTCallBackHandler, (4 * SYS_CLK));
//
// Enable the Sleep Clock
//
MAP_PRCMPeripheralClkEnable(PRCM_WDT, PRCM_SLP_MODE_CLK);
//
// Enter SLEEP...WaitForInterrupt ARM intrinsic
//
DBG_PRINT("WDT_SLEEP: Entering Sleep\n\r");
MAP_UtilsDelay(80000);
MAP_PRCMSleepEnter();
DBG_PRINT("WDT_SLEEP: Exiting Sleep\n\r");
//
// Disable the Sleep Clock
//
MAP_PRCMPeripheralClkDisable(PRCM_WDT, PRCM_SLP_MODE_CLK);
//
// Deinitialize the WDT
//
WDT_IF_DeInit();
//
// PowerOff WDT
//
MAP_PRCMPeripheralClkDisable(PRCM_WDT, PRCM_RUN_MODE_CLK);
}
//****************************************************************************
//
//! Disables the timer PWMs
//!
//! \param none
//!
//! This function disables the timers used
//!
//! \return None.
//
//****************************************************************************
void DeInitPWMModules()
{
//
// Disable the peripherals
//
MAP_TimerDisable(TIMERA2_BASE, TIMER_B);
MAP_TimerDisable(TIMERA3_BASE, TIMER_A);
MAP_TimerDisable(TIMERA3_BASE, TIMER_B);
MAP_PRCMPeripheralClkDisable(PRCM_TIMERA2, PRCM_RUN_MODE_CLK);
MAP_PRCMPeripheralClkDisable(PRCM_TIMERA3, PRCM_RUN_MODE_CLK);
}
/// \method deinit()
/// Turn off the UART bus.
STATIC mp_obj_t pyb_uart_deinit(mp_obj_t self_in) {
pyb_uart_obj_t *self = self_in;
uint uartPerh;
switch (self->uart_id) {
case PYB_UART_0:
uartPerh = PRCM_UARTA0;
break;
case PYB_UART_1:
uartPerh = PRCM_UARTA1;
break;
default:
return mp_const_none;
}
self->enabled = false;
MAP_UARTIntDisable(self->reg, UART_INT_RX | UART_INT_RT);
MAP_UARTIntClear(self->reg, UART_INT_RX | UART_INT_RT);
MAP_UARTIntUnregister(self->reg);
MAP_UARTDisable(self->reg);
MAP_PRCMPeripheralClkDisable(uartPerh, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
return mp_const_none;
}
//****************************************************************************
//
//! Implements Sleep followed by wakeup using GPT timeout
//!
//! \param none
//!
//! This function
//! 1. Implements Sleep followed by wakeup using GPT
//!
//! \return None.
//
//****************************************************************************
void PerformPRCMSleepGPTWakeup()
{
//
// Power On the GPT along with sleep clock
//
MAP_PRCMPeripheralClkEnable(PRCM_TIMERA0, PRCM_RUN_MODE_CLK);
//
// Initialize the GPT as One Shot timer
//
Timer_IF_Init(PRCM_TIMERA0, TIMERA0_BASE, TIMER_CFG_ONE_SHOT, TIMER_BOTH, 0);
Timer_IF_IntSetup(TIMERA0_BASE, TIMER_BOTH, AppGPTCallBackHandler);
//
// Start timer with value in mSec
//
Timer_IF_Start(TIMERA0_BASE, TIMER_BOTH, 4000);
//
// Enable the Sleep Clock
//
MAP_PRCMPeripheralClkEnable(PRCM_TIMERA0, PRCM_SLP_MODE_CLK);
//
// Enter SLEEP...WaitForInterrupt ARM intrinsic
//
DBG_PRINT("GPT_SLEEP: Entering Sleep\n\r");
MAP_UtilsDelay(80000);
MAP_PRCMSleepEnter();
DBG_PRINT("GPT_SLEEP: Exiting Sleep\n\r");
//
// Disable the Sleep Clock
//
MAP_PRCMPeripheralClkDisable(PRCM_TIMERA0, PRCM_SLP_MODE_CLK);
//
// Deinitialize the GPT
//
Timer_IF_Stop(TIMERA0_BASE, TIMER_BOTH);
Timer_IF_DeInit(TIMERA0_BASE, TIMER_BOTH);
//
// PowerOff GPT
//
MAP_PRCMPeripheralClkDisable(PRCM_TIMERA0, PRCM_RUN_MODE_CLK);
}
void sj_i2c_close(i2c_connection conn) {
struct i2c_state *c = (struct i2c_state *) conn;
MAP_PRCMPeripheralClkDisable(PRCM_I2CA0, PRCM_RUN_MODE_CLK);
MAP_PinModeSet(c->sda_pin, c->sda_pin_mode);
MAP_PinConfigSet(c->sda_pin, c->sda_pin_strength, c->sda_pin_type);
MAP_PinModeSet(c->scl_pin, c->scl_pin_mode);
MAP_PinConfigSet(c->scl_pin, c->scl_pin_strength, c->scl_pin_type);
free(c);
}
STATIC mp_obj_t pyb_sd_deinit (mp_obj_t self_in) {
pybsd_obj_t *self = self_in;
// disable the peripheral
self->enabled = false;
MAP_PRCMPeripheralClkDisable(PRCM_SDHOST, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
// de-initialze the sd card at diskio level
sd_disk_deinit();
// unregister it from the sleep module
pyb_sleep_remove (self);
return mp_const_none;
}
//****************************************************************************
//
//! \brief This function gates the clk for the peripheral given as argument
//!
//! \param hw_module is the pointer to the module structure for a peripheral
//! \param Sx is the power state of the peripheral after gating the clk
//!
//! \return 0
//
//****************************************************************************
int clk_dsbl_op(struct soc_module *hw_module, enum soc_pm Sx)
{
switch(Sx) {
case e_pm_S0:
case e_pm_S1:
MAP_PRCMPeripheralClkDisable(hw_module->module_id,
PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK);
break;
case e_pm_S2:
MAP_PRCMPeripheralClkDisable(hw_module->module_id,
PRCM_DSLP_MODE_CLK);
break;
default: break;
}
return 0;
}
void cc3200_hash_update(struct cc3200_hash_ctx *ctx, const uint8_t *data,
uint32_t len) {
if (ctx->block_len > 0) {
uint32_t block_remain = CC3200_HASH_BLOCK_SIZE - ctx->block_len;
if (block_remain > len) block_remain = len;
memcpy(ctx->block + ctx->block_len, data, block_remain);
ctx->block_len += block_remain;
data += block_remain;
len -= block_remain;
if (ctx->block_len < CC3200_HASH_BLOCK_SIZE) return;
}
const uint32_t to_hash =
(((uint32_t) ctx->block_len) + len) & ~(CC3200_HASH_BLOCK_SIZE - 1);
if (to_hash > 0) {
vPortEnterCritical();
init_engine(ctx, 0);
HWREG(SHAMD5_BASE + SHAMD5_O_LENGTH) = to_hash;
if (ctx->block_len == CC3200_HASH_BLOCK_SIZE) {
while (
!(HWREG(SHAMD5_BASE + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY))
;
uint32_t *p = (uint32_t *) ctx->block;
for (int i = 0; i < CC3200_HASH_BLOCK_SIZE; i += 4) {
HWREG(SHAMD5_BASE + SHAMD5_O_DATA0_IN + i) = *p++;
}
}
while (len >= CC3200_HASH_BLOCK_SIZE) {
while (
!(HWREG(SHAMD5_BASE + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY))
;
for (int i = 0; i < CC3200_HASH_BLOCK_SIZE; i += 4) {
HWREG(SHAMD5_BASE + SHAMD5_O_DATA0_IN + i) = *((uint32_t *) data);
data += 4;
len -= 4;
}
}
while (!(HWREG(SHAMD5_BASE + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY))
;
MAP_SHAMD5ResultRead(SHAMD5_BASE, (uint8_t *) ctx->digest);
/* Must read count register to finish the round. */
HWREG(SHAMD5_BASE + SHAMD5_O_DIGEST_COUNT);
MAP_PRCMPeripheralClkDisable(PRCM_DTHE, PRCM_RUN_MODE_CLK);
vPortExitCritical();
}
memcpy(ctx->block, data, len);
ctx->block_len = len;
}
/*!
\brief closes an opened spi communication port
\param fd - file descriptor of an opened SPI channel
\return upon successful completion, the function shall return 0.
Otherwise, -1 shall be returned
\sa spi_Open
\note
\warning
*/
int spi_Close(Fd_t fd)
{
unsigned long ulBase = LSPI_BASE;
g_SpiFd = 0;
//Disable Chip Select
MAP_SPICSDisable(LSPI_BASE);
//Disable SPI Channel
MAP_SPIDisable(ulBase);
// Reset SPI
MAP_SPIReset(ulBase);
// Disable SPI Peripheral
MAP_PRCMPeripheralClkDisable(PRCM_LSPI,PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
return 0;
}
void cc3200_hash_final(struct cc3200_hash_ctx *ctx, uint8_t *digest) {
vPortEnterCritical();
init_engine(ctx, SHAMD5_MODE_CLOSE_HASH);
HWREG(SHAMD5_BASE + SHAMD5_O_LENGTH) = ctx->block_len;
int bl = ctx->block_len;
int i = 0;
uint32_t *p = (uint32_t *) ctx->block;
while (bl - i > 4) {
HWREG(SHAMD5_BASE + SHAMD5_O_DATA0_IN + i) = *p++;
i += 4;
}
if (i < bl) {
for (int j = bl; j % 4 != 0; j++) ctx->block[j] = 0;
HWREG(SHAMD5_BASE + SHAMD5_O_DATA0_IN + i) = *p;
}
while (!(HWREG(SHAMD5_BASE + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY))
;
MAP_SHAMD5ResultRead(SHAMD5_BASE, digest);
/* Must read count register to finish the round. */
HWREG(SHAMD5_BASE + SHAMD5_O_DIGEST_COUNT);
MAP_PRCMPeripheralClkDisable(PRCM_DTHE, PRCM_RUN_MODE_CLK);
vPortExitCritical();
}
/*!
\brief closes an opened spi communication port
\param fd - file descriptor of an opened SPI channel
\return upon successful completion, the function shall return 0.
Otherwise, -1 shall be returned
\sa spi_Open
\note
\warning
*/
int spi_Close(Fd_t fd)
{
unsigned long ulBase = LSPI_BASE;
g_SpiFd = 0;
if(g_ucDMAEnabled)
{
#ifdef SL_PLATFORM_MULTI_THREADED
osi_InterruptDeRegister(INT_LSPI);
osi_MsgQDelete(&DMAMsgQ);
#else
MAP_SPIIntUnregister(ulBase);
g_cDummy = 0;
#endif
MAP_SPIFIFODisable(ulBase,SPI_RX_FIFO);
MAP_SPIFIFODisable(ulBase,SPI_TX_FIFO);
MAP_SPIDmaDisable(ulBase,SPI_RX_DMA);
MAP_SPIDmaDisable(ulBase,SPI_TX_DMA);
}
//Disable Chip Select
MAP_SPICSDisable(LSPI_BASE);
//Disable SPI Channel
MAP_SPIDisable(ulBase);
// Reset SPI
MAP_SPIReset(ulBase);
// Enable SPI Peripheral
MAP_PRCMPeripheralClkDisable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK);
return 0;
}
//*****************************************************************************
//
//! \brief Connecting to a WLAN Accesspoint
//! This function connects to the required AP (SSID_NAME).
//! This code example assumes the AP doesn't use WIFI security.
//! The function will return only once we are connected
//! and have acquired IP address
//!
//! \param[in] None
//!
//! \return 0 means success, -1 means failure
//!
//! \note
//!
//! \warning If the WLAN connection fails or we don't aquire an IP address,
//! We will be stuck in this function forever.
//
//*****************************************************************************
int WlanConnect()
{
int iRetCode = 0;
int iRetVal = 0;
int iConnect = 0;
unsigned char ucQueueMsg = 0;
SlSecParams_t secParams;
secParams.Key = (signed char *)SECURITY_KEY;
secParams.KeyLen = strlen((const char *)secParams.Key);
secParams.Type = SECURITY_TYPE;
//
// Set up the watchdog interrupt handler.
//
WDT_IF_Init(WatchdogIntHandler, MILLISECONDS_TO_TICKS(WD_PERIOD_MS));
/* Enabling the Sleep clock for the Watch Dog Timer*/
MAP_PRCMPeripheralClkEnable(PRCM_WDT, PRCM_SLP_MODE_CLK);
g_ucFeedWatchdog = 1;
g_ucWdogCount = 0;
while(!(ucQueueMsg & (EVENT_IP_ACQUIRED|CONNECTION_FAILED)))
{
UART_PRINT("Trying to connect to AP: ");
UART_PRINT(SSID_NAME);
UART_PRINT("\n\r");
sl_WlanConnect((signed char *)SSID_NAME,
strlen((const char *)SSID_NAME), 0, &secParams, 0);
iConnect = 0;
do{
osi_MsgQRead(&g_tConnection, &ucQueueMsg, OSI_WAIT_FOREVER);
switch(ucQueueMsg)
{
case EVENT_CONNECTION:
iConnect = 1;
break;
case EVENT_IP_ACQUIRED:
iRetVal = 0;
break;
case WDOG_EXPIRED:
//
// disconnect from the Access Point
//
if(iConnect)
{
WlanDisconnect();
}
//
// stop the simplelink with reqd. timeout value (30 ms)
//
sl_Stop(SL_STOP_TIMEOUT);
UART_PRINT("sl stop\n\r");
MAP_UtilsDelay(8000);
//
// starting the simplelink
//
sl_Start(NULL, NULL, NULL);
UART_PRINT("sl start\n\r");
break;
case EVENT_DISCONNECTION:
iConnect = 0;
break;
case CONNECTION_FAILED:
iRetVal = -1;
break;
default:
UART_PRINT("unexpected event\n\r");
break;
}
}while(ucQueueMsg == (unsigned char)EVENT_CONNECTION);
}
iRetCode = MAP_WatchdogRunning(WDT_BASE);
if(iRetCode)
{
WDT_IF_DeInit();
MAP_PRCMPeripheralClkDisable(PRCM_WDT, PRCM_RUN_MODE_CLK);
}
ASSERT_ON_ERROR(iRetVal);
return(iRetVal);
}
