static void ReadSPI(unsigned char* pIn,unsigned char* pOut,unsigned long ulLen) { // Reset SPI MAP_SPIReset(GSPI_BASE); // Configure SPI interface MAP_SPIConfigSetExpClk(GSPI_BASE,MAP_PRCMPeripheralClockGet(PRCM_GSPI), 20000000,SPI_MODE_MASTER,SPI_SUB_MODE_3, (SPI_HW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_ON | SPI_CS_ACTIVEHIGH | SPI_WL_8)); // Enable SPI for communication MAP_SPIEnable(GSPI_BASE); READ_FROM_SPI; unsigned char tmpbuf[2]; MAP_SPITransfer(GSPI_BASE, pOut, pIn, ulLen, SPI_CS_ENABLE|SPI_CS_DISABLE); MAP_SPIDisable(GSPI_BASE); }
int main() { interrupt_count = 0; transfer_count = 0; tx_count = 0; rx_count = 0; uint32_t output_count = 0; uint32_t sum = 0; init(); // initialize buffers with some known value memset(tx_buffer,0x55,sizeof(tx_buffer)); memset(rx_buffer,0x22,sizeof(rx_buffer)); // configure SPI MAP_SPIReset(GSPI_BASE); MAP_SPIConfigSetExpClk(GSPI_BASE,MAP_PRCMPeripheralClockGet(PRCM_GSPI), SPI_IF_BIT_RATE,SPI_MODE_SLAVE,SPI_SUB_MODE_0, (SPI_HW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF | SPI_CS_ACTIVEHIGH | SPI_WL_8)); MAP_SPIIntRegister(GSPI_BASE,interrupt_handler); MAP_SPIIntEnable(GSPI_BASE,SPI_INT_RX_FULL|SPI_INT_TX_EMPTY); MAP_SPIEnable(GSPI_BASE); Message("Enabled SPI Interface in Slave Mode!\n\r"); Message("Starting while\n\r"); while(1) { memcpy(tx_buffer,rx_buffer,TR_BUFF_SIZE); // here we could also change the tx_buffer // e.g. tx_buffer[TR_BUFF_SIZE - 1] = 18; sum = 0; if(output_count < transfer_count) { for(int i = 0; i < TR_BUFF_SIZE; i++) { sum += rx_buffer[i]; } Report("The sum in the Rx buffer is: %d\n\r",sum); Report("Checksum Rx buffer is: 0x%02x\n\r",crc(rx_buffer)); Report("interrupt: %d, tx: %d, rx: %d, transfer: %d\n\r",interrupt_count,tx_count,rx_count, transfer_count); Message("TX-"); print_buffer(tx_buffer,TR_BUFF_SIZE); Message("RX-"); print_buffer(rx_buffer,TR_BUFF_SIZE); output_count++; } } return 0; }
void spi_transfer(uint8_t* tx, uint8_t* rx) { MAP_SPIDisable(GSPI_BASE); SetupTransfer(UDMA_CH30_GSPI_RX,UDMA_MODE_BASIC,DMA_SIZE, UDMA_SIZE_8,UDMA_ARB_1, (void *)(GSPI_BASE + MCSPI_O_RX0),UDMA_SRC_INC_NONE, rx,UDMA_DST_INC_8); SetupTransfer(UDMA_CH31_GSPI_TX,UDMA_MODE_BASIC,DMA_SIZE, UDMA_SIZE_8,UDMA_ARB_1, tx,UDMA_SRC_INC_8, (void *)(GSPI_BASE + MCSPI_O_TX0),UDMA_DST_INC_NONE); MAP_SPIEnable(GSPI_BASE); }
void SampleInit(void) { /* //UDMAInit(); // Reset SPI //MAP_SPIReset(GSPI_BASE); MAP_SPIConfigSetExpClk(GSPI_BASE,MAP_PRCMPeripheralClockGet(PRCM_GSPI), SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_3, (SPI_HW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_ON| SPI_CS_ACTIVELOW | SPI_WL_8)); MAP_SPIEnable(GSPI_BASE); MAP_SPICSEnable(GSPI_BASE); MAP_SPIFIFOEnable(GSPI_BASE,SPI_RX_FIFO); MAP_SPIFIFOEnable(GSPI_BASE,SPI_TX_FIFO); SPIFIFOLevelSet(GSPI_BASE,1,1); MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMARX|SPI_INT_DMATX); //MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMATX); //MAP_SPIIntRegister(GSPI_BASE,DMAIntHandler); osi_InterruptRegister(INT_GSPI, DMAIntHandler, 32); */ UDMAInit(); MAP_SPIConfigSetExpClk(GSPI_BASE,MAP_PRCMPeripheralClockGet(PRCM_GSPI), SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_3, (SPI_HW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_ON| SPI_CS_ACTIVEHIGH | SPI_WL_8)); MAP_SPIEnable(GSPI_BASE); MAP_SPICSEnable(GSPI_BASE); MAP_SPIFIFOEnable(GSPI_BASE,SPI_RX_FIFO); MAP_SPIFIFOEnable(GSPI_BASE,SPI_TX_FIFO); SPIFIFOLevelSet(GSPI_BASE,1,1); MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMARX); //MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMATX); //MAP_SPIIntRegister(GSPI_BASE,DMAIntHandler); osi_InterruptRegister(INT_GSPI, DMAIntHandler, 32); }
/* * ======== SPICC3200DMA_transfer ======== * @pre Function assumes that handle and transaction is not NULL */ bool SPICC3200DMA_transfer(SPI_Handle handle, SPI_Transaction *transaction) { uintptr_t key; SPICC3200DMA_Object *object = handle->object; SPICC3200DMA_HWAttrs const *hwAttrs = handle->hwAttrs; /* This is a limitation by the micro DMA controller */ if ((transaction->count == 0) || (transaction->count > 1024) || !(transaction->rxBuf || transaction->txBuf) || (!(transaction->rxBuf && transaction->txBuf) && !hwAttrs->scratchBufPtr)) { return (false); } /* Check if a transfer is in progress */ key = HwiP_disable(); if (object->transaction) { HwiP_restore(key); DebugP_log1("SPI:(%p) ERROR! Transaction still in progress", ((SPICC3200DMA_HWAttrs const *)(handle->hwAttrs))->baseAddr); return (false); } else { object->transaction = transaction; HwiP_restore(key); } /* Set constraints to guarantee transaction */ Power_setConstraint(PowerCC3200_DISALLOW_DEEPSLEEP); SPICC3200DMA_configDMA(handle, transaction); MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMARX | SPI_INT_DMATX | SPI_INT_EOW); MAP_SPIIntEnable(hwAttrs->baseAddr, SPI_INT_DMARX | SPI_INT_DMATX | SPI_INT_EOW); MAP_SPIEnable(hwAttrs->baseAddr); MAP_SPICSEnable(hwAttrs->baseAddr); if (object->transferMode == SPI_MODE_BLOCKING) { DebugP_log1("SPI:(%p) transfer pending on transferComplete semaphore", ((SPICC3200DMA_HWAttrs const *)(handle->hwAttrs))->baseAddr); SemaphoreP_pend(object->transferComplete, SemaphoreP_WAIT_FOREVER); } return (true); }
STATIC void pyb_sleep_flash_powerdown (void) { uint32_t status; // Enable clock for SSPI module MAP_PRCMPeripheralClkEnable(PRCM_SSPI, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); // Reset SSPI at PRCM level and wait for reset to complete MAP_PRCMPeripheralReset(PRCM_SSPI); while(!MAP_PRCMPeripheralStatusGet(PRCM_SSPI)); // Reset SSPI at module level MAP_SPIReset(SSPI_BASE); // Configure SSPI module MAP_SPIConfigSetExpClk (SSPI_BASE, PRCMPeripheralClockGet(PRCM_SSPI), 20000000, SPI_MODE_MASTER,SPI_SUB_MODE_0, (SPI_SW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF | SPI_CS_ACTIVELOW | SPI_WL_8)); // Enable SSPI module MAP_SPIEnable(SSPI_BASE); // Enable chip select for the spi flash. MAP_SPICSEnable(SSPI_BASE); // Wait for the spi flash do { // Send the status register read instruction and read back a dummy byte. MAP_SPIDataPut(SSPI_BASE, SPIFLASH_INSTR_READ_STATUS); MAP_SPIDataGet(SSPI_BASE, &status); // Write a dummy byte then read back the actual status. MAP_SPIDataPut(SSPI_BASE, 0xFF); MAP_SPIDataGet(SSPI_BASE, &status); } while ((status & 0xFF) == SPIFLASH_STATUS_BUSY); // Disable chip select for the spi flash. MAP_SPICSDisable(SSPI_BASE); // Start another CS enable sequence for Power down command. MAP_SPICSEnable(SSPI_BASE); // Send Deep Power Down command to spi flash MAP_SPIDataPut(SSPI_BASE, SPIFLASH_INSTR_DEEP_POWER_DOWN); // Disable chip select for the spi flash. MAP_SPICSDisable(SSPI_BASE); }
void SPIInit(){ // Reset SPI MAP_SPIReset(GSPI_BASE); //Enables the transmit and/or receive FIFOs. //Base address is GSPI_BASE, SPI_TX_FIFO || SPI_RX_FIFO are the FIFOs to be enabled MAP_SPIFIFOEnable(GSPI_BASE, SPI_TX_FIFO || SPI_RX_FIFO); // Configure SPI interface MAP_SPIConfigSetExpClk(GSPI_BASE,MAP_PRCMPeripheralClockGet(PRCM_GSPI), SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_0, (SPI_SW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF | SPI_CS_ACTIVELOW | SPI_WL_8)); // Enable SPI for communication MAP_SPIEnable(GSPI_BASE); }
static void Command(bool bPowerEn, unsigned char ucZoom, unsigned char ucGain, unsigned char ucLine) { unsigned short usCommand = 0x0000; if (bPowerEn) usCommand |= 0x8000; usCommand |= (ucZoom & 0x03) << 6; //usCommand |= (ucGain & 0x3F); usCommand |= (ucGain & 0x7E) >> 1; TRACE("Gain: %d\r\n",ucGain); usCommand |= (ucLine & 0x7F) << 8; // Reset SPI MAP_SPIReset(GSPI_BASE); // Configure SPI interface MAP_SPIConfigSetExpClk(GSPI_BASE,MAP_PRCMPeripheralClockGet(PRCM_GSPI), 20000000,SPI_MODE_MASTER,SPI_SUB_MODE_0, (SPI_SW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_ON | SPI_CS_ACTIVEHIGH | SPI_WL_8)); // Enable SPI for communication MAP_SPIEnable(GSPI_BASE); WRITE_TO_SPI; unsigned char tmpbuf[2]; MAP_SPITransfer(GSPI_BASE, (unsigned char*)&usCommand, tmpbuf,2, SPI_CS_ENABLE|SPI_CS_DISABLE); READ_FROM_SPI; MAP_SPIDisable(GSPI_BASE); }
Fd_t spi_Open(char *ifName, unsigned long flags) { unsigned long ulBase; unsigned long ulSpiBitRate = SPI_RATE_20M; //NWP master interface ulBase = LSPI_BASE; //Enable MCSPIA2 MAP_PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); //Disable Chip Select MAP_SPICSDisable(ulBase); //Disable SPI Channel MAP_SPIDisable(ulBase); // Reset SPI MAP_SPIReset(ulBase); // // Configure SPI interface // MAP_SPIConfigSetExpClk(ulBase,MAP_PRCMPeripheralClockGet(PRCM_LSPI), ulSpiBitRate,SPI_MODE_MASTER,SPI_SUB_MODE_0, (SPI_SW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF | SPI_CS_ACTIVEHIGH | SPI_WL_32)); MAP_SPIEnable(ulBase); g_SpiFd = 1; return g_SpiFd; }
Fd_t spi_Open(char *ifName, unsigned long flags) { unsigned long ulBase; unsigned long ulSpiBitRate; tROMVersion* pRomVersion = (tROMVersion *)(ROM_VERSION_ADDR); //NWP master interface ulBase = LSPI_BASE; //Enable MCSPIA2 MAP_PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK); //Disable Chip Select MAP_SPICSDisable(ulBase); //Disable SPI Channel MAP_SPIDisable(ulBase); // Reset SPI MAP_SPIReset(ulBase); // // Configure SPI interface // if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_21 ) { ulSpiBitRate = SPI_RATE_13M; } else if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_32) { ulSpiBitRate = SPI_RATE_13M; } else if(pRomVersion->ucMinorVerNum >= ROM_VER_PG1_33) { ulSpiBitRate = SPI_RATE_20M; } MAP_SPIConfigSetExpClk(ulBase,MAP_PRCMPeripheralClockGet(PRCM_LSPI), ulSpiBitRate,SPI_MODE_MASTER,SPI_SUB_MODE_0, (SPI_SW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF | SPI_CS_ACTIVEHIGH | SPI_WL_32)); if(MAP_PRCMPeripheralStatusGet(PRCM_UDMA)) { g_ucDMAEnabled = (HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0x0) ? 1 : 0; } else { g_ucDMAEnabled = 0; } #ifdef SL_CPU_MODE g_ucDMAEnabled = 0; #endif if(g_ucDMAEnabled) { memset(g_ucDinDout,0xFF,sizeof(g_ucDinDout)); // Set DMA channel cc_UDMAChannelSelect(UDMA_CH12_LSPI_RX); cc_UDMAChannelSelect(UDMA_CH13_LSPI_TX); MAP_SPIFIFOEnable(ulBase,SPI_RX_FIFO); MAP_SPIFIFOEnable(ulBase,SPI_TX_FIFO); MAP_SPIDmaEnable(ulBase,SPI_RX_DMA); MAP_SPIDmaEnable(ulBase,SPI_TX_DMA); MAP_SPIFIFOLevelSet(ulBase,1,1); #if defined(SL_PLATFORM_MULTI_THREADED) osi_InterruptRegister(INT_LSPI, (P_OSI_INTR_ENTRY)DmaSpiSwIntHandler,INT_PRIORITY_LVL_1); MAP_SPIIntEnable(ulBase,SPI_INT_EOW); osi_MsgQCreate(&DMAMsgQ,"DMAQueue",sizeof(int),1); #else MAP_IntRegister(INT_LSPI,(void(*)(void))DmaSpiSwIntHandler); MAP_IntPrioritySet(INT_LSPI, INT_PRIORITY_LVL_1); MAP_IntEnable(INT_LSPI); MAP_SPIIntEnable(ulBase,SPI_INT_EOW); g_cDummy = 0x0; #endif } MAP_SPIEnable(ulBase); g_SpiFd = 1; return g_SpiFd; }