int main()
{
interrupt_count = 0;
transfer_count = 0;
tx_count = 0;
rx_count = 0;
uint32_t output_count = 0;
uint32_t sum = 0;
init();
// initialize buffers with some known value
memset(tx_buffer,0x55,sizeof(tx_buffer));
memset(rx_buffer,0x22,sizeof(rx_buffer));
// configure SPI
MAP_SPIReset(GSPI_BASE);
MAP_SPIConfigSetExpClk(GSPI_BASE,MAP_PRCMPeripheralClockGet(PRCM_GSPI),
SPI_IF_BIT_RATE,SPI_MODE_SLAVE,SPI_SUB_MODE_0,
(SPI_HW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_OFF |
SPI_CS_ACTIVEHIGH |
SPI_WL_8));
MAP_SPIIntRegister(GSPI_BASE,interrupt_handler);
MAP_SPIIntEnable(GSPI_BASE,SPI_INT_RX_FULL|SPI_INT_TX_EMPTY);
MAP_SPIEnable(GSPI_BASE);
Message("Enabled SPI Interface in Slave Mode!\n\r");
Message("Starting while\n\r");
while(1)
{
memcpy(tx_buffer,rx_buffer,TR_BUFF_SIZE);
// here we could also change the tx_buffer
// e.g. tx_buffer[TR_BUFF_SIZE - 1] = 18;
sum = 0;
if(output_count < transfer_count)
{
for(int i = 0; i < TR_BUFF_SIZE; i++)
{
sum += rx_buffer[i];
}
Report("The sum in the Rx buffer is: %d\n\r",sum);
Report("Checksum Rx buffer is: 0x%02x\n\r",crc(rx_buffer));
Report("interrupt: %d, tx: %d, rx: %d, transfer: %d\n\r",interrupt_count,tx_count,rx_count, transfer_count);
Message("TX-");
print_buffer(tx_buffer,TR_BUFF_SIZE);
Message("RX-");
print_buffer(rx_buffer,TR_BUFF_SIZE);
output_count++;
}
}
return 0;
}
void SampleInit(void)
{
/*
//UDMAInit();
// Reset SPI
//MAP_SPIReset(GSPI_BASE);
MAP_SPIConfigSetExpClk(GSPI_BASE,MAP_PRCMPeripheralClockGet(PRCM_GSPI),
SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_3,
(SPI_HW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_ON|
SPI_CS_ACTIVELOW |
SPI_WL_8));
MAP_SPIEnable(GSPI_BASE);
MAP_SPICSEnable(GSPI_BASE);
MAP_SPIFIFOEnable(GSPI_BASE,SPI_RX_FIFO);
MAP_SPIFIFOEnable(GSPI_BASE,SPI_TX_FIFO);
SPIFIFOLevelSet(GSPI_BASE,1,1);
MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMARX|SPI_INT_DMATX);
//MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMATX);
//MAP_SPIIntRegister(GSPI_BASE,DMAIntHandler);
osi_InterruptRegister(INT_GSPI, DMAIntHandler, 32);
*/
UDMAInit();
MAP_SPIConfigSetExpClk(GSPI_BASE,MAP_PRCMPeripheralClockGet(PRCM_GSPI),
SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_3,
(SPI_HW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_ON|
SPI_CS_ACTIVEHIGH |
SPI_WL_8));
MAP_SPIEnable(GSPI_BASE);
MAP_SPICSEnable(GSPI_BASE);
MAP_SPIFIFOEnable(GSPI_BASE,SPI_RX_FIFO);
MAP_SPIFIFOEnable(GSPI_BASE,SPI_TX_FIFO);
SPIFIFOLevelSet(GSPI_BASE,1,1);
MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMARX);
//MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMATX);
//MAP_SPIIntRegister(GSPI_BASE,DMAIntHandler);
osi_InterruptRegister(INT_GSPI, DMAIntHandler, 32);
}
/*
* ======== SPICC3200DMA_transfer ========
* @pre Function assumes that handle and transaction is not NULL
*/
bool SPICC3200DMA_transfer(SPI_Handle handle, SPI_Transaction *transaction)
{
uintptr_t key;
SPICC3200DMA_Object *object = handle->object;
SPICC3200DMA_HWAttrs const *hwAttrs = handle->hwAttrs;
/* This is a limitation by the micro DMA controller */
if ((transaction->count == 0) || (transaction->count > 1024) ||
!(transaction->rxBuf || transaction->txBuf) ||
(!(transaction->rxBuf && transaction->txBuf) && !hwAttrs->scratchBufPtr)) {
return (false);
}
/* Check if a transfer is in progress */
key = HwiP_disable();
if (object->transaction) {
HwiP_restore(key);
DebugP_log1("SPI:(%p) ERROR! Transaction still in progress",
((SPICC3200DMA_HWAttrs const *)(handle->hwAttrs))->baseAddr);
return (false);
}
else {
object->transaction = transaction;
HwiP_restore(key);
}
/* Set constraints to guarantee transaction */
Power_setConstraint(PowerCC3200_DISALLOW_DEEPSLEEP);
SPICC3200DMA_configDMA(handle, transaction);
MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMARX | SPI_INT_DMATX | SPI_INT_EOW);
MAP_SPIIntEnable(hwAttrs->baseAddr, SPI_INT_DMARX | SPI_INT_DMATX | SPI_INT_EOW);
MAP_SPIEnable(hwAttrs->baseAddr);
MAP_SPICSEnable(hwAttrs->baseAddr);
if (object->transferMode == SPI_MODE_BLOCKING) {
DebugP_log1("SPI:(%p) transfer pending on transferComplete semaphore",
((SPICC3200DMA_HWAttrs const *)(handle->hwAttrs))->baseAddr);
SemaphoreP_pend(object->transferComplete, SemaphoreP_WAIT_FOREVER);
}
return (true);
}
Fd_t spi_Open(char *ifName, unsigned long flags)
{
unsigned long ulBase;
unsigned long ulSpiBitRate;
tROMVersion* pRomVersion = (tROMVersion *)(ROM_VERSION_ADDR);
//NWP master interface
ulBase = LSPI_BASE;
//Enable MCSPIA2
MAP_PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK);
//Disable Chip Select
MAP_SPICSDisable(ulBase);
//Disable SPI Channel
MAP_SPIDisable(ulBase);
// Reset SPI
MAP_SPIReset(ulBase);
//
// Configure SPI interface
//
if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_21 )
{
ulSpiBitRate = SPI_RATE_13M;
}
else if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_32)
{
ulSpiBitRate = SPI_RATE_13M;
}
else if(pRomVersion->ucMinorVerNum >= ROM_VER_PG1_33)
{
ulSpiBitRate = SPI_RATE_20M;
}
MAP_SPIConfigSetExpClk(ulBase,MAP_PRCMPeripheralClockGet(PRCM_LSPI),
ulSpiBitRate,SPI_MODE_MASTER,SPI_SUB_MODE_0,
(SPI_SW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_OFF |
SPI_CS_ACTIVEHIGH |
SPI_WL_32));
if(MAP_PRCMPeripheralStatusGet(PRCM_UDMA))
{
g_ucDMAEnabled = (HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0x0) ? 1 : 0;
}
else
{
g_ucDMAEnabled = 0;
}
#ifdef SL_CPU_MODE
g_ucDMAEnabled = 0;
#endif
if(g_ucDMAEnabled)
{
memset(g_ucDinDout,0xFF,sizeof(g_ucDinDout));
// Set DMA channel
cc_UDMAChannelSelect(UDMA_CH12_LSPI_RX);
cc_UDMAChannelSelect(UDMA_CH13_LSPI_TX);
MAP_SPIFIFOEnable(ulBase,SPI_RX_FIFO);
MAP_SPIFIFOEnable(ulBase,SPI_TX_FIFO);
MAP_SPIDmaEnable(ulBase,SPI_RX_DMA);
MAP_SPIDmaEnable(ulBase,SPI_TX_DMA);
MAP_SPIFIFOLevelSet(ulBase,1,1);
#if defined(SL_PLATFORM_MULTI_THREADED)
osi_InterruptRegister(INT_LSPI, (P_OSI_INTR_ENTRY)DmaSpiSwIntHandler,INT_PRIORITY_LVL_1);
MAP_SPIIntEnable(ulBase,SPI_INT_EOW);
osi_MsgQCreate(&DMAMsgQ,"DMAQueue",sizeof(int),1);
#else
MAP_IntRegister(INT_LSPI,(void(*)(void))DmaSpiSwIntHandler);
MAP_IntPrioritySet(INT_LSPI, INT_PRIORITY_LVL_1);
MAP_IntEnable(INT_LSPI);
MAP_SPIIntEnable(ulBase,SPI_INT_EOW);
g_cDummy = 0x0;
#endif
}
MAP_SPIEnable(ulBase);
g_SpiFd = 1;
return g_SpiFd;
}