//--------------------------------
void ssi_peripheral::Initialize() {
MAP_SysCtlPeripheralEnable(m_rSpecification.m_nSSIPeripheral);
MAP_SysCtlPeripheralEnable(m_rSpecification.m_nGPIOPeripheral);
// Assign the SSI signals to the appropriate pins
MAP_GPIOPinConfigure(m_rSpecification.m_nSSIPinRx);
MAP_GPIOPinConfigure(m_rSpecification.m_nSSIPinClk);
MAP_GPIOPinConfigure(m_rSpecification.m_nSSIPinTx);
if (m_rSpecification.m_nSSIPinFss) {
MAP_GPIOPinConfigure(m_rSpecification.m_nSSIPinFss);
}
// Set the GPIO AFSEL bits for the appropriate pins
MAP_GPIOPinTypeSSI(m_rSpecification.m_nGPIOBase,
m_rSpecification.m_nGPIOPins);
// Set pull-up on the SSI Rx pin
GPIOPadConfigSet(m_rSpecification.m_nGPIOBase,
m_rSpecification.m_nGPIOInputPin, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPU);
// Set standard on the SSI output pins
GPIOPadConfigSet(m_rSpecification.m_nGPIOBase,
m_rSpecification.m_nGPIOOutputPins, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD);
// Configure the SSI peripheral
SSIConfigSetExpClk(m_rSpecification.m_nSSIBase, SysCtlClockGet(),
m_nProtocol, SSI_MODE_MASTER, m_nBitRate, 16);
// Enable the SSI module.
MAP_SSIEnable(m_rSpecification.m_nSSIBase);
// Read any residual data from the SSI port.
while (MAP_SSIDataGetNonBlocking(m_rSpecification.m_nSSIBase, &m_nDataRx[0])) {
}
m_bEmpty = true;
// Enable the SSI interrupt
switch (m_nDevice) {
case ssi_peripheral::SSI0:
g_pTheSSI0 = this;
break;
case ssi_peripheral::SSI1:
g_pTheSSI1 = this;
break;
case ssi_peripheral::SSI2:
g_pTheSSI2 = this;
break;
case ssi_peripheral::SSI3:
g_pTheSSI3 = this;
break;
default:
break;
}
SSIIntDisable(m_rSpecification.m_nSSIBase,
SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR);
SSIIntClear(m_rSpecification.m_nSSIBase,
SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR);
(*((volatile uint32_t *) m_rSpecification.m_nSSI_CR1_R)) |= SSI_CR1_EOT; /* switch tx interrupt to eot int */
if (m_bNonBlocking) {
SSIIntEnable(m_rSpecification.m_nSSIBase, SSI_TXFF); /* SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR */
MAP_IntEnable(m_rSpecification.m_nInterrupt);
}
}
static void spi_init(void) {
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
// Configure SSI1 for SPI RAM usage
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);
MAP_GPIOPinConfigure(GPIO_PB4_SSI2CLK);
MAP_GPIOPinConfigure(GPIO_PB6_SSI2RX);
MAP_GPIOPinConfigure(GPIO_PB7_SSI2TX);
MAP_GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_6 | GPIO_PIN_7);
MAP_SSIConfigSetExpClk(SSI2_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 1000000, 8);
MAP_SSIEnable(SSI2_BASE);
unsigned long b;
while(MAP_SSIDataGetNonBlocking(SSI2_BASE, &b)) {}
}
/*
* @brief Selects a SPI device and enable high A,B,C
* @param device to be selected
* @returns void
*/
void SPISelectDeviceISR(uint8 device) {
unsigned long junk;
volatile uint8 q;
// deassert the previous device
SPIDeselectISR();
// clear the receive FIFO
while (MAP_SSIDataGetNonBlocking(SSI0_BASE, &junk)) {
q++;
}
// Configure the device to have the right settings
SPIConfigureDevice(device);
// Actually Select the Device
#if (defined(RONE_V9) || defined(RONE_V12))
switch (device) {
case SPI_RADIO: {
MAP_GPIOPinWrite(SPI_SELECT_PORT, SPI_SELECT_PINS, RADIO_SELECT_PINS);
break;
}
case SPI_MSP430: {
MAP_GPIOPinWrite(SPI_SELECT_PORT, SPI_SELECT_PINS, MSP430_SELECT_PINS);
break;
}
default: {
MAP_GPIOPinWrite(SPI_SELECT_PORT, SPI_SELECT_PINS, NULL_SELECT_PINS);
break;
}
}
//set output enable high since A,B,C spi pins are set
MAP_GPIOPinWrite(SPI_ENABLE_PORT, SPI_ENABLE_PIN, SPI_ENABLE_PIN);
#endif
}
void enc28_InitSPI(uint32_t ui32_bitrate, uint32_t ui32_SSI_Base)
{
uint32_t ui32_RxData;
uint32_t ui32_SysCtl_Periph_SSI;
uint32_t ui32_SysCtl_Periph_GPIO;
ui32_SSIx = ui32_SSI_Base;
switch(ui32_SSIx) {
case SSI1_BASE:
ui32_SysCtl_Periph_SSI = SYSCTL_PERIPH_SSI1;
ui32_SysCtl_Periph_GPIO = SYSCTL_PERIPH_GPIOF;
break;
case SSI2_BASE:
ui32_SysCtl_Periph_SSI = SYSCTL_PERIPH_SSI2;
ui32_SysCtl_Periph_GPIO = SYSCTL_PERIPH_GPIOB;
break;
case SSI3_BASE:
ui32_SysCtl_Periph_SSI = SYSCTL_PERIPH_SSI3;
ui32_SysCtl_Periph_GPIO = SYSCTL_PERIPH_GPIOD;
break;
case SSI0_BASE:
default:
ui32_SysCtl_Periph_SSI = SYSCTL_PERIPH_SSI0;
ui32_SysCtl_Periph_GPIO = SYSCTL_PERIPH_GPIOA;
break;
};
#ifdef UART_STDIO
UARTprintf("Configuring MASTER SSI%d, data 16-bit, (0,0) mode, %d bit rate.\n", 0, ui32_bitrate);
#endif // UART_STDIO
// Enable Periphericals in SysCtl
MAP_SysCtlPeripheralEnable(ui32_SysCtl_Periph_SSI);
MAP_SysCtlPeripheralEnable(ui32_SysCtl_Periph_GPIO);
// Enable alternate GPIO functions
// Configures pin(s) for use by the SSI peripheral
switch(ui32_SSIx) {
case SSI1_BASE:
MAP_GPIOPinConfigure(GPIO_PF2_SSI1CLK);
MAP_GPIOPinConfigure(GPIO_PF3_SSI1FSS);
MAP_GPIOPinConfigure(GPIO_PF0_SSI1RX);
MAP_GPIOPinConfigure(GPIO_PF1_SSI1TX);
MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_3 | GPIO_PIN_2 | GPIO_PIN_1 |
GPIO_PIN_0);
break;
case SSI2_BASE:
MAP_GPIOPinConfigure(GPIO_PB4_SSI2CLK);
MAP_GPIOPinConfigure(GPIO_PB5_SSI2FSS);
MAP_GPIOPinConfigure(GPIO_PB6_SSI2RX);
MAP_GPIOPinConfigure(GPIO_PB7_SSI2TX);
MAP_GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 |
GPIO_PIN_7);
break;
case SSI3_BASE:
MAP_GPIOPinConfigure(GPIO_PD0_SSI3CLK);
MAP_GPIOPinConfigure(GPIO_PD1_SSI3FSS);
MAP_GPIOPinConfigure(GPIO_PD2_SSI3RX);
MAP_GPIOPinConfigure(GPIO_PD3_SSI3TX);
MAP_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |
GPIO_PIN_3);
break;
case SSI0_BASE:
default:
MAP_GPIOPinConfigure(GPIO_PA2_SSI0CLK);
MAP_GPIOPinConfigure(GPIO_PA3_SSI0FSS);
MAP_GPIOPinConfigure(GPIO_PA4_SSI0RX);
MAP_GPIOPinConfigure(GPIO_PA5_SSI0TX);
MAP_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 |
GPIO_PIN_2);
break;
};
// Configures the SSI operation mode
MAP_SSIConfigSetExpClk(ui32_SSIx, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, ui32_bitrate, 16);
// Enables SSI
MAP_SSIEnable(ui32_SSIx);
while(MAP_SSIDataGetNonBlocking(ui32_SSIx, &ui32_RxData));
}
