/**
* Initializes the QSSI_COMM port to transmit or receive a data transmission
*
* \param RXmode - true - initialize QSSI_COMM to read as a slave
* false - initialize QSSI_COMM to write as a master
**/
void twe_initQSSI(uint32_t SysClkFreq, bool RXmode) {
// Enable Peripherals
MAP_SysCtlPeripheralEnable(twe_QSSI_COMM_PERIPH);
MAP_SysCtlPeripheralEnable(twe_QSSI_COMM_CLK_FSS_GPIO_PERIPH);
MAP_SysCtlPeripheralEnable(twe_QSSI_COMM_XDAT01_GPIO_PERIPH);
MAP_SysCtlPeripheralEnable(twe_QSSI_COMM_XDAT23_GPIO_PERIPH);
// Set the pin muxing
MAP_GPIOPinConfigure(twe_QSSI_COMM_CLK_PIN_CONFIG);
MAP_GPIOPinConfigure(twe_QSSI_COMM_FSS_PIN_CONFIG);
MAP_GPIOPinConfigure(twe_QSSI_COMM_DAT0_PIN_CONFIG);
MAP_GPIOPinConfigure(twe_QSSI_COMM_DAT1_PIN_CONFIG);
MAP_GPIOPinConfigure(twe_QSSI_COMM_DAT2_PIN_CONFIG);
MAP_GPIOPinConfigure(twe_QSSI_COMM_DAT3_PIN_CONFIG);
MAP_GPIOPinTypeSSI(twe_QSSI_COMM_CLK_FSS_GPIO_BASE, twe_QSSI_COMM_CLK_PIN | twe_QSSI_COMM_FSS_PIN);
MAP_GPIOPinTypeSSI(twe_QSSI_COMM_XDAT01_GPIO_BASE, twe_QSSI_COMM_DAT0_PIN | twe_QSSI_COMM_DAT1_PIN);
MAP_GPIOPinTypeSSI(twe_QSSI_COMM_XDAT23_GPIO_BASE, twe_QSSI_COMM_DAT2_PIN | twe_QSSI_COMM_DAT3_PIN);
// Must be in SPI Mode0 for QSSI (Advanced) mode
if(RXmode) {
MAP_SSIConfigSetExpClk(twe_QSSI_COMM_BASE, SysClkFreq, SSI_FRF_MOTO_MODE_0,
SSI_MODE_SLAVE, twe_QSSI_COMM_BAUD, 8);
SSIAdvModeSet(twe_QSSI_COMM_BASE, SSI_ADV_MODE_QUAD_READ);
SSIDataPut(twe_QSSI_COMM_BASE,0x00);
}
else {
SSIConfigSetExpClk(twe_QSSI_COMM_BASE, SysClkFreq, SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, twe_QSSI_COMM_BAUD, 8);
SSIAdvModeSet(twe_QSSI_COMM_BASE, SSI_ADV_MODE_QUAD_WRITE);
}
// Enable SSI
MAP_SSIEnable(twe_QSSI_COMM_BASE);
//SSIDMAEnable(ADC_SSI_BASE, SSI_DMA_RX); // Enable SSI uDMA
}
//*****************************************************************************
//
// Initializes the SSI port and determines if the TRF79x0 is available.
//
// This function must be called prior to any other function offered by the
// TRF79x0. It configures the SSI port to run in Motorola/Freescale
// mode.
//
// \return None.
//
//*****************************************************************************
void
SSITRF79x0Init(void)
{
//
// Enable the peripherals used to drive the TRF79x0 on SSI.
//
MAP_SysCtlPeripheralEnable(TRF79X0_SSI_PERIPH);
//
// Enable the GPIO peripherals associated with the SSI.
//
MAP_SysCtlPeripheralEnable(TRF79X0_CLK_PERIPH);
MAP_SysCtlPeripheralEnable(TRF79X0_RX_PERIPH);
MAP_SysCtlPeripheralEnable(TRF79X0_TX_PERIPH);
MAP_SysCtlPeripheralEnable(TRF79X0_CS_PERIPH);
//
// Configure the appropriate pins to be SSI instead of GPIO. The CS
// is configured as GPIO to support TRF79x0 SPI requirements for R/W
// access.
//
MAP_GPIOPinConfigure(TRF79X0_CLK_CONFIG);
MAP_GPIOPinConfigure(TRF79X0_RX_CONFIG);
MAP_GPIOPinConfigure(TRF79X0_TX_CONFIG);
MAP_GPIOPinTypeSSI(TRF79X0_CLK_BASE, TRF79X0_CLK_PIN);
MAP_GPIOPinTypeSSI(TRF79X0_RX_BASE, TRF79X0_RX_PIN);
MAP_GPIOPinTypeSSI(TRF79X0_TX_BASE, TRF79X0_TX_PIN);
MAP_GPIOPinTypeGPIOOutput(TRF79X0_CS_BASE, TRF79X0_CS_PIN);
MAP_GPIOPadConfigSet(TRF79X0_CLK_BASE, TRF79X0_CLK_PIN,
GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);
MAP_GPIOPadConfigSet(TRF79X0_RX_BASE, TRF79X0_RX_PIN,
GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);
MAP_GPIOPadConfigSet(TRF79X0_TX_BASE, TRF79X0_TX_PIN,
GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);
//
// Deassert the SSI chip selects TRF79x0.
//
MAP_GPIOPinWrite(TRF79X0_CS_BASE, TRF79X0_CS_PIN, TRF79X0_CS_PIN);
//
// Configure the SSI port for 2MHz operation.
//
MAP_SSIConfigSetExpClk(TRF79X0_SSI_BASE, g_ui32SysClk,
SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SSI_CLK_RATE,
8);
if(RF_DAUGHTER_TRF7970) {
//
// Switch from SPH=0 to SPH=1. Required for TRF7970.
//
HWREG(TRF79X0_SSI_BASE + SSI_O_CR0) |= SSI_CR0_SPH;
}
//
// Enable the SSI controller.
//
MAP_SSIEnable(TRF79X0_SSI_BASE);
}
static void prvSetupSPI(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);
// set the SSI clock to the PIOSC clock
SSIClockSourceSet(SSI2_BASE, SSI_CLOCK_SYSTEM);
SSIConfigSetExpClk(SSI2_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
MAP_SSIEnable(SSI2_BASE);
}
//--------------------------------
void ssi_peripheral::Initialize() {
MAP_SysCtlPeripheralEnable(m_rSpecification.m_nSSIPeripheral);
MAP_SysCtlPeripheralEnable(m_rSpecification.m_nGPIOPeripheral);
// Assign the SSI signals to the appropriate pins
MAP_GPIOPinConfigure(m_rSpecification.m_nSSIPinRx);
MAP_GPIOPinConfigure(m_rSpecification.m_nSSIPinClk);
MAP_GPIOPinConfigure(m_rSpecification.m_nSSIPinTx);
if (m_rSpecification.m_nSSIPinFss) {
MAP_GPIOPinConfigure(m_rSpecification.m_nSSIPinFss);
}
// Set the GPIO AFSEL bits for the appropriate pins
MAP_GPIOPinTypeSSI(m_rSpecification.m_nGPIOBase,
m_rSpecification.m_nGPIOPins);
// Set pull-up on the SSI Rx pin
GPIOPadConfigSet(m_rSpecification.m_nGPIOBase,
m_rSpecification.m_nGPIOInputPin, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPU);
// Set standard on the SSI output pins
GPIOPadConfigSet(m_rSpecification.m_nGPIOBase,
m_rSpecification.m_nGPIOOutputPins, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD);
// Configure the SSI peripheral
SSIConfigSetExpClk(m_rSpecification.m_nSSIBase, SysCtlClockGet(),
m_nProtocol, SSI_MODE_MASTER, m_nBitRate, 16);
// Enable the SSI module.
MAP_SSIEnable(m_rSpecification.m_nSSIBase);
// Read any residual data from the SSI port.
while (MAP_SSIDataGetNonBlocking(m_rSpecification.m_nSSIBase, &m_nDataRx[0])) {
}
m_bEmpty = true;
// Enable the SSI interrupt
switch (m_nDevice) {
case ssi_peripheral::SSI0:
g_pTheSSI0 = this;
break;
case ssi_peripheral::SSI1:
g_pTheSSI1 = this;
break;
case ssi_peripheral::SSI2:
g_pTheSSI2 = this;
break;
case ssi_peripheral::SSI3:
g_pTheSSI3 = this;
break;
default:
break;
}
SSIIntDisable(m_rSpecification.m_nSSIBase,
SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR);
SSIIntClear(m_rSpecification.m_nSSIBase,
SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR);
(*((volatile uint32_t *) m_rSpecification.m_nSSI_CR1_R)) |= SSI_CR1_EOT; /* switch tx interrupt to eot int */
if (m_bNonBlocking) {
SSIIntEnable(m_rSpecification.m_nSSIBase, SSI_TXFF); /* SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR */
MAP_IntEnable(m_rSpecification.m_nInterrupt);
}
}
// note must be called after you have the mutex - after
// radio max clock freq = 10mhz
// MSP430 max fre clkI cycles - we might be violating this
// SD card -fast frequency ~= 2 MHz
// sound chip - 2s to be 400kHz at first, then bump up speed
void SPIConfigure(uint32 ulBase, uint8 wordSize, uint8 mode, uint32 frequency) {
if ((wordSize != SPIWordSize) || (mode != SPIMode) || (frequency != SPIFrequency)) {
// cache word size value
SPIWordSize = wordSize;
SPIMode = mode;
SPIFrequency = frequency;
MAP_SSIDisable(ulBase);
// Configure the SSI0 port for master mode with all the configuration settings
MAP_SSIConfigSetExpClk(ulBase, SYSCTL_CLOCK_FREQ, SPIMode, SSI_MODE_MASTER, SPIFrequency, SPIWordSize);
// Enable the SSI port.
MAP_SSIEnable(ulBase);
}
}
static void spi_init(void) {
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
// Configure SSI1 for SPI RAM usage
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);
MAP_GPIOPinConfigure(GPIO_PB4_SSI2CLK);
MAP_GPIOPinConfigure(GPIO_PB6_SSI2RX);
MAP_GPIOPinConfigure(GPIO_PB7_SSI2TX);
MAP_GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_6 | GPIO_PIN_7);
MAP_SSIConfigSetExpClk(SSI2_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 1000000, 8);
MAP_SSIEnable(SSI2_BASE);
unsigned long b;
while(MAP_SSIDataGetNonBlocking(SSI2_BASE, &b)) {}
}
u32 platform_spi_setup( unsigned id, int mode, u32 clock, unsigned cpol, unsigned cpha, unsigned databits )
{
unsigned protocol;
if( cpol == 0 )
protocol = cpha ? SSI_FRF_MOTO_MODE_1 : SSI_FRF_MOTO_MODE_0;
else
protocol = cpha ? SSI_FRF_MOTO_MODE_3 : SSI_FRF_MOTO_MODE_2;
mode = mode == PLATFORM_SPI_MASTER ? SSI_MODE_MASTER : SSI_MODE_SLAVE;
MAP_SSIDisable( spi_base[ id ] );
MAP_GPIOPinTypeSSI( spi_gpio_base[ id ], spi_gpio_pins[ id ] );
// FIXME: not sure this is always "right"
// MAP_GPIOPadConfigSet(spi_gpio_base[ id ], spi_gpio_clk_pin[ id ], GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
MAP_SSIConfigSetExpClk( spi_base[ id ], MAP_SysCtlClockGet(), protocol, mode, clock, databits );
MAP_SSIEnable( spi_base[ id ] );
return clock;
}
void spi_init(unsigned long bitrate,unsigned long datawidth){
//SSI
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
MAP_SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOA);
MAP_SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOC);
//CS Pin
MAP_GPIOPinTypeGPIOOutput(CS_PIN_BASE,CS_PIN);
//CE Pin
MAP_GPIOPinTypeGPIOOutput(CE_PIN_BASE,CE_PIN);
/* Configure the SSI0 port */
MAP_SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,SSI_MODE_MASTER, bitrate, datawidth);
/* Configure the appropriate pins to be SSI instead of GPIO */
MAP_GPIOPinTypeSSI(GPIO_PORTA_AHB_BASE, GPIO_PIN_2 |GPIO_PIN_4 | GPIO_PIN_5);
MAP_SSIEnable(SSI0_BASE);
ulClockMS = MAP_SysCtlClockGet() / (3 * 1000);
}
void spi_init(void) {
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
MAP_GPIOPinConfigure(GPIO_PA2_SSI0CLK);
MAP_GPIOPinConfigure(GPIO_PA5_SSI0TX);
MAP_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_5);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
MAP_GPIOPinConfigure(GPIO_PF2_SSI1CLK);
MAP_GPIOPinConfigure(GPIO_PF1_SSI1TX);
MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_1);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
MAP_GPIOPinConfigure(GPIO_PB4_SSI2CLK);
MAP_GPIOPinConfigure(GPIO_PB7_SSI2TX);
MAP_GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_7);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
MAP_GPIOPinConfigure(GPIO_PD0_SSI3CLK);
MAP_GPIOPinConfigure(GPIO_PD3_SSI3TX);
MAP_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_3);
/* Configure SSI0..3 for the ws2801's SPI-like protocol */
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
MAP_SSIConfigSetExpClk(SSI0_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SPI_SPEED, 16);
MAP_SSIConfigSetExpClk(SSI1_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SPI_SPEED, 16);
MAP_SSIConfigSetExpClk(SSI2_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SPI_SPEED, 16);
MAP_SSIConfigSetExpClk(SSI3_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SPI_SPEED, 16);
/* Configure the µDMA controller for use by the SPI interface */
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
MAP_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UDMA);
// FIXME what do we need this for? IntEnable(INT_UDMAERR); // Enable µDMA error interrupt
MAP_uDMAEnable();
MAP_uDMAControlBaseSet(ucControlTable);
MAP_uDMAChannelAssign(UDMA_CH11_SSI0TX);
MAP_uDMAChannelAssign(UDMA_CH25_SSI1TX);
MAP_uDMAChannelAssign(UDMA_CH13_SSI2TX);
MAP_uDMAChannelAssign(UDMA_CH15_SSI3TX);
ssi_udma_channel_config(11);
ssi_udma_channel_config(25);
ssi_udma_channel_config(13);
ssi_udma_channel_config(15);
MAP_SSIDMAEnable(SSI0_BASE, SSI_DMA_TX);
MAP_SSIDMAEnable(SSI1_BASE, SSI_DMA_TX);
MAP_SSIDMAEnable(SSI2_BASE, SSI_DMA_TX);
MAP_SSIDMAEnable(SSI3_BASE, SSI_DMA_TX);
/* Enable the SSIs after configuring anything around them. */
MAP_SSIEnable(SSI0_BASE);
MAP_SSIEnable(SSI1_BASE);
MAP_SSIEnable(SSI2_BASE);
MAP_SSIEnable(SSI3_BASE);
}
void enc28_InitSPI(uint32_t ui32_bitrate, uint32_t ui32_SSI_Base)
{
uint32_t ui32_RxData;
uint32_t ui32_SysCtl_Periph_SSI;
uint32_t ui32_SysCtl_Periph_GPIO;
ui32_SSIx = ui32_SSI_Base;
switch(ui32_SSIx) {
case SSI1_BASE:
ui32_SysCtl_Periph_SSI = SYSCTL_PERIPH_SSI1;
ui32_SysCtl_Periph_GPIO = SYSCTL_PERIPH_GPIOF;
break;
case SSI2_BASE:
ui32_SysCtl_Periph_SSI = SYSCTL_PERIPH_SSI2;
ui32_SysCtl_Periph_GPIO = SYSCTL_PERIPH_GPIOB;
break;
case SSI3_BASE:
ui32_SysCtl_Periph_SSI = SYSCTL_PERIPH_SSI3;
ui32_SysCtl_Periph_GPIO = SYSCTL_PERIPH_GPIOD;
break;
case SSI0_BASE:
default:
ui32_SysCtl_Periph_SSI = SYSCTL_PERIPH_SSI0;
ui32_SysCtl_Periph_GPIO = SYSCTL_PERIPH_GPIOA;
break;
};
#ifdef UART_STDIO
UARTprintf("Configuring MASTER SSI%d, data 16-bit, (0,0) mode, %d bit rate.\n", 0, ui32_bitrate);
#endif // UART_STDIO
// Enable Periphericals in SysCtl
MAP_SysCtlPeripheralEnable(ui32_SysCtl_Periph_SSI);
MAP_SysCtlPeripheralEnable(ui32_SysCtl_Periph_GPIO);
// Enable alternate GPIO functions
// Configures pin(s) for use by the SSI peripheral
switch(ui32_SSIx) {
case SSI1_BASE:
MAP_GPIOPinConfigure(GPIO_PF2_SSI1CLK);
MAP_GPIOPinConfigure(GPIO_PF3_SSI1FSS);
MAP_GPIOPinConfigure(GPIO_PF0_SSI1RX);
MAP_GPIOPinConfigure(GPIO_PF1_SSI1TX);
MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_3 | GPIO_PIN_2 | GPIO_PIN_1 |
GPIO_PIN_0);
break;
case SSI2_BASE:
MAP_GPIOPinConfigure(GPIO_PB4_SSI2CLK);
MAP_GPIOPinConfigure(GPIO_PB5_SSI2FSS);
MAP_GPIOPinConfigure(GPIO_PB6_SSI2RX);
MAP_GPIOPinConfigure(GPIO_PB7_SSI2TX);
MAP_GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 |
GPIO_PIN_7);
break;
case SSI3_BASE:
MAP_GPIOPinConfigure(GPIO_PD0_SSI3CLK);
MAP_GPIOPinConfigure(GPIO_PD1_SSI3FSS);
MAP_GPIOPinConfigure(GPIO_PD2_SSI3RX);
MAP_GPIOPinConfigure(GPIO_PD3_SSI3TX);
MAP_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |
GPIO_PIN_3);
break;
case SSI0_BASE:
default:
MAP_GPIOPinConfigure(GPIO_PA2_SSI0CLK);
MAP_GPIOPinConfigure(GPIO_PA3_SSI0FSS);
MAP_GPIOPinConfigure(GPIO_PA4_SSI0RX);
MAP_GPIOPinConfigure(GPIO_PA5_SSI0TX);
MAP_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 |
GPIO_PIN_2);
break;
};
// Configures the SSI operation mode
MAP_SSIConfigSetExpClk(ui32_SSIx, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, ui32_bitrate, 16);
// Enables SSI
MAP_SSIEnable(ui32_SSIx);
while(MAP_SSIDataGetNonBlocking(ui32_SSIx, &ui32_RxData));
}
