/*
* ======== UARTMSP432_hwiIntFxn ========
* Hwi function that processes UART interrupts.
*
* @param(arg) The UART_Handle for this Hwi.
*/
void UARTMSP432_hwiIntFxn(uintptr_t arg)
{
bool readSuccess = true;
uint8_t status;
uintptr_t errorFlags;
UARTMSP432_Object *object = ((UART_Handle) arg)->object;
UARTMSP432_HWAttrs const *hwAttrs = ((UART_Handle) arg)->hwAttrs;
/* Clear interrupts */
status = MAP_UART_getEnabledInterruptStatus(hwAttrs->baseAddr);
MAP_UART_clearInterruptFlag(hwAttrs->baseAddr, status);
if (status & EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG) {
readSuccess = object->readFxns.readIsrFxn((UART_Handle)arg);
}
if (status & EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG) {
writeData((UART_Handle)arg);
}
if (status & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT |
EUSCI_A_UART_BREAKCHAR_INTERRUPT) || !readSuccess) {
errorFlags = MAP_UART_queryStatusFlags(hwAttrs->baseAddr,
EUSCI_A_UART_OVERRUN_ERROR | EUSCI_A_UART_BREAK_DETECT |
EUSCI_A_UART_PARITY_ERROR | EUSCI_A_UART_FRAMING_ERROR);
errorCallback((UART_Handle)arg, errorFlags);
}
}
void vUART_Handler( void )
{
uint8_t ucChar;
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
uint_fast8_t xInterruptStatus;
xInterruptStatus = MAP_UART_getEnabledInterruptStatus( EUSCI_A0_MODULE );
if( ( xInterruptStatus & EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG ) != 0x00 )
{
/* Obtain the character. */
ucChar = MAP_UART_receiveData( EUSCI_A0_MODULE );
/* Send the character to the queue. Note the comments at the top of this
file with regards to the inefficiency of this method for anything other than
very low bandwidth communications.
If writing to the queue unblocks a task, and the unblocked task has a
priority above the currently running task (the task that this interrupt
interrupted), then xHigherPriorityTaskWoken will be set to pdTRUE inside the
xQueueSendFromISR() function. xHigherPriorityTaskWoken is then passed to
portYIELD_FROM_ISR() at the end of this interrupt handler to request a
context switch so the interrupt returns directly to the (higher priority)
unblocked task. */
xQueueSendFromISR( xRxQueue, &ucChar, &xHigherPriorityTaskWoken );
}
if( ( xInterruptStatus & EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG ) != 0x00 )
{
/* Are there more characters to transmit? */
pcStringStart++;
if( ( uint32_t ) pcStringStart < ( uint32_t ) pcStringEnd )
{
/* This is probably quite a heavy wait function just for writing to
the Tx register. An optimised design would probably replace this
with a simple register write. */
pxUARTA0->rTXBUF.r = ( uint_fast8_t ) *pcStringStart;
}
else
{
/* No more characters to send. Disable the interrupt and notify the
task, if the task is waiting. */
MAP_UART_disableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
if( xTransmittingTask != NULL )
{
vTaskNotifyGiveFromISR( xTransmittingTask, &xHigherPriorityTaskWoken );
xTransmittingTask = NULL;
}
}
}
/* portYIELD_FROM_ISR() will request a context switch if executing this
interrupt handler caused a task to leave the blocked state, and the task
that left the blocked state has a higher priority than the currently running
task (the task this interrupt interrupted). See the comment above the calls
to xSemaphoreGiveFromISR() and xQueueSendFromISR() within this function. */
portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
}
/* EUSCI A0 UART ISR - Echoes data back to PC host */
void euscia0_isr(void)
{
uint32_t status = MAP_UART_getEnabledInterruptStatus(EUSCI_A0_MODULE);
MAP_UART_clearInterruptFlag(EUSCI_A0_MODULE, status);
if(status & EUSCI_A_UART_RECEIVE_INTERRUPT)
{
MAP_UART_transmitData(EUSCI_A0_MODULE, MAP_UART_receiveData(EUSCI_A0_MODULE));
}
}
/* EUSCI A0 UART ISR - Echos data back to PC host */
void euscia0_isr(void)
{
uint32_t status = MAP_UART_getEnabledInterruptStatus(EUSCI_A0_MODULE);
MAP_UART_clearInterruptFlag(EUSCI_A0_MODULE, status);
if(status & EUSCI_A_UART_RECEIVE_INTERRUPT)
{
RXData = MAP_UART_receiveData(EUSCI_A0_MODULE);
if(RXData != TXData) // Check value
{
MAP_GPIO_setOutputHighOnPin(GPIO_PORT_P1, GPIO_PIN0);
while(1); // Trap CPU
}
TXData++;
MAP_Interrupt_disableSleepOnIsrExit();
}
}
