// ------------------------------------------------- // // 采样的控制 // // ------------------------------------------------- static void DMAIntHandler(void) { MAP_SPIIntClear(GSPI_BASE,SPI_INT_DMATX|SPI_INT_DMARX); //MAP_SPIDmaDisable(GSPI_BASE, SPI_RX_DMA | SPI_TX_DMA); unsigned long ulMode; ulMode = MAP_uDMAChannelModeGet(UDMA_CH30_GSPI_RX | UDMA_PRI_SELECT); if(ulMode == UDMA_MODE_STOP) { //MAP_SPIDmaDisable(GSPI_BASE, SPI_RX_DMA ); if (!s_bRxDone) { s_bRxDone = true; // 发送同步脉冲 READ_FROM_SPI; WRITE_TO_SPI; READ_FROM_SPI; // 发送最后一根线 if (s_nSampleIndex >= 129) { ISR_LineSend(s_ucFrame,127,s_pucRxRcv,512); } } } ulMode = MAP_uDMAChannelModeGet(UDMA_CH31_GSPI_TX | UDMA_PRI_SELECT); if(ulMode == UDMA_MODE_STOP) { //MAP_SPIDmaDisable(GSPI_BASE, SPI_TX_DMA ); } }
//***************************************************************************** // //! Start a DMA transfer and wait for it to finish. //! //! This function will perform the steps necessary to initiate a DMA transfer //! It waits until the transfer is complete before returning to the caller. //! //! \param ulChannel DMA Channel //! //! \return Zero if there is no error // //***************************************************************************** unsigned long StartAndCompleteSWTransfer(unsigned long ulChannel) { unsigned long ulIdx; // // Clear interrupt status // MAP_uDMAIntClear(0xffffffff); MAP_uDMAChannelRequest(ulChannel); // // Wait for the mode to change to stopped // ulIdx = 0; while(MAP_uDMAChannelModeGet(ulChannel) != UDMA_MODE_STOP) { ulIdx++; if(ulIdx > 200000) { break; } } if(MAP_uDMAChannelIsEnabled(ulChannel)) { UART_PRINT("Error, channel was enabled at end of transfer\n"); return 1; } UART_PRINT("Transfer complete \n\r"); return(0); }
//***************************************************************************** // // USBLibDMAIntStatus() for USB controllers that use uDMA. // //***************************************************************************** static uint32_t uDMAUSBIntStatus(tUSBDMAInstance *psUSBDMAInst) { uint32_t ui32Status, ui32Pending; int32_t i32Channel; // // Initialize the current status to no events. // ui32Status = 0; // // No pending interrupts by default. // ui32Status = 0; // // Save the pending channels. // ui32Pending = psUSBDMAInst->ui32Pending; // // Loop through channels to find out if any pending DMA transfers have // completed. // for(i32Channel = 0; i32Channel < USB_MAX_DMA_CHANNELS; i32Channel++) { // // If pending and stopped then the DMA completed. // if((ui32Pending & 1) && (MAP_uDMAChannelModeGet(i32Channel) == UDMA_MODE_STOP)) { ui32Status |= (1 << i32Channel); } ui32Pending >>= 1; // // Done if this is zero. // if(ui32Pending == 0) { break; } } return(ui32Status); }
//***************************************************************************** //! //! The interrupt handler for UART0. This interrupt will occur when a DMA //! transfer is complete using the UART0 uDMA channel.This interrupt handler will //! switch between receive ping-pong buffers A and B. It will also restart a TX //! uDMA transfer if the prior transfer is complete. This will keep the UART //! running continuously (looping TX data back to RX). //! //! \param None //! //! \return None //***************************************************************************** void UART0IntHandler(void) { unsigned long ulStatus; unsigned long ulMode; // // Read the interrupt status of the UART. // ulStatus = MAP_UARTIntStatus(UARTA0_BASE, 1); // // Clear any pending status, even though there should be none since no UART // interrupts were enabled. // MAP_UARTIntClear(UARTA0_BASE, ulStatus); if(uiCount<6) { // // Check the DMA control table to see if the ping-pong "A" transfer is // complete. The "A" transfer uses receive buffer "A", and the primary // control structure. // ulMode = MAP_uDMAChannelModeGet(UDMA_CH8_UARTA0_RX | UDMA_PRI_SELECT); // // If the primary control structure indicates stop, that means the "A" // receive buffer is done. The uDMA controller should still be receiving // data into the "B" buffer. // if(ulMode == UDMA_MODE_STOP) { // // Increment a counter to indicate data was received into buffer A. // g_ulRxBufACount++; // // Set up the next transfer for the "A" buffer, using the primary // control structure. When the ongoing receive into the "B" buffer is // done, the uDMA controller will switch back to this one. // UDMASetupTransfer(UDMA_CH8_UARTA0_RX | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, sizeof(g_ucRxBufA),UDMA_SIZE_8, UDMA_ARB_4, (void *)(UARTA0_BASE + UART_O_DR), UDMA_SRC_INC_NONE, g_ucRxBufA, UDMA_DST_INC_8); } // // Check the DMA control table to see if the ping-pong "B" transfer is // complete. The "B" transfer uses receive buffer "B", and the alternate // control structure. // ulMode = MAP_uDMAChannelModeGet(UDMA_CH8_UARTA0_RX | UDMA_ALT_SELECT); // // If the alternate control structure indicates stop, that means the "B" // receive buffer is done. The uDMA controller should still be receiving // data into the "A" buffer. // if(ulMode == UDMA_MODE_STOP) { // // Increment a counter to indicate data was received into buffer A. // g_ulRxBufBCount++; // // Set up the next transfer for the "B" buffer, using the alternate // control structure. When the ongoing receive into the "A" buffer is // done, the uDMA controller will switch back to this one. // UDMASetupTransfer(UDMA_CH8_UARTA0_RX | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, sizeof(g_ucRxBufB),UDMA_SIZE_8, UDMA_ARB_4,(void *)(UARTA0_BASE + UART_O_DR), UDMA_SRC_INC_NONE, g_ucRxBufB, UDMA_DST_INC_8); } // // If the UART0 DMA TX channel is disabled, that means the TX DMA transfer // is done. // if(!MAP_uDMAChannelIsEnabled(UDMA_CH9_UARTA0_TX)) { g_ulTxCount++; // // Start another DMA transfer to UART0 TX. // UDMASetupTransfer(UDMA_CH9_UARTA0_TX| UDMA_PRI_SELECT, UDMA_MODE_BASIC, sizeof(g_ucTxBuf),UDMA_SIZE_8, UDMA_ARB_4,g_ucTxBuf, UDMA_SRC_INC_8, (void *)(UARTA0_BASE + UART_O_DR), UDMA_DST_INC_NONE); // // The uDMA TX channel must be re-enabled. // MAP_uDMAChannelEnable(UDMA_CH9_UARTA0_TX); } } else { UARTDone=1; MAP_UARTIntUnregister(UARTA0_BASE); } }