//***************************************************************************** // //! Initialize the DMA controller //! //! \param None //! //! This function initializes //! 1. Initializes the McASP module //! //! \return None. // //***************************************************************************** void UDMAInit() { unsigned int uiLoopCnt; // // Enable McASP at the PRCM module // MAP_PRCMPeripheralClkEnable(PRCM_UDMA,PRCM_RUN_MODE_CLK); MAP_PRCMPeripheralReset(PRCM_UDMA); // // Register interrupt handlers // MAP_uDMAIntRegister(UDMA_INT_SW, DmaSwIntHandler); MAP_uDMAIntRegister(UDMA_INT_ERR, DmaErrorIntHandler); // // Enable uDMA using master enable // MAP_uDMAEnable(); // // Set Control Table // memset(gpCtlTbl,0,sizeof(tDMAControlTable)*CTL_TBL_SIZE); MAP_uDMAControlBaseSet(gpCtlTbl); // // Reset App Callbacks // for(uiLoopCnt = 0; uiLoopCnt < MAX_NUM_CH; uiLoopCnt++) { gfpAppCallbackHndl[uiLoopCnt] = NULL; } }
//**************************************************************************** // //! \brief This function restore the backed up data (after S3) //! //! \param none //! //! \return none // //**************************************************************************** void lp3p0_restore_soc_data(void) { /* Invoking the default CC3xxx service impl. */ cc_restore_soc_data(); // // Configure the pinmux settings for the peripherals exercised // PinMuxConfig(); cc_gpio_restore_context(); #ifdef DEBUG_GPIO cc_gpio_write(tGPIODbgHndl, GPIO_09, 1); #endif /* Initialize timer services */ MAP_PRCMPeripheralClkEnable(PRCM_TIMERA0, PRCM_RUN_MODE_CLK| PRCM_SLP_MODE_CLK); /* ungates the clk for the shared SPI*/ MAP_PRCMPeripheralClkEnable(PRCM_SSPI, PRCM_RUN_MODE_CLK| PRCM_SLP_MODE_CLK); /* Initialize the DMA module */ MAP_PRCMPeripheralClkEnable(PRCM_UDMA, PRCM_RUN_MODE_CLK| PRCM_SLP_MODE_CLK); MAP_uDMAControlBaseSet(dma_ctrl_table); MAP_uDMAEnable(); MAP_PRCMIntEnable(PRCM_INT_SLOW_CLK_CTR); }
/* * ======== SPICC3200DMA_postNotify ======== * This functions is called to notify the SPI driver of an ongoing transition * out of LPDS mode. * clientArg should be pointing to a hardware module which has already * been opened. */ static int SPICC3200DMA_postNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg) { /* Reconfigure the hardware when returning from LPDS */ MAP_uDMAEnable(); MAP_uDMAControlBaseSet(uDMAControlBase); SPICC3200DMA_initHw((SPI_Handle)clientArg); return (Power_NOTIFYDONE); }
//***************************************************************************** // //! Initialize the DMA controller //! //! \param None //! //! This function initializes //! 1. Initializes the McASP module //! //! \return None. // //***************************************************************************** void UDMAInit() { unsigned int uiLoopCnt; // // Enable McASP at the PRCM module // MAP_PRCMPeripheralClkEnable(PRCM_UDMA,PRCM_RUN_MODE_CLK); MAP_PRCMPeripheralReset(PRCM_UDMA); // // Register interrupt handlers // #if defined(USE_TIRTOS) || defined(USE_FREERTOS) || defined(SL_PLATFORM_MULTI_THREADED) // USE_TIRTOS: if app uses TI-RTOS (either networking/non-networking) // USE_FREERTOS: if app uses Free-RTOS (either networking/non-networking) // SL_PLATFORM_MULTI_THREADED: if app uses any OS + networking(simplelink) osi_InterruptRegister(INT_UDMA, DmaSwIntHandler, INT_PRIORITY_LVL_1); osi_InterruptRegister(INT_UDMAERR, DmaErrorIntHandler, INT_PRIORITY_LVL_1); #else MAP_IntPrioritySet(INT_UDMA, INT_PRIORITY_LVL_1); MAP_uDMAIntRegister(UDMA_INT_SW, DmaSwIntHandler); MAP_IntPrioritySet(INT_UDMAERR, INT_PRIORITY_LVL_1); MAP_uDMAIntRegister(UDMA_INT_ERR, DmaErrorIntHandler); #endif // // Enable uDMA using master enable // MAP_uDMAEnable(); // // Set Control Table // memset(gpCtlTbl,0,sizeof(tDMAControlTable)*CTL_TBL_SIZE); MAP_uDMAControlBaseSet(gpCtlTbl); // // Reset App Callbacks // for(uiLoopCnt = 0; uiLoopCnt < MAX_NUM_CH; uiLoopCnt++) { gfpAppCallbackHndl[uiLoopCnt] = NULL; } }
//***************************************************************************** // // Initializes the USB stack for mass storage. // //***************************************************************************** void USBStickInit(void) { // // Enable the uDMA controller and set up the control table base. // The uDMA controller is used by the USB library. // MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA); MAP_uDMAEnable(); MAP_uDMAControlBaseSet(g_psDMAControlTable); // // Initially wait for device connection. // g_iState = eSTATE_NO_DEVICE; // // Register the host class drivers. // USBHCDRegisterDrivers(0, g_ppHostClassDrivers, g_ui32NumHostClassDrivers); // // Open an instance of the mass storage class driver. // g_psMSCInstance = USBHMSCDriveOpen(0, MSCCallback); // // Initialize the power configuration. This sets the power enable signal // to be active high and does not enable the power fault. // USBHCDPowerConfigInit(0, USBHCD_VBUS_AUTO_HIGH | USBHCD_VBUS_FILTER); // // Run initial pass through USB host stack. // USBHCDMain(); // // Initialize the file system. // FileInit(); }
/* * ======== Board_initDMA ======== */ void Board_initDMA(void) { Error_Block eb; Hwi_Params hwiParams; if (!dmaInitialized) { Error_init(&eb); Hwi_Params_init(&hwiParams); Hwi_construct(&(hwiStruct), INT_UDMAERR, Board_errorDMAHwi, &hwiParams, &eb); if (Error_check(&eb)) { System_abort("Couldn't create DMA error hwi"); } MAP_PRCMPeripheralClkEnable(PRCM_UDMA, PRCM_RUN_MODE_CLK); MAP_PRCMPeripheralReset(PRCM_UDMA); MAP_uDMAEnable(); MAP_uDMAControlBaseSet(dmaControlTable); dmaInitialized = true; } }
void spi_init(void) { MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); MAP_GPIOPinConfigure(GPIO_PA2_SSI0CLK); MAP_GPIOPinConfigure(GPIO_PA5_SSI0TX); MAP_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_5); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); MAP_GPIOPinConfigure(GPIO_PF2_SSI1CLK); MAP_GPIOPinConfigure(GPIO_PF1_SSI1TX); MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_1); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); MAP_GPIOPinConfigure(GPIO_PB4_SSI2CLK); MAP_GPIOPinConfigure(GPIO_PB7_SSI2TX); MAP_GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_7); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); MAP_GPIOPinConfigure(GPIO_PD0_SSI3CLK); MAP_GPIOPinConfigure(GPIO_PD3_SSI3TX); MAP_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_3); /* Configure SSI0..3 for the ws2801's SPI-like protocol */ MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3); MAP_SSIConfigSetExpClk(SSI0_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SPI_SPEED, 16); MAP_SSIConfigSetExpClk(SSI1_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SPI_SPEED, 16); MAP_SSIConfigSetExpClk(SSI2_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SPI_SPEED, 16); MAP_SSIConfigSetExpClk(SSI3_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SPI_SPEED, 16); /* Configure the µDMA controller for use by the SPI interface */ MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA); MAP_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UDMA); // FIXME what do we need this for? IntEnable(INT_UDMAERR); // Enable µDMA error interrupt MAP_uDMAEnable(); MAP_uDMAControlBaseSet(ucControlTable); MAP_uDMAChannelAssign(UDMA_CH11_SSI0TX); MAP_uDMAChannelAssign(UDMA_CH25_SSI1TX); MAP_uDMAChannelAssign(UDMA_CH13_SSI2TX); MAP_uDMAChannelAssign(UDMA_CH15_SSI3TX); ssi_udma_channel_config(11); ssi_udma_channel_config(25); ssi_udma_channel_config(13); ssi_udma_channel_config(15); MAP_SSIDMAEnable(SSI0_BASE, SSI_DMA_TX); MAP_SSIDMAEnable(SSI1_BASE, SSI_DMA_TX); MAP_SSIDMAEnable(SSI2_BASE, SSI_DMA_TX); MAP_SSIDMAEnable(SSI3_BASE, SSI_DMA_TX); /* Enable the SSIs after configuring anything around them. */ MAP_SSIEnable(SSI0_BASE); MAP_SSIEnable(SSI1_BASE); MAP_SSIEnable(SSI2_BASE); MAP_SSIEnable(SSI3_BASE); }
//***************************************************************************** // // The main function sets up the peripherals for the example, then enters // a wait loop until the DMA transfers are complete. At the end some // information is printed for the user. // //***************************************************************************** int main(void) { unsigned long ulIdx; // // Set the clocking to run directly from the PLL at 50 MHz. // MAP_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ); // // Initialize the console UART and write a message to the terminal. // MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); MAP_GPIOPinConfigure(GPIO_PA0_U0RX); MAP_GPIOPinConfigure(GPIO_PA1_U0TX); MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); UARTStdioInit(0); UARTprintf("\033[2JMemory/UART scatter-gather uDMA example\n\n"); // // Configure UART1 to be used for the loopback peripheral // MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1); // // Configure the UART communication parameters. // MAP_UARTConfigSetExpClk(UART1_BASE, MAP_SysCtlClockGet(), 115200, UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE); // // Set both the TX and RX trigger thresholds to one-half (8 bytes). This // will be used by the uDMA controller to signal when more data should be // transferred. The uDMA TX and RX channels will be configured so that it // can transfer 8 bytes in a burst when the UART is ready to transfer more // data. // MAP_UARTFIFOLevelSet(UART1_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8); // // Enable the UART for operation, and enable the uDMA interface for both TX // and RX channels. // MAP_UARTEnable(UART1_BASE); MAP_UARTDMAEnable(UART1_BASE, UART_DMA_RX | UART_DMA_TX); // // This register write will set the UART to operate in loopback mode. Any // data sent on the TX output will be received on the RX input. // HWREG(UART1_BASE + UART_O_CTL) |= UART_CTL_LBE; // // Enable the UART peripheral interrupts. Note that no UART interrupts // were enabled, but the uDMA controller will cause an interrupt on the // UART interrupt signal when a uDMA transfer is complete. // MAP_IntEnable(INT_UART1); // // Enable the uDMA peripheral clocking. // MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA); // // Enable the uDMA controller. // MAP_uDMAEnable(); // // Point at the control table to use for channel control structures. // MAP_uDMAControlBaseSet(sControlTable); // // Configure the UART TX channel for scatter-gather // Peripheral scatter-gather is used because transfers are gated by // requests from the peripheral // UARTprintf("Configuring UART TX uDMA channel for scatter-gather\n"); #ifndef USE_SGSET_API // // Use the original method for configuring the scatter-gather transfer // uDMAChannelControlSet(UDMA_CHANNEL_UART1TX, UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_4); uDMAChannelTransferSet(UDMA_CHANNEL_UART1TX, UDMA_MODE_PER_SCATTER_GATHER, g_TaskTableSrc, &sControlTable[UDMA_CHANNEL_UART1TX], 6 * 4); #else // // Use the simplified API for configuring the scatter-gather transfer // uDMAChannelScatterGatherSet(UDMA_CHANNEL_UART1TX, 6, g_TaskTableSrc, 1); #endif // // Configure the UART RX channel for scatter-gather task list. // This is set to peripheral s-g because it starts by receiving data // from the UART // UARTprintf("Configuring UART RX uDMA channel for scatter-gather\n"); #ifndef USE_SGSET_API // // Use the original method for configuring the scatter-gather transfer // uDMAChannelControlSet(UDMA_CHANNEL_UART1RX, UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_4); uDMAChannelTransferSet(UDMA_CHANNEL_UART1RX, UDMA_MODE_PER_SCATTER_GATHER, g_TaskTableDst, &sControlTable[UDMA_CHANNEL_UART1RX], 7 * 4); #else // // Use the simplified API for configuring the scatter-gather transfer // uDMAChannelScatterGatherSet(UDMA_CHANNEL_UART1RX, 7, g_TaskTableDst, 1); #endif // // Fill the source buffer with a pattern // for(ulIdx = 0; ulIdx < 1024; ulIdx++) { g_ucSrcBuf[ulIdx] = ulIdx + (ulIdx / 256); } // // Enable the uDMA controller error interrupt. This interrupt will occur // if there is a bus error during a transfer. // IntEnable(INT_UDMAERR); // // Enable the UART RX DMA channel. It will wait for data to be available // from the UART. // UARTprintf("Enabling uDMA channel for UART RX\n"); MAP_uDMAChannelEnable(UDMA_CHANNEL_UART1RX); // // Enable the UART TX DMA channel. Since the UART TX will be asserting // a DMA request (since the TX FIFO is empty), this will cause this // DMA channel to start running. // UARTprintf("Enabling uDMA channel for UART TX\n"); MAP_uDMAChannelEnable(UDMA_CHANNEL_UART1TX); // // Wait for the TX task list to be finished // UARTprintf("Waiting for TX task list to finish ... "); while(!g_bTXdone) { } UARTprintf("done\n"); // // Wait for the RX task list to be finished // UARTprintf("Waiting for RX task list to finish ... "); while(!g_bRXdone) { } UARTprintf("done\n"); // // Verify that all the counters are in the expected state // UARTprintf("Verifying counters\n"); if(g_ulDMAIntCount != 2) { UARTprintf("ERROR in interrupt count, found %d, expected 2\n", g_ulDMAIntCount); } if(g_uluDMAErrCount != 0) { UARTprintf("ERROR in error counter, found %d, expected 0\n", g_uluDMAErrCount); } // // Now verify the contents of the final destination buffer. Compare it // to the original source buffer. // UARTprintf("Verifying buffer contents ... "); for(ulIdx = 0; ulIdx < 1024; ulIdx++) { if(g_ucDstBuf[ulIdx] != g_ucSrcBuf[ulIdx]) { UARTprintf("ERROR\n @ index %d: expected 0x%02X, found 0x%02X\n", ulIdx, g_ucSrcBuf[ulIdx], g_ucDstBuf[ulIdx]); UARTprintf("Checking stopped. There may be additional errors\n"); break; } } if(ulIdx == 1024) { UARTprintf("OK\n"); } // // End of program, loop forever // for(;;) { } }