void mcf523xfec_disable( mcf523xfec_if_t * fecif ) { ( void )fecif; int old_ipl = asm_set_ipl( 7 ); /* Set the Graceful Transmit Stop bit */ MCF_FEC_TCR = ( MCF_FEC_TCR | MCF_FEC_TCR_GTS ); /* Wait for the current transmission to complete */ while( !( MCF_FEC_EIR & MCF_FEC_EIR_GRA ) ); /* Clear the GRA event */ MCF_FEC_EIR = MCF_FEC_EIR_GRA; /* Disable the FEC */ MCF_FEC_ECR = 0; /* Disable all FEC interrupts by clearing the IMR register */ MCF_FEC_EIMR = 0; /* Unconfigure the interrupt controller. */ MCF_INTC0_ICR27 = MCF_INTC0_ICRn_IL( 0 ) | MCF_INTC0_ICRn_IP( 0 ); MCF_INTC0_IMRL |= MCF_INTC0_IMRL_INT_MASK27; /* Clear the GTS bit so frames can be tranmitted when restarted */ MCF_FEC_TCR = ( MCF_FEC_TCR & ~MCF_FEC_TCR_GTS ); /* Disable I/O pins used by the FEC. */ MCF_GPIO_PAR_FECI2C &= ~( MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC ); ( void )asm_set_ipl( old_ipl ); }
BaseType_t xPortStartScheduler( void ) { extern void ( *portVECTOR_TABLE[ ] ) ( ); /* Add entry in vector table for yield system call. */ portVECTOR_TABLE[ portVECTOR_SYSCALL ] = prvPortYield; /* Add entry in vector table for periodic timer. */ portVECTOR_TABLE[ portVECTOR_TIMER ] = prvPortPreemptiveTick; /* Configure the timer for the system clock. */ if ( configTICK_RATE_HZ > 0) { /* Configure prescaler */ MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_OVW; /* Initialize the periodic timer interrupt. */ MCF_PIT_PMR0 = MCF_PIT_MODULUS_REGISTER( configTICK_RATE_HZ ); /* Configure interrupt priority and level and unmask interrupt. */ MCF_INTC0_ICR36 = MCF_INTC0_ICRn_IL( 0x1 ) | MCF_INTC0_ICRn_IP( 0x1 ); MCF_INTC0_IMRH &= ~( MCF_INTC0_IMRH_INT_MASK36 | MCF_INTC0_IMRH_MASKALL ); /* Enable interrupts */ MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_EN | MCF_PIT_PCSR_PIF; } /* Restore the context of the first task that is going to run. */ portRESTORE_CONTEXT( ); /* Should not get here. */ return pdTRUE; }
void mcf523xfec_enable( mcf523xfec_if_t * fecif ) { ( void )fecif; int old_ipl = asm_set_ipl( 7 ); /* Configure I/O pins for the FEC. */ MCF_GPIO_PAR_FECI2C = ( MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC ); /* Allow interrupts by setting IMR register */ MCF_FEC_EIMR = MCF_FEC_EIMR_RXF; /* Configure the interrupt controller. */ MCF_INTC0_ICR27 = ( MCF_INTC0_ICRn_IL( MCF_FEC_INT_LEVEL ) | MCF_INTC0_ICRn_IP( MCF_FEC_INT_PRIORITY ) ); MCF_INTC0_IMRL &= ~( MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_MASKALL ); /* Enable FEC */ MCF_FEC_ECR = MCF_FEC_ECR_ETHER_EN; /* Indicate that there have been empty receive buffers produced */ MCF_FEC_RDAR = 1; ( void )asm_set_ipl( old_ipl ); }