status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
{
/*
This function is designed to change MCG to PBE mode from PEE/BLPE/FBE,
but with this workflow, the source mode could be all modes except PEI/PBI.
*/
MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
/* Change to use external clock first. */
MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
/* Wait for CLKST clock status bits to show clock source is ext ref clk */
while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
(MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
{
}
/* Disable PLL first, then configure PLL. */
MCG->C6 &= ~MCG_C6_PLLS_MASK;
while (MCG->S & MCG_S_PLLST_MASK)
{
}
/* Configure the PLL. */
{
CLOCK_EnablePll0(config);
}
/* Change to PLL mode. */
MCG->C6 |= MCG_C6_PLLS_MASK;
while (!(MCG->S & MCG_S_PLLST_MASK))
{
}
return kStatus_Success;
}
/*
** ===================================================================
** Method : Cpu_SetMCGModePEE (component MK21FN1M0MC12)
**
** Description :
** This method sets the MCG to PEE mode.
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
static void Cpu_SetMCGModePEE(uint8_t CLKMode)
{
switch (CLKMode) {
case 0U:
/* Switch to PEE Mode */
/* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=1,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC_CR = (OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK);
/* MCG_C7: OSCSEL=0 */
MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03));
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK);
/* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
MCG_C5 = MCG_C5_PRDIV0(0x01);
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x06));
while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
}
break;
default:
break;
}
}
/************************************************************************************************
* SetPLL_Kinetis
* 系统的锁相环设定，其完成的主要工作为: 设定CoreClock、BusClock、FlexClock、FlashClock
* (设置的具体频率在KinetisConfig.h中配置)
************************************************************************************************/
static void SetPLL_Kinetis(void)
{
K_int32u_t temp_reg;
K_int8u_t i;
// First move to FBE mode
// Enable external oscillator, RANGE=2, HGO=1, EREFS=1, LP=0, IRCS=0
MCG_C2 = MCG_C2_RANGE(1) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;
// after initialization of oscillator release latched state of oscillator and GPIO
SIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;
LLWU_CS |= LLWU_CS_ACKISO_MASK;
// Select external oscilator and Reference Divider and clear IREFS to start ext osc
// CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
/* if we aren't using an osc input we don't need to wait for the osc to init */
while (MCG_S & MCG_S_IREFST_MASK){}; // wait for Reference clock Status bit to clear
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}; // Wait for clock status bits to show clock source is ext ref clk
// Now in FBE
/* 设定PLL时钟 */
#if CORE_CLK_Kinetis <= 110
MCG_C5 = MCG_C5_PRDIV(REF_CLK_Kinetis/2 - 1); /* PLLCLK == 2MHz */
#else
#if REF_CLK_Kinetis % 3 == 0
MCG_C5 = MCG_C5_PRDIV(REF_CLK_Kinetis/3 - 1); /* PLLCLK == 3MHz */
#elif REF_CLK_Kinetis % 4 == 0
MCG_C5 = MCG_C5_PRDIV(REF_CLK_Kinetis/4 - 1); /* PLLCLK == 4MHz */
#elif REF_CLK_Kinetis % 5 == 0
MCG_C5 = MCG_C5_PRDIV(REF_CLK_Kinetis*2/5 - 1); /* PLLCLK == 2.5MHz */
#endif
#endif
/*
* Ensure MCG_C6 is at the reset default of 0. LOLIE disabled,
* PLL disabled, clk monitor disabled, PLL VCO divider is clear
*/
MCG_C6 = 0x0;
/* 设定各时钟的分频数 */
temp_reg = FMC_PFAPR; // store present value of FMC_PFAPR
// set M0PFD through M7PFD to 1 to disable prefetch
FMC_PFAPR |= FMC_PFAPR_M7PFD_MASK | FMC_PFAPR_M6PFD_MASK | FMC_PFAPR_M5PFD_MASK
| FMC_PFAPR_M4PFD_MASK | FMC_PFAPR_M3PFD_MASK | FMC_PFAPR_M2PFD_MASK
| FMC_PFAPR_M1PFD_MASK | FMC_PFAPR_M0PFD_MASK;
// set clock dividers to desired value
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0)
| SIM_CLKDIV1_OUTDIV2(DIV_BusClk_Kinetis - 1)
| SIM_CLKDIV1_OUTDIV3(DIV_FlexClk_Kinetis - 1)
| SIM_CLKDIV1_OUTDIV4(DIV_FlashClk_Kinetis - 1);
// wait for dividers to change
for (i = 0 ; i < DIV_FlashClk_Kinetis ; i++) {}
FMC_PFAPR = temp_reg; // re-store original value of FMC_PFAPR
/* 设置倍频数,倍频数为VDIV+24 */
#if CORE_CLK_Kinetis <= 110
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(CORE_CLK_Kinetis/2 - 24);
#else
#if REF_CLK_Kinetis % 3 == 0
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(CORE_CLK_Kinetis/3 - 24);
#elif REF_CLK_Kinetis % 4 == 0
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(CORE_CLK_Kinetis/4 - 24);
#elif REF_CLK_Kinetis % 5 == 0
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(CORE_CLK_Kinetis*2/5 - 24);
#endif
#endif
while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
// Now running PBE Mode
// Transition into PEE by setting CLKS to 0
// CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
MCG_C1 &= ~MCG_C1_CLKS_MASK;
// Wait for clock status bits to update
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};
}
/*!
* @brief PLL超频
* @param PLL_e 频率设置参数
* @return 超频频率（MHz）
* @since v5.0
* @warning 此函数只能在 复位后没进行任何频率设置情况下调用，即MCG在FEI模式下才可调用
* Sample usage: uint8 clk = pll_init(PLL100); //超频
*/
uint8 pll_init(PLL_e pll)
{
mcg_div_count( pll);
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; //PTA18 和 PTA19 用于 晶振
// set clock dividers to desired value
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(mcg_div.core_div) | SIM_CLKDIV1_OUTDIV4(mcg_div.bus_div);
//上电复位后，单片机会自动进入 FEI 模式，使用 内部参考时钟
//FEI -> FBE
OSC0_CR = ( 0
| OSC_CR_ERCLKEN_MASK //使能 外部参考时钟
//| OSC_CR_SC2P_MASK //配置电容
//| OSC_CR_SC4P_MASK //配置电容
//| OSC_CR_SC8P_MASK //配置电容
| OSC_CR_SC16P_MASK //配置电容
);
MCG_C2 = ( 0
| MCG_C2_RANGE0(2)
| MCG_C2_EREFS0_MASK
);
MCG_C1 = (0
| MCG_C1_CLKS(2)
| MCG_C1_FRDIV(7)
| MCG_C1_IRCLKEN_MASK
);
while (MCG_S & MCG_S_IREFST_MASK) {}; //等待FLL参考时钟 为 外部参考时钟（S[IREFST]=0，表示使用外部参考时钟，）
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(0x2)) {}; //等待选择外部参考时钟
//现在已经进入了 FBE模式
//FBE -> PBE
MCG_C5 = MCG_C5_PRDIV0(mcg_cfg[pll].prdiv); //分频， EXTAL_IN_MHz/( PRDIV+1)
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(mcg_cfg[pll].vdiv) ; //倍频， EXTAL_IN_MHz/( PRDIV+1) * (VDIV+24)
while (!(MCG_S & MCG_S_PLLST_MASK)) {}; //等待时钟源选择PLL
while (!(MCG_S & MCG_S_LOCK0_MASK)) {}; //等待 PLL锁了（锁相环）
// 现在已经进入了 PBE 模式
// PBE -> PEE
//MCG_C1 &= ~MCG_C1_CLKS_MASK;
MCG_C1 = MCG_C1_IRCLKEN_MASK;
while (((MCG_S & MCG_S_CLKST_MASK) ) != MCG_S_CLKST(0x3)) {};//等待选择输出PLL
// 现在已经进入了 PEE 模式
SIM_SOPT2 |= (0 //选择 PLL时钟
| SIM_SOPT2_PLLFLLSEL_MASK
);
return mcg_cfg[pll].clk;
} //pll_init
/**
* @brief K20x clock initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function is meant to be invoked early during the system
* initialization, it is usually invoked from the file
* @p board.c.
* @todo This function needs to be more generic.
*
* @special
*/
void k20x_clock_init(void) {
#if !KINETIS_NO_INIT
/* Disable the watchdog */
WDOG->UNLOCK = 0xC520;
WDOG->UNLOCK = 0xD928;
WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN;
SIM->SCGC5 |= SIM_SCGC5_PORTA |
SIM_SCGC5_PORTB |
SIM_SCGC5_PORTC |
SIM_SCGC5_PORTD |
SIM_SCGC5_PORTE;
#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
/* This is the default mode at reset. */
/* Configure FEI mode */
MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
(KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
/* Set clock dividers */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); /* not strictly necessary since usb_lld will set this */
#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
uint32_t ratio, frdiv;
uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
uint8_t i;
/* EXTAL0 and XTAL0 */
PORTA->PCR[18] = 0;
PORTA->PCR[19] = 0;
/*
* Start in FEI mode
*/
/* Internal capacitors for crystal */
#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
/* Disable the internal capacitors */
OSC0->CR = 0;
#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
/* TODO: need to add more flexible calculation, specially regarding
* divisors which may not be available depending on the XTAL
* frequency, which would required other registers to be modified.
*/
/* Enable OSC, low power mode */
MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0;
if (KINETIS_XTAL_FREQUENCY > 8000000UL)
MCG->C2 |= MCG_C2_RANGE0(2);
else
MCG->C2 |= MCG_C2_RANGE0(1);
frdiv = 7;
ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
for (i = 0; i < ratio_quantity; ++i) {
if (ratio == ratios[i]) {
frdiv = i;
break;
}
}
/* Switch to crystal as clock source, FLL input of 31.25 KHz */
MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(frdiv);
/* Wait for crystal oscillator to begin */
while (!(MCG->S & MCG_S_OSCINIT0));
/* Wait for the FLL to use the oscillator */
while (MCG->S & MCG_S_IREFST);
/* Wait for the MCGOUTCLK to use the oscillator */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));
/*
* Now in FBE mode
*/
#define KINETIS_PLLIN_FREQUENCY 2000000UL
/*
* Config PLL input for 2 MHz
* TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz
*/
MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
/*
* Config PLL output to match KINETIS_SYSCLK_FREQUENCY
* TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match
*/
for(i = 24; i < 56; i++)
{
if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY))
{
/* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
break;
}
}
if(i>=56) /* Config PLL for 96 MHz output as default setting */
MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
/* Wait for PLL to start using crystal as its input, and to lock */
while ((MCG->S & (MCG_S_PLLST|MCG_S_LOCK0))!=(MCG_S_PLLST|MCG_S_LOCK0));
/*
* Now in PBE mode
*/
/* Set the PLL dividers for the different clocks */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL;
/* Switch to PLL as clock source */
MCG->C1 = MCG_C1_CLKS(0);
/* Wait for PLL clock to be used */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
/*
* Now in PEE mode
*/
#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
#error Unimplemented KINETIS_MCG_MODE
#endif /* KINETIS_MCG_MODE == ... */
#endif /* !KINETIS_NO_INIT */
}
status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
{
mcg_mode_t next_mode;
status_t status = kStatus_Success;
mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0;
/* If need to change external clock, MCG_C7[OSCSEL]. */
if (MCG_C7_OSCSEL_VAL != config->oscsel)
{
/* If external clock is in use, change to FEI first. */
if (!(MCG->S & MCG_S_IRCST_MASK))
{
CLOCK_ExternalModeToFbeModeQuick();
CLOCK_SetFeiMode(config->dmx32, config->drs, (void (*)(void))0);
}
CLOCK_SetExternalRefClkConfig(config->oscsel);
}
/* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt)
{
MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
{
CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
}
}
/* Configure MCGIRCLK. */
CLOCK_SetInternalRefClkConfig(config->irclkEnableMode, config->ircs, config->fcrdiv);
next_mode = CLOCK_GetMode();
do
{
next_mode = mcgModeMatrix[next_mode][config->mcgMode];
switch (next_mode)
{
case kMCG_ModeFEI:
status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
break;
case kMCG_ModeFEE:
status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
break;
case kMCG_ModeFBI:
status = CLOCK_SetFbiMode(config->dmx32, config->drs, (void (*)(void))0);
break;
case kMCG_ModeFBE:
status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0);
break;
case kMCG_ModeBLPI:
status = CLOCK_SetBlpiMode();
break;
case kMCG_ModeBLPE:
status = CLOCK_SetBlpeMode();
break;
case kMCG_ModePBE:
/* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode))
{
{
status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
}
}
else
{
MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
{
}
}
break;
case kMCG_ModePEE:
status = CLOCK_SetPeeMode();
break;
default:
break;
}
if (kStatus_Success != status)
{
return status;
}
} while (next_mode != config->mcgMode);
if (config->pll0Config.enableMode & kMCG_PllEnableIndependent)
{
CLOCK_EnablePll0(&config->pll0Config);
}
else
{
MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent;
}
return kStatus_Success;
}
/**
* @brief MK20D5 clock initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function is meant to be invoked early during the system
* initialization, it is usually invoked from the file
* @p board.c.
* @todo This function needs to be more generic.
*
* @special
*/
void mk20d50_clock_init(void) {
uint32_t ratio, frdiv;
uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
int ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
int i;
/* Disable the watchdog */
WDOG->UNLOCK = 0xC520;
WDOG->UNLOCK = 0xD928;
WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN;
SIM->SCGC5 |= SIM_SCGC5_PORTA |
SIM_SCGC5_PORTB |
SIM_SCGC5_PORTC |
SIM_SCGC5_PORTD |
SIM_SCGC5_PORTE;
/* EXTAL0 and XTAL0 */
PORTA->PCR[18] = 0;
PORTA->PCR[19] = 0;
/*
* Start in FEI mode
*/
/* Disable capacitors for crystal */
OSC->CR = 0;
/* TODO: need to add more flexible calculation, specially regarding
* divisors which may not be available depending on the XTAL
* frequency, which would required other registers to be modified.
*/
/* Enable OSC, low power mode */
MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0;
if (KINETIS_XTAL_FREQUENCY > 8000000)
MCG->C2 |= MCG_C2_RANGE0(2);
else
MCG->C2 |= MCG_C2_RANGE0(1);
frdiv = 7;
ratio = KINETIS_XTAL_FREQUENCY / 31250;
for (i = 0; i < ratio_quantity; ++i) {
if (ratio == ratios[i]) {
frdiv = i;
break;
}
}
/* Switch to crystal as clock source, FLL input of 31.25 KHz */
MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(frdiv);
/* Wait for crystal oscillator to begin */
while (!(MCG->S & MCG_S_OSCINIT0));
/* Wait for the FLL to use the oscillator */
while (MCG->S & MCG_S_IREFST);
/* Wait for the MCGOUTCLK to use the oscillator */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));
/*
* Now in FBE mode
*/
/* Config PLL input for 2 MHz */
MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY / 2000000) - 1);
/* Config PLL for 96 MHz output */
MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
/* Wait for PLL to start using crystal as its input */
while (!(MCG->S & MCG_S_PLLST));
/* Wait for PLL to lock */
while (!(MCG->S & MCG_S_LOCK0));
/*
* Now in PBE mode
*/
/* Switch to PLL as clock source */
MCG->C1 = MCG_C1_CLKS(0);
/* Wait for PLL clock to be used */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
/*
* Now in PEE mode
*/
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void) {
// system dividers
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(5);
// after reset, we are in FEI mode
// enable external clock source - OSC0
#if __SYS_OSC_CLK <= 8000000
MCG_C2 = MCG_C2_LOCRE0_MASK | MCG_C2_RANGE(RANGE0_VAL) | (/*hgo_val*/0 << MCG_C2_HGO_SHIFT) | (/*erefs_val*/0 << MCG_C2_EREFS_SHIFT);
#else
// On rev. 1.0 of silicon there is an issue where the the input bufferd are enabled when JTAG is connected.
// This has the affect of sometimes preventing the oscillator from running. To keep the oscillator amplitude
// low, RANGE = 2 should not be used. This should be removed when fixed silicon is available.
MCG_C2 = MCG_C2_LOCRE_MASK | MCG_C2_RANGE(2) | (/*hgo_val*/0 << MCG_C2_HGO_SHIFT) | (/*erefs_val*/0 << MCG_C2_EREFS_SHIFT);
// MCG_C2 = MCG_C2_LOCRE_MASK | MCG_C2_RANGE(1) | (/*hgo_val*/0 << MCG_C2_HGO_SHIFT) | (/*erefs_val*/0 << MCG_C2_EREFS_SHIFT);
#endif
// select clock mode, we want FBE mode
// CLKS = 2, FRDIV = frdiv_val, IREFS = 0, IRCLKEN = 0, IREFSTEN = 0
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(FRDIV_VAL);
/* wait until the MCG has moved into the proper mode */
// if the external oscillator is used need to wait for OSCINIT to set
// for (i = 0 ; i < 10000 ; i++)
// {
// if (MCG_S & MCG_S_OSCINIT_MASK) break; // jump out early if OSCINIT sets before loop finishes
// }
// if (!(MCG_S & MCG_S_OSCINIT_MASK)) return 0x23; // check bit is really set and return with error if not set
// wait for reference clock status bit is cleared and clock source is ext ref clk
while ((MCG_S & MCG_S_IREFST_MASK) || MCG_S_CLKST(2) != (MCG_S & MCG_S_CLKST_MASK));
// ... FBE mode
// enable clock monitor for osc0
MCG_C6 = MCG_C6_CME_MASK;
// PLL0
MCG_C5 = MCG_C5_PRDIV(PRDIV_VAL - 1); // set PLL0 ref divider, osc0 is reference
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(VDIV_VAL - 16); // set VDIV and enable PLL
// wait to lock...
while (!(MCG_S & MCG_S_PLLST_MASK));
while (!(MCG_S & MCG_S_LOCK_MASK));
// // Use actual PLL settings to calculate PLL frequency
// prdiv = ((MCG_C5 & MCG_C5_PRDIV_MASK) + 1);
// vdiv = ((MCG_C6 & MCG_C6_VDIV_MASK) + 16);
// ... PBE mode
MCG_C1 &= ~MCG_C1_CLKS_MASK; // CLKS = 0, select PLL as MCG_OUT
while (MCG_S_CLKST(3) != (MCG_S & MCG_S_CLKST_MASK));
// ... PEE mode
/* ToDo: add code to initialize the system
do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
SystemCoreClock = __SYSTEM_CLOCK;
}
status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
{
uint8_t mcg_c4;
bool change_drs = false;
#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
mcg_mode_t mode = CLOCK_GetMode();
if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
(kMCG_ModeBLPI == mode)))
{
return kStatus_MCG_ModeUnreachable;
}
#endif
mcg_c4 = MCG->C4;
MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
/*
Errata: ERR007993
Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
reference clock source changes, then reset to previous value after
reference clock changes.
*/
if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
{
change_drs = true;
/* Change the LSB of DRST_DRS. */
MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
}
/* Set CLKS and IREFS. */
MCG->C1 =
((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */
| MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
/* Wait and check status. */
while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
{
}
/* Errata: ERR007993 */
if (change_drs)
{
MCG->C4 = mcg_c4;
}
while (kMCG_ClkOutStatInt != MCG_S_CLKST_VAL)
{
}
MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs));
/* Wait for FLL stable time. */
if (fllStableDelay)
{
fllStableDelay();
}
return kStatus_Success;
}
/*
** ===================================================================
** Method : Cpu_SetOperationMode (component MK22FN512VDC12)
**
** Description :
** This method requests to change the component's operation
** mode (RUN, WAIT, SLEEP, STOP). The target operation mode
** will be entered immediately.
** See <Operation mode settings> for further details of the
** operation modes mapping to low power modes of the cpu.
** Parameters :
** NAME - DESCRIPTION
** OperationMode - Requested driver
** operation mode
** ModeChangeCallback - Callback to
** notify the upper layer once a mode has been
** changed. Parameter is ignored, only for
** compatibility of API with other components.
** * ModeChangeCallbackParamPtr
** - Pointer to callback parameter to notify
** the upper layer once a mode has been
** changed. Parameter is ignored, only for
** compatibility of API with other components.
** Returns :
** --- - Error code
** ERR_OK - OK
** ERR_PARAM_MODE - Invalid operation mode
** ===================================================================
*/
LDD_TError Cpu_SetOperationMode(LDD_TDriverOperationMode OperationMode, LDD_TCallback ModeChangeCallback, LDD_TCallbackParam *ModeChangeCallbackParamPtr)
{
(void) ModeChangeCallback; /* Parameter is not used, suppress unused argument warning */
(void) ModeChangeCallbackParamPtr; /* Parameter is not used, suppress unused argument warning */
switch (OperationMode) {
case DOM_HSRUN:
SMC_PMPROT = SMC_PMPROT_AHSRUN_MASK;
SMC_PMCTRL |= SMC_PMCTRL_RUNM(3); /*HS RUN */
while((SMC_PMSTAT & SMC_PMSTAT_PMSTAT_MASK) != SMC_PMSTAT_PMSTAT(0x80)) { /* HS RUN status */
};
/* SCB_SCR: SLEEPDEEP=0,SLEEPONEXIT=0 */
SCB_SCR &= (uint32_t)~(uint32_t)(
SCB_SCR_SLEEPDEEP_MASK |
SCB_SCR_SLEEPONEXIT_MASK
);
if (ClockConfigurationID != 2U) {
if ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) { /* If in PBE mode, switch to PEE. PEE to PBE transition was caused by wakeup from low power mode. */
/* MCG_C1: CLKS=0,IREFS=0 */
MCG_C1 &= (uint8_t)~(uint8_t)((MCG_C1_CLKS(0x03) | MCG_C1_IREFS_MASK));
while( (MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait for PLL lock */
}
}
}
break;
case DOM_RUN:
SMC_PMCTRL &= ~(SMC_PMCTRL_RUNM(3)); /*Normal RUN */
while((SMC_PMSTAT & SMC_PMSTAT_PMSTAT_MASK) != SMC_PMSTAT_PMSTAT(0x1)) { /* Normal RUN status */
};
/* SCB_SCR: SLEEPDEEP=0,SLEEPONEXIT=0 */
SCB_SCR &= (uint32_t)~(uint32_t)(
SCB_SCR_SLEEPDEEP_MASK |
SCB_SCR_SLEEPONEXIT_MASK
);
if (ClockConfigurationID != 2U) {
if ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) { /* If in PBE mode, switch to PEE. PEE to PBE transition was caused by wakeup from low power mode. */
/* MCG_C1: CLKS=0,IREFS=0 */
MCG_C1 &= (uint8_t)~(uint8_t)((MCG_C1_CLKS(0x03) | MCG_C1_IREFS_MASK));
while( (MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait for PLL lock */
}
}
}
break;
case DOM_WAIT:
/* SCB_SCR: SLEEPDEEP=0 */
SCB_SCR &= (uint32_t)~(uint32_t)(SCB_SCR_SLEEPDEEP_MASK);
/* SCB_SCR: SLEEPONEXIT=0 */
SCB_SCR &= (uint32_t)~(uint32_t)(SCB_SCR_SLEEPONEXIT_MASK);
PE_WFI();
break;
case DOM_SLEEP:
/* SCB_SCR: SLEEPDEEP=1 */
SCB_SCR |= SCB_SCR_SLEEPDEEP_MASK;
/* SMC_PMCTRL: STOPM=0 */
SMC_PMCTRL &= (uint8_t)~(uint8_t)(SMC_PMCTRL_STOPM(0x07));
(void)(SMC_PMCTRL == 0U); /* Dummy read of SMC_PMCTRL to ensure the register is written before enterring low power mode */
/* SCB_SCR: SLEEPONEXIT=1 */
SCB_SCR |= SCB_SCR_SLEEPONEXIT_MASK;
PE_WFI();
break;
case DOM_STOP:
break;
default:
return ERR_PARAM_MODE;
}
return ERR_OK;
}
/*! @brief Sets up the clock out of RESET
*
*/
void clock_initialise(void) {
#if (CLOCK_MODE == CLOCK_MODE_NONE)
// No clock setup
#else
// XTAL/EXTAL Pins
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
PORTA->PCR[3] = PORT_PCR_MUX(0);
PORTA->PCR[4] = PORT_PCR_MUX(0);
// Configure the Crystal Oscillator
RTC->CR = RTC_CR_WPE_M|RTC_CR_SUP_M|RTC_CR_UM_M|RTC_CR_OSCE_M|RTC_CR_CLKO_M|RTC_CR_SCP_M;
// Fast Internal Clock divider
MCG->SC = MCG_SC_FCRDIV_M;
// Out of reset MCG is in FEI mode
// =============================================================
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(7) | SIM_CLKDIV1_OUTDIV3(3) | SIM_CLKDIV1_OUTDIV4(7);
// Switch from FEI -> FEI/FBI/FEE/FBE
// =============================================================
// Set up crystal or external clock source
MCG->C2 =
MCG_C2_LOCRE0_M | // LOCRE0 = 0,1 -> Loss of clock reset enable
MCG_C2_RANGE0_M | // RANGE0 = 0,1,2 -> Oscillator low/high/very high clock range
MCG_C2_HGO0_M | // HGO0 = 0,1 -> Oscillator low power/high gain
MCG_C2_EREFS0_M | // EREFS0 = 0,1 -> Select external clock/crystal oscillator
MCG_C2_IRCS_M; // IRCS = 0,1 -> Select slow/fast internal clock for internal reference
#if ((CLOCK_MODE == CLOCK_MODE_FEI) || (CLOCK_MODE == CLOCK_MODE_FBI) || (CLOCK_MODE == CLOCK_MODE_BLPI) )
// Transition via FBI
//=====================================
#define BYPASS (1) // CLKS value used while FLL locks
MCG->C1 = MCG_C1_CLKS(BYPASS) | // CLKS = X -> External reference source while PLL locks
MCG_C1_FRDIV_M | // FRDIV = N -> XTAL/2^n ~ 31.25 kHz
MCG_C1_IREFS_M | // IREFS = 0,1 -> External/Slow IRC for FLL source
MCG_C1_IRCLKEN_M | // IRCLKEN = 0,1 -> IRCLK disable/enable
MCG_C1_IREFSTEN_M; // IREFSTEN = 0,1 -> Internal reference enabled in STOP mode
// Wait for S_IREFST to indicate FLL Reference has switched
do {
__asm__("nop");
} while ((MCG->S & MCG_S_IREFST_MASK) != (MCG_C1_IREFS_V<<MCG_S_IREFST_SHIFT));
// Wait for S_CLKST to indicating that OUTCLK has switched to bypass PLL/FLL
do {
__asm__("nop");
} while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(BYPASS));
// Set FLL Parameters
MCG->C4 = (MCG->C4&~(MCG_C4_DMX32_MASK|MCG_C4_DRST_DRS_MASK))|MCG_C4_DMX32_M|MCG_C4_DRST_DRS_M;
#endif
#if ((CLOCK_MODE == CLOCK_MODE_FBE) || (CLOCK_MODE == CLOCK_MODE_FEE) || (CLOCK_MODE == CLOCK_MODE_PLBE) || (CLOCK_MODE == CLOCK_MODE_PBE) || (CLOCK_MODE == CLOCK_MODE_PEE))
// Transition via FBE
//=====================================
#define BYPASS (2) // CLKS value used while PLL locks
MCG->C1 = MCG_C1_CLKS(BYPASS) | // CLKS = 2 -> External reference source while PLL locks
MCG_C1_FRDIV_M | // FRDIV = N -> XTAL/2^n ~ 31.25 kHz
MCG_C1_IREFS_M | // IREFS = 0,1 -> External/Slow IRC for FLL source
MCG_C1_IRCLKEN_M | // IRCLKEN = 0,1 -> IRCLK disable/enable
MCG_C1_IREFSTEN_M; // IREFSTEN = 0,1 -> Internal reference enabled in STOP mode
#if (MCG_C2_EREFS_V != 0)
// Wait for oscillator stable (if used)
do {
__asm__("nop");
} while ((MCG->S & MCG_S_OSCINIT0_MASK) == 0);
#endif
// Wait for S_IREFST to indicate FLL Reference has switched
do {
__asm__("nop");
} while ((MCG->S & MCG_S_IREFST_MASK) != (MCG_C1_IREFS_V<<MCG_S_IREFST_SHIFT));
// Wait for S_CLKST to indicating that OUTCLK has switched to bypass PLL/FLL
do {
__asm__("nop");
} while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(BYPASS));
// Set FLL Parameters
MCG->C4 = (MCG->C4&~(MCG_C4_DMX32_MASK|MCG_C4_DRST_DRS_MASK))|MCG_C4_DMX32_M|MCG_C4_DRST_DRS_M;
#endif
// Select FEI/FBI/FEE/FBE clock mode
MCG->C1 = MCG_C1_CLKS_M | // CLKS = 0,1,2 -> Select FLL/IRCSCLK/ERCLK
MCG_C1_FRDIV_M | // FRDIV = N -> XTAL/2^n ~ 31.25 kHz
MCG_C1_IREFS_M | // IREFS = 0,1 -> External/Slow IRC for FLL source
MCG_C1_IRCLKEN_M | // IRCLKEN = 0,1 -> IRCLK disable/enable
MCG_C1_IREFSTEN_M; // IREFSTEN = 0,1 -> Internal reference enabled in STOP mode
// Wait for mode change
do {
__asm__("nop");
} while ((MCG->S & MCG_S_IREFST_MASK) != (MCG_C1_IREFS_V<<MCG_S_IREFST_SHIFT));
#if defined (MCG_C6_PLLS_V) && (MCG_C1_CLKS_V == 0) // FLL or PLL
#define MCG_S_CLKST_M MCG_S_CLKST(MCG_C6_PLLS_V?3:0)
#else
#define MCG_S_CLKST_M MCG_S_CLKST(MCG_C1_CLKS_V)
#endif
// Wait for S_CLKST to indicating that OUTCLK has switched
do {
__asm__("nop");
} while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_M);
// Set the SIM _CLKDIV dividers
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1_M | SIM_CLKDIV1_OUTDIV2_M | SIM_CLKDIV1_OUTDIV3_M | SIM_CLKDIV1_OUTDIV4_M;
#if (CLOCK_MODE == CLOCK_MODE_BLPE) || (CLOCK_MODE == CLOCK_MODE_BLPI)
// Select BLPE/BLPI clock mode
MCG->C2 =
MCG_C2_LOCRE0_M | // LOCRE0 = 0,1 -> Loss of clock reset
MCG_C2_RANGE0_M | // RANGE0 = 0,1,2 -> Oscillator low/high/very high clock range
MCG_C2_HGO0_M | // HGO0 = 0,1 -> Oscillator low power/high gain
MCG_C2_EREFS0_M | // EREFS0 = 0,1 -> Select external clock/crystal oscillator
MCG_C2_LP_M | // LP = 0,1 -> Select FLL enabled/disabled in bypass mode
MCG_C2_IRCS_M; // IRCS = 0,1 -> Select slow/fast internal clock for internal reference
#endif // (CLOCK_MODE == CLOCK_MODE_BLPE) || (CLOCK_MODE == CLOCK_MODE_BLPI)
#endif // (CLOCK_MODE == CLOCK_MODE_NONE)
/*!
* SOPT1 Clock multiplexing
*/
#if defined(SIM_SOPT1_OSC32KSEL_MASK) && defined(SIM_SOPT1_OSC32KSEL_M) // ERCLK32K source
SIM->SOPT1 = (SIM->SOPT1&~SIM_SOPT1_OSC32KSEL_MASK)|SIM_SOPT1_OSC32KSEL_M;
#endif
/*!
* SOPT2 Clock multiplexing
*/
#if defined(SIM_SOPT2_SDHCSRC_MASK) && defined(SIM_SOPT2_SDHCSRC_M) // SDHC clock
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_SDHCSRC_MASK)|SIM_SOPT2_SDHCSRC_M;
#endif
#if defined(SIM_SOPT2_TIMESRC_MASK) && defined(SIM_SOPT2_TIMESRC_M) // Ethernet time-stamp clock
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_TIMESRC_MASK)|SIM_SOPT2_TIMESRC_M;
#endif
#if defined(SIM_SOPT2_RMIISRC_MASK) && defined(SIM_SOPT2_RMIISRC_M) // RMII clock
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_RMIISRC_MASK)|SIM_SOPT2_RMIISRC_M;
#endif
#ifdef SIM_SCGC4_USBOTG_MASK
// !! WARNING !! The USB interface must be disabled for clock changes to have effect !! WARNING !!
SIM->SCGC4 &= ~SIM_SCGC4_USBOTG_MASK;
#endif
#if defined(SIM_SOPT2_USBSRC_MASK) && defined(SIM_SOPT2_USBSRC_M) // USB clock (48MHz req.)
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_USBSRC_MASK)|SIM_SOPT2_USBSRC_M;
#endif
#if defined(SIM_SOPT2_USBFSRC_MASK) && defined(SIM_SOPT2_USBFSRC_M) // USB clock (48MHz req.)
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_USBFSRC_MASK)|SIM_SOPT2_USBFSRC_M;
#endif
#if defined(SIM_SOPT2_PLLFLLSEL_MASK) && defined(SIM_SOPT2_PLLFLLSEL_M) // Peripheral clock
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_PLLFLLSEL_MASK)|SIM_SOPT2_PLLFLLSEL_M;
#endif
#if defined(SIM_SOPT2_UART0SRC_MASK) && defined(SIM_SOPT2_UART0SRC_M) // UART0 clock
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_UART0SRC_MASK)|SIM_SOPT2_UART0SRC_M;
#endif
#if defined(SIM_SOPT2_TPMSRC_MASK) && defined(SIM_SOPT2_TPMSRC_M) // TPM clock
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_TPMSRC_MASK)|SIM_SOPT2_TPMSRC_M;
#endif
#if defined(SIM_SOPT2_CLKOUTSEL_MASK) && defined(SIM_SOPT2_CLKOUTSEL_M)
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_CLKOUTSEL_MASK)|SIM_SOPT2_CLKOUTSEL_M;
#endif
#if defined(SIM_SOPT2_RTCCLKOUTSEL_MASK) && defined(SIM_SOPT2_RTCCLKOUTSEL_M)
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_RTCCLKOUTSEL_MASK)|SIM_SOPT2_RTCCLKOUTSEL_M;
#endif
#if defined(SIM_CLKDIV2_USBDIV_MASK) && defined(SIM_CLKDIV2_USBFRAC_MASK) && defined(SIM_CLKDIV2_USB_M)
SIM->CLKDIV2 = (SIM->CLKDIV2&~(SIM_CLKDIV2_USBDIV_MASK|SIM_CLKDIV2_USBFRAC_MASK)) | SIM_CLKDIV2_USB_M;
#endif
SystemCoreClockUpdate();
}
void Boot_Init_Clock(void){
/* System clock initialization */
/* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x03)); /* Set the system prescalers to safe value */
/* SIM_SCGC5: PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {
/* PMC_REGSC: ACKISO=1 */
PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */
}
/* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
/* SIM_SOPT2: PLLFLLSEL=1 */
SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=3 */
SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
/* SIM_SOPT2: TPMSRC=1 */
SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)(
SIM_SOPT2_TPMSRC(0x02)
)) | (uint32_t)(
SIM_SOPT2_TPMSRC(0x01)
)); /* Set the TPM clock */
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* PORTA_PCR19: ISF=0,MUX=0 */
PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* Switch to FBE Mode */
/* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
MCG_C2 = (uint8_t)((MCG_C2 & (uint8_t)~(uint8_t)(
MCG_C2_LOCRE0_MASK |
MCG_C2_RANGE0(0x01) |
MCG_C2_HGO0_MASK |
MCG_C2_LP_MASK |
MCG_C2_IRCS_MASK
)) | (uint8_t)(
MCG_C2_RANGE0(0x02) |
MCG_C2_EREFS0_MASK
));
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0_CR = OSC_CR_ERCLKEN_MASK;
/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK);
/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
MCG_C5 = MCG_C5_PRDIV0(0x03);
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG_C6 = MCG_C6_VDIV0(0x00);
while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to PBE Mode */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x00));
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
}
/* Switch to PEE Mode */
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK);
while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
}
/* MCG_C6: CME0=1 */
MCG_C6 |= MCG_C6_CME0_MASK; /* Enable the clock monitor */
/*** End of PE initialization code after reset ***/
}
void __startup(void) {
// The CPU has a watchdog feature which is on by default,
// so we have to configure it to not have nasty reset-surprises
// later on.
startup_watchdog_hook();
// If the system was in VLLS mode, some peripherials and
// the I/O pins are in latched mode. We need to restore
// config and can then acknowledge the isolation to get back
// to normal. For now, we'll just ack TODO: properly do this
if (PMC_REGSC & PMC_REGSC_ACKISO_MASK) PMC_REGSC |= PMC_REGSC_ACKISO_MASK;
// There is a write-once-after-reset register that allows to
// set which power states are available. Let's set it here.
SMC_PMPROT = ENABLED_POWER_MODES;
// For the sake of simplicity, enable all GPIO port clocks
SIM_SCGC5 |= ( SIM_SCGC5_PORTA_MASK
| SIM_SCGC5_PORTB_MASK
| SIM_SCGC5_PORTC_MASK
| SIM_SCGC5_PORTD_MASK
| SIM_SCGC5_PORTE_MASK);
// ----------------------------------------------------------------------------------
// Setup clocks
// ----------------------------------------------------------------------------------
// See section 5 in the Freescale K20 manual for how clock distribution works
// The limits are outlined in section 5.5:
// Core and System clocks: max 72 MHz
// Bus/peripherial clock: max 50 MHz (integer divide of core)
// Flash clock: max 25 MHz
//
// The teensy 3.x has a 16 MHz external oscillator
// So we'll enable the external clock for the OSC module. Since
// we're in high-frequency mode, also enable capacitors
OSC_CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK; // TODO This does not actually seem enable the ext crystal
// Set MCG to very high frequency crystal and request oscillator. We have
// to do this first so that the divisor will be correct (512 and not 16)
MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
// Select the external reference clock for MCGOUTCLK
// The divider for the FLL has to be chosen that we get something in 31.25 to 39.0625 kHz
// 16MHz / 512 = 31.25 kHz -> set FRDIV to 4
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(4);
// Wait for OSC to become ready
while ((MCG_S & MCG_S_OSCINIT0_MASK) == 0) ;
// Wait for the FLL to synchronize to external reference
while ((MCG_S & MCG_S_IREFST_MASK) != 0) ;
// Wait for the clock mode to synchronize to external
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) ;
// The clock is now in FBE mode
#if F_CPU <= 16000000
// For 16 MHz and below, the crystal is fast enough
// -> enable BLPE mode which will disable both FLL and PLL
MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS_MASK | MCG_C2_LP_MASK;
#else
// We need PLL to go above 16 MHz
#if F_CPU == 96000000
MCG_C5 = MCG_C5_PRDIV0(3); // 16MHz / 4 = 4MHz (this needs to be 2-4MHz)
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0); // Enable PLL*24 = 96 MHz
#elif F_CPU == 72000000
MCG_C5 = MCG_C5_PRDIV0(5); // 16 MHz / 6 = 2.66 MHz (this needs to be 2-4MHz)
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3); // Enable PLL*27 = 71.82 MHz
#elif F_CPU == 48000000
MCG_C5 = MCG_C5_PRDIV0(7); // 16 MHz / 8 = 2 MHz (this needs to be 2-4MHz)
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0); // Enable PLL*24 = 48 MHz
#elif F_CPU == 24000000
// For 24 MHz, we'll use a 48 MHz PLL and divide in the SIM
MCG_C5 = MCG_C5_PRDIV0(7); // 16 MHz / 8 = 2 MHz (this needs to be 2-4MHz)
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0); // Enable PLL*24 = 48 MHz
#else
#error "Unknown F_CPU value"
#endif
// Now that we setup and enabled the PLL, wait for it to become active
while (!(MCG_S & MCG_S_PLLST_MASK)) ;
// and locked
while (!(MCG_S & MCG_S_LOCK0_MASK)) ;
#endif
// Next up: Setup clock dividers for MCU, peripherials, flash and USB
// This is done by the SIM (System Integration Module)
// There are two registers:
// SIM_CLKDIV1:
// OUTDIV1: Core/system clock divider
// OUTDIV2: Peripherial/Bus clock
// OUTDIV4: Flash clock
// SIM_CLKDIV2:
// USBDIV: Divisor
// USBFRAC: Fraction
// Output is input_clock*(USBFRAC+1)/(USBDIV+1)
//
// USB needs a 48MHz clock, so the divider should be setup accordingly. Also,
// for the USB FS OTG controller to work, the system clock needs to be >= 20 MHz
#if F_CPU == 96000000
// 96 MHz core, 48 MHz bus, 24 MHz flash (OVERCLOCKED!)
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3);
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // 96 * 1/2 = 48
#elif F_CPU == 72000000
// 72 MHz core, 36 MHz bus, 24 MHz flash
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(2);
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK; // 72 * 2/3 = 48
#elif F_CPU == 48000000
// 48 MHz core, 48 MHz bus, 24 MHz flash, USB = 96 / 2
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) | SIM_CLKDIV1_OUTDIV4(1);
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0); // 48 * 1/1 = 48
#elif F_CPU == 24000000
// PLL is 48 MHz
// 24 MHz core, 24 MHz bus, 24 MHz flash
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(1);
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0); // 48 * 1/1 = 48
// -- For the modes <= 16 MHz, we have the MCG clock on 16 MHz, without FLL/PLL
// Also, USB is not possible
#elif F_CPU == 16000000
// 16 MHz core, 16 MHz bus, 16 MHz flash
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) | SIM_CLKDIV1_OUTDIV4(0);
#elif F_CPU == 8000000
// 8 MHz core, 8 MHz bus, 8 MHz flash
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(1);
#else
#error "Unsupported F_CPU value"
#endif
// The dividers are set, so we can transition over to PLL for > 16 MHz
#if F_CPU > 16000000
// Switch clock source to PLL, keep FLL divider at 512
MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4);
// Wait for the clock to sync
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) ;
// Use PLL for USB and Bus/peripherals, core for trace and put OSCERCLK0 on CLKOUT pin
SIM_SOPT2 = SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_TRACECLKSEL_MASK | SIM_SOPT2_CLKOUTSEL(6);
#endif
// ----------------------------------------------------------------------------------
// Relocate data from flash to RAM as necessary
// ----------------------------------------------------------------------------------
//
// At the minimum, the .data and .bss sections have to be setup in RAM. Also, since
// they are aligned to 4 bytes, we can use uint32s for copying (which is faster than
// byte by byte)
uint32_t * src = &_etext;
uint32_t * dest = &_sdata;
while (dest < &_edata) *dest++ = *src++;
// Also zero out .bss
dest = &_sbss;
while (dest < &_ebss) *dest++ = 0;
// TODO: Relocate interrupt vector to RAM for speed?
// Init systick?
#if ENABLE_SYSTICK_HANDLER
systick_init();
#endif
// Enable interrupts before entering main?
#if ENABLE_INTERRUPTS_ON_STARTUP
interrupt_enable();
#endif
// After everthing is done, call main
main();
// This should be unreachable code as long as main() does not return.
// To avoid running the instruction pointer into places it shouldn't go,
// loop forever
// TODO: Going into sleep would maybe be a better solution
while (1);
}
/*lint -esym(765,Cpu_Interrupt) Disable MISRA rule (8.10) checking for symbols (Cpu_Interrupt). */
void __init_hardware(void)
{
/*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/
/*** ### MK60DN512ZVLQ10 "Cpu" init code ... ***/
/*** PE initialization code after reset ***/
SCB_VTOR = (uint32_t)(&__vect_table); /* Set the interrupt vector table position */
/* Disable the WDOG module */
/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
/* WDOG_UNLOCK: WDOGUNLOCK=0xD928 */
WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
/* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG_STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
WDOG_STCTRLH_STNDBYEN_MASK |
WDOG_STCTRLH_WAITEN_MASK |
WDOG_STCTRLH_STOPEN_MASK |
WDOG_STCTRLH_ALLOWUPDATE_MASK |
WDOG_STCTRLH_CLKSRC_MASK;
/* System clock initialization */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x01) |
SIM_CLKDIV1_OUTDIV3(0x03) |
SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */
/* SIM_SCGC5: PORTC=1,PORTA=1 */
SIM_SCGC5 |= (SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTA_MASK); /* Enable clock gate for ports to enable pin routing */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x00) |
SIM_CLKDIV1_OUTDIV3(0x01) |
SIM_CLKDIV1_OUTDIV4(0x01); /* Update system prescalers */
/* SIM_CLKDIV2: USBDIV=0,USBFRAC=1 */
SIM_CLKDIV2 = (uint32_t)((SIM_CLKDIV2 & (uint32_t)~(uint32_t)(
SIM_CLKDIV2_USBDIV(0x07)
)) | (uint32_t)(
SIM_CLKDIV2_USBFRAC_MASK
)); /* Update USB clock prescalers */
/* SIM_SOPT2: PLLFLLSEL=0 */
SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=0 */
SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL_MASK); /* System oscillator drives 32 kHz clock for various peripherals */
/* Switch to FEI Mode */
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG_C1 = MCG_C1_CLKS(0x00) |
MCG_C1_FRDIV(0x00) |
MCG_C1_IREFS_MASK |
MCG_C1_IRCLKEN_MASK;
/* MCG_C2: ??=0,??=0,RANGE=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
MCG_C2 = MCG_C2_RANGE(0x00);
/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC_CR = OSC_CR_ERCLKEN_MASK;
/* SIM_SOPT2: MCGCLKSEL=0 */
SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_MCGCLKSEL_MASK);
/* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
MCG_C5 = MCG_C5_PRDIV(0x00);
/* MCG_C6: LOLIE=0,PLLS=0,CME=0,VDIV=0 */
MCG_C6 = MCG_C6_VDIV(0x00);
while((MCG_S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG_S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
}
/*** End of PE initialization code after reset ***/
/*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/
}
status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
{
uint8_t mcg_c4;
bool change_drs = false;
#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
mcg_mode_t mode = CLOCK_GetMode();
if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode)))
{
return kStatus_MCG_ModeUnreachable;
}
#endif
mcg_c4 = MCG->C4;
/*
Errata: ERR007993
Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
reference clock source changes, then reset to previous value after
reference clock changes.
*/
if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
{
change_drs = true;
/* Change the LSB of DRST_DRS. */
MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
}
/* Set CLKS and IREFS. */
MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
(MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
| MCG_C1_FRDIV(frdiv) /* FRDIV */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
/* If use external crystal as clock source, wait for it stable. */
{
if (MCG->C2 & MCG_C2_EREFS_MASK)
{
while (!(MCG->S & MCG_S_OSCINIT0_MASK))
{
}
}
}
/* Wait and check status. */
while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
{
}
/* Errata: ERR007993 */
if (change_drs)
{
MCG->C4 = mcg_c4;
}
/* Set DRS and DMX32. */
mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
MCG->C4 = mcg_c4;
/* Wait for DRST_DRS update. */
while (MCG->C4 != mcg_c4)
{
}
/* Check MCG_S[CLKST] */
while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
{
}
/* Wait for FLL stable time. */
if (fllStableDelay)
{
fllStableDelay();
}
return kStatus_Success;
}
/*! Sets up the clock out of RESET
*!
*/
void clock_initialise(void) {
#ifdef ENABLE_CLKOUT
showClocks();
#endif
#if (CLOCK_MODE == CLOCK_MODE_RESET)
// No clock setup
#else
// XTAL/EXTAL Pins
SIM_SCGC6 |= SIM_SCGC6_PORTB_MASK;
MXC_PTBPF1 = (MXC_PTBPF1&~MXC_PTBPF1_B6_MASK)|MXC_PTBPF1_B6(0);
MXC_PTBPF2 = (MXC_PTBPF2&~MXC_PTBPF2_B5_MASK)|MXC_PTBPF2_B5(0);
// Configure OSC2 (XTAL1/EXTAL1
OSC1_CR = OSC1_CR_ERCLKEN_M|OSC1_CR_EREFSTEN_M|OSC1_CR_SCP_M;
// Configure OSC2 (XTAL2/EXTAL2
OSC2_CR = OSC2_CR_ERCLKEN_M|OSC2_CR_EREFSTEN_M|OSC2_CR_SCP_M;
// Configure OSC1 (XTAL1/EXTAL1
SIM_OSC1 = SIM_OSC1_OSC1EN_M|SIM_OSC1_OSC1RANGE_M|SIM_OSC1_OSC1HGO_M|SIM_OSC1_OSC1EREFS_M;
// Out of reset MCG is in FEI mode
// =============================================================
// Switch from FEI -> FEI/FBI/FEE/FBE
// =============================================================
// Set up crystal or external clock source
MCG_C2 = MCG_C2_RANGE_M | // RANGE = 0,1,2 -> Oscillator low/high/very high clock range
MCG_C2_HGO_M | // HGO = 0,1 -> Oscillator low power/high gain
MCG_C2_EREFS_M | // EREFS = 0,1 -> Select external clock/crystal oscillator
MCG_C2_IRCS_M; // IRCS = 0,1 -> Select slow/fast internal clock for internal reference
SIM_CLKDIV0 = SIM_CLKDIV0_OUTDIV(3);
#if ((CLOCK_MODE == CLOCK_MODE_FEI) || (CLOCK_MODE == CLOCK_MODE_FBI) || (CLOCK_MODE == CLOCK_MODE_BLPI) )
// Transition via FBI
//=====================================
#define BYPASS (1) // CLKS value used while FLL locks
MCG_C1 = MCG_C1_CLKS(BYPASS) | // CLKS = 1 -> Internal reference source while PLL locks
MCG_C1_FRDIV_M | // FRDIV = N -> XTAL/2^n ~ 31.25 kHz
MCG_C1_IREFS_M | // IREFS = 0,1 -> External/Slow IRC for FLL source
MCG_C1_IRCLKEN_M | // IRCLKEN = 0,1 -> IRCLK disable/enable
MCG_C1_IREFSTEN_M; // IREFSTEN = 0,1 -> Internal reference enabled in STOP mode
// Wait for S_IREFST to indicate FLL Reference has switched
do {
__asm__("nop");
} while ((MCG_S & MCG_S_IREFST_MASK) != (MCG_C1_IREFS_V<<MCG_S_IREFST_SHIFT));
// Wait for S_CLKST to indicating that OUTCLK has switched to bypass PLL/FLL
do {
__asm__("nop");
} while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(BYPASS));
// Set FLL Parameters
MCG_C4 = (MCG_C4&~(MCG_C4_DMX32_MASK|MCG_C4_DRST_DRS_MASK))|MCG_C4_DMX32_M|MCG_C4_DRST_DRS_M;
#endif
#if ((CLOCK_MODE == CLOCK_MODE_FBE) || (CLOCK_MODE == CLOCK_MODE_FEE) || (CLOCK_MODE == CLOCK_MODE_PLBE) || (CLOCK_MODE == CLOCK_MODE_PBE) || (CLOCK_MODE == CLOCK_MODE_PEE))
// Transition via FBE
//=====================================
#define BYPASS (2) // CLKS value used while PLL locks
MCG_C1 = MCG_C1_CLKS(BYPASS) | // CLKS = 2 -> External reference source while PLL locks
MCG_C1_FRDIV_M | // FRDIV = N -> XTAL/2^n ~ 31.25 kHz
MCG_C1_IREFS_M | // IREFS = 0,1 -> External/Slow IRC for FLL source
MCG_C1_IRCLKEN_M | // IRCLKEN = 0,1 -> IRCLK disable/enable
MCG_C1_IREFSTEN_M; // IREFSTEN = 0,1 -> Internal reference enabled in STOP mode
#if (MCG_C2_EREFS_V != 0)
// Wait for oscillator stable (if used)
do {
__asm__("nop");
} while ((MCG_S & MCG_S_OSCINIT_MASK) == 0);
#endif
// Wait for S_IREFST to indicate FLL Reference has switched
do {
__asm__("nop");
} while ((MCG_S & MCG_S_IREFST_MASK) != (MCG_C1_IREFS_V<<MCG_S_IREFST_SHIFT));
// Wait for S_CLKST to indicating that OUTCLK has switched to bypass PLL/FLL
do {
__asm__("nop");
} while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(BYPASS));
// Set FLL Parameters
MCG_C4 = (MCG_C4&~(MCG_C4_DMX32_MASK|MCG_C4_DRST_DRS_MASK))|MCG_C4_DMX32_M|MCG_C4_DRST_DRS_M;
#endif
#if ((CLOCK_MODE == CLOCK_MODE_PBE) || (CLOCK_MODE == CLOCK_MODE_PEE))
// Configure PLL Reference Frequency
// =============================================================
MCG_C5 = MCG_C5_PLLCLKEN_M | // PLLCLKEN = 0,1 -> PLL -/enabled (irrespective of PLLS)
MCG_C5_PLLSTEN_M | // PLLSTEN0 = 0,1 -> disabled/enabled in normal stop mode
MCG_C5_PRDIV_M; // PRDIV0 = N -> PLL divider so PLL Ref. Freq. = 2-4 MHz
// Transition via PBE
// =============================================================
MCG_C6 = MCG_C6_LOLIE_M |
MCG_C6_PLLS_M | // PLLS = 0,1 -> Enable PLL
MCG_C6_CME_M | // CME0 = 0,1 -> Disable/enable clock monitor
MCG_C6_VDIV_M; // VDIV0 = N -> PLL Multiplication factor
// Wait for PLL to lock
do {
__asm__("nop");
} while((MCG_S & MCG_S_LOCK_MASK) == 0);
// Wait until PLLS clock source changes to the PLL clock out
do {
__asm__("nop");
} while((MCG_S & MCG_S_PLLST_MASK) == 0);
#endif
#if ((CLOCK_MODE == CLOCK_MODE_FEI) || (CLOCK_MODE == CLOCK_MODE_FEE))
// Wait for FLL to lock
do {
__asm__("nop");
} while ((MCG_C4&MCG_C4_DRST_DRS_MASK) != MCG_C4_DRST_DRS_M);
#endif
// Select FEI/FBI/FEE/FBE/PBE/PEE clock mode
MCG_C1 = MCG_C1_CLKS_M | // CLKS = 0,1,2 -> Select FLL/IRCSCLK/ERCLK
MCG_C1_FRDIV_M | // FRDIV = N -> XTAL/2^n ~ 31.25 kHz
MCG_C1_IREFS_M | // IREFS = 0,1 -> External/Slow IRC for FLL source
MCG_C1_IRCLKEN_M | // IRCLKEN = 0,1 -> IRCLK disable/enable
MCG_C1_IREFSTEN_M; // IREFSTEN = 0,1 -> Internal reference enabled in STOP mode
// Wait for mode change
do {
__asm__("nop");
} while ((MCG_S & MCG_S_IREFST_MASK) != (MCG_C1_IREFS_V<<MCG_S_IREFST_SHIFT));
#if defined (MCG_C6_PLLS_V) && (MCG_C1_CLKS_V == 0) // FLL or PLL
#define MCG_S_CLKST_M MCG_S_CLKST(MCG_C6_PLLS_V?3:0)
#else
#define MCG_S_CLKST_M MCG_S_CLKST(MCG_C1_CLKS_V)
#endif
// Wait for S_CLKST to indicating that OUTCLK has switched
do {
__asm__("nop");
} while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_M);
#if (CLOCK_MODE == CLOCK_MODE_BLPE) || (CLOCK_MODE == CLOCK_MODE_BLPI)
// Select BLPE/BLPI clock mode
MCG_C2 =
MCG_C2_LOCRE_M | // LOCRE0 = 0,1 -> Loss of clock reset
MCG_C2_RANGE_M | // RANGE0 = 0,1,2 -> Oscillator low/high/very high clock range
MCG_C2_HGO_M | // HGO0 = 0,1 -> Oscillator low power/high gain
MCG_C2_EREFS_M | // EREFS0 = 0,1 -> Select external clock/crystal oscillator
MCG_C2_LP_M | // LP = 0,1 -> Select FLL enabled/disabled in bypass mode
MCG_C2_IRCS_M; // IRCS = 0,1 -> Select slow/fast internal clock for internal reference
#endif // (CLOCK_MODE == CLOCK_MODE_BLPE) || (CLOCK_MODE == CLOCK_MODE_BLPI)
#endif // (CLOCK_MODE == CLOCK_MODE_RESET)
// Basic clock multiplexing
#if defined(MCU_mcf51jf128)
// SIM_SOPT2 = SIM_SOPT2_UART0SRC_M | // UART0 clock - 0,1,2,3 -> Disabled, (MCGFLLCLK, MCGPLLCLK/2), OSCERCLK, MCGIRCLK
// SIM_SOPT2_TPMSRC_M ; // TPM2 source
#else
#error "CPU not set"
#endif
#ifdef SIM_CLKDIV1_USBFRAC_MASK
SIM_CLKDIV1 = SIM_CLKDIV1_USBDIV_M | SIM_CLKDIV1_USBFRAC_M | SIM_CLKDIV1_USBSRC_M;
#endif
SIM_CLKDIV0 = SIM_CLKDIV0_M;
SystemCoreClockUpdate();
}
/*----------------------------------------------------------------------------
MAIN function
*----------------------------------------------------------------------------*/
int main (void) {
#if USE_VLPR == 1
// enter low power run
SIM->CLKDIV1 = (0x1 << SIM_CLKDIV1_OUTDIV1_SHIFT) | (0x5 << SIM_CLKDIV1_OUTDIV4_SHIFT); // reduce core clock < 4 MHz and flash < 1 MHz
MCG->C6 &= ~MCG_C6_CME0_MASK; // disable MCG clock monitor
MCG->C2 |= MCG_C2_IRCS_MASK; // don't use slow internal reference clock
MCG->C1 |= MCG_C1_CLKS(2); // enter BLPE mode
MCG->C1 &= ~MCG_C1_IREFS_MASK;
MCG->C6 &= ~MCG_C6_PLLS_MASK;
while(!(MCG->S & MCG_S_IREFST_MASK >> MCG_S_IREFST_SHIFT)); // wait to ensure clock change
MCG->C2 |= MCG_C2_LP_MASK;
#endif
Init_RGB_LEDs();
#if DEBUG_SIGNALS == 1
Init_Debug_Signals();
#endif
// I2C and MMA
i2c_init(); /* init i2c */
if (!init_mma()) { /* init mma peripheral */
Control_RGB_LEDs(1, 0, 0); /* Light red error LED */
while (1) /* not able to initialize mma */
;
}
#if RUN_I2C_FAST == 1
// increase i2c baud rate
I2C_DISABLE;
I2C0->F = (I2C_F_ICR(0x00) | I2C_F_MULT(0));
I2C_ENABLE;
#endif
// configure low power modes
SMC->PMPROT = SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK; // allow low leakage stop mode
SMC->PMCTRL = SMC_PMCTRL_RUNM(2) | SMC_PMCTRL_STOPM(3); // enable low power run mode (10) and low leakage stop mode (011)
SMC->STOPCTRL = SMC_STOPCTRL_PSTOPO(0) | SMC_STOPCTRL_VLLSM(3); // normal stop mode and VLL stop3 (not needed?)
// configure low leakage wakeup unit (LLWU)
LLWU->ME |= LLWU_ME_WUME0_MASK; // internal module 0 is wakeup source which is apparently the LPTMR
// enable stop mode (deep sleep)
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
// LPTMR
Init_LPTMR();
Start_LPTMR();
__enable_irq();
while (1) {
// read acceleration every 100 ms
if (run_Read_Accel){
run_Read_Accel = 0;
Read_Accel();
}
// update LEDs every 500 ms; keep them on for 10 ms
if (run_Update_LEDs){
run_Update_LEDs = 0;
Update_LEDs();
#if USE_PWM == 1
#if PWM_SLEEP == 1
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; // switch to regular sleep mode
#if USE_SLEEP_MODES == 1
#if DEBUG_SIGNALS == 1
PTE->PSOR |= MASK(30);
#endif
__wfi(); // PWM does not work in LLS mode
#endif
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; // switch back to LLS mode
#else
while(led_on_period); // poll -> bad solution
#endif
#endif
}
#if USE_SLEEP_MODES == 1
#if DEBUG_SIGNALS == 1
PTE->PSOR |= MASK(30);
#endif
__wfi(); // go to sleep
#endif
}
}
/*lint -esym(765,Cpu_Interrupt) Disable MISRA rule (8.10) checking for symbols (Cpu_Interrupt). */
void __init_hardware(void)
{
/*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/
/*** ### MKL46Z256VMC4 "Cpu" init code ... ***/
/*** PE initialization code after reset ***/
SCB_VTOR = (uint32_t)(&__vect_table); /* Set the interrupt vector table position */
/* Disable the WDOG module */
/* SIM_COPC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COPT=0,COPCLKS=0,COPW=0 */
SIM_COPC = SIM_COPC_COPT(0x00);
/* System clock initialization */
/* SIM_SCGC5: PORTE=1,PORTC=1,PORTB=1,PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK |
SIM_SCGC5_PORTC_MASK |
SIM_SCGC5_PORTB_MASK |
SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
/* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
/* SIM_SOPT2: PLLFLLSEL=1 */
SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=2 */
SIM_SOPT1 = (uint32_t)((SIM_SOPT1 & (uint32_t)~(uint32_t)(
SIM_SOPT1_OSC32KSEL(0x01)
)) | (uint32_t)(
SIM_SOPT1_OSC32KSEL(0x02)
)); /* System oscillator drives 32 kHz clock for various peripherals */
/* SIM_SOPT2: TPMSRC=1 */
SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)(
SIM_SOPT2_TPMSRC(0x02)
)) | (uint32_t)(
SIM_SOPT2_TPMSRC(0x01)
)); /* Set the TPM clock */
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* PORTA_PCR19: ISF=0,MUX=0 */
PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* Switch to FBE Mode */
/* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
MCG_C2 = (uint8_t)((MCG_C2 & (uint8_t)~(uint8_t)(
MCG_C2_LOCRE0_MASK |
MCG_C2_RANGE0(0x01) |
MCG_C2_HGO0_MASK |
MCG_C2_LP_MASK |
MCG_C2_IRCS_MASK
)) | (uint8_t)(
MCG_C2_RANGE0(0x02) |
MCG_C2_EREFS0_MASK
));
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0_CR = OSC_CR_ERCLKEN_MASK;
/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK);
/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
MCG_C5 = MCG_C5_PRDIV0(0x03);
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG_C6 = MCG_C6_VDIV0(0x00);
while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to PBE Mode */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x00));
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
}
/* Switch to PEE Mode */
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK);
while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
}
/* Initialization of the RTC_CLKIN pin */
/* PORTC_PCR1: ISF=0,MUX=1 */
PORTC_PCR1 = (uint32_t)((PORTC_PCR1 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x06)
)) | (uint32_t)(
PORT_PCR_MUX(0x01)
));
/*** End of PE initialization code after reset ***/
/*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/
}
void ResetHandler(void)
{
uint32_t *src = &_etext;
uint32_t *dest = &_sdata;
WDOG_UNLOCK = WDOG_UNLOCK_SEQ1;
WDOG_UNLOCK = WDOG_UNLOCK_SEQ2;
WDOG_STCTRLH = WDOG_STCTRLH_ALLOWUPDATE;
startup_early_hook();
// enable clocks to always-used peripherals
SIM_SCGC5 = 0x00043F82; // clocks active to all GPIO
SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;
// if the RTC oscillator isn't enabled, get it started early
if (!(RTC_CR & RTC_CR_OSCE)) {
RTC_SR = 0;
RTC_CR = RTC_CR_SC16P | RTC_CR_SC4P | RTC_CR_OSCE;
}
// TODO: do this while the PLL is waiting to lock....
while (dest < &_edata) *dest++ = *src++;
dest = &_sbss;
while (dest < &_ebss) *dest++ = 0;
SCB_VTOR = 0; // use vector table in flash
// start in FEI mode
// enable capacitors for crystal
OSC0_CR = OSC_SC8P | OSC_SC2P;
// enable osc, 8-32 MHz range, low power mode
MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS;
// switch to crystal as clock source, FLL input = 16 MHz / 512
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(4);
// wait for crystal oscillator to begin
while ((MCG_S & MCG_S_OSCINIT0) == 0) ;
// wait for FLL to use oscillator
while ((MCG_S & MCG_S_IREFST) != 0) ;
// wait for MCGOUT to use oscillator
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) ;
// now we're in FBE mode
// config PLL input for 16 MHz Crystal / 4 = 4 MHz
MCG_C5 = MCG_C5_PRDIV0(3);
// config PLL for 96 MHz output
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
// wait for PLL to start using xtal as its input
while (!(MCG_S & MCG_S_PLLST)) ;
// wait for PLL to lock
while (!(MCG_S & MCG_S_LOCK0)) ;
// now we're in PBE mode
#if F_CPU == 96000000
// config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3);
#elif F_CPU == 48000000
// config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3);
#elif F_CPU == 24000000
// config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(3);
#else
#error "Error, F_CPU must be 96000000, 48000000, or 24000000"
#endif
// switch to PLL as clock source, FLL input = 16 MHz / 512
MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4);
// wait for PLL clock to be used
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) ;
// now we're in PEE mode
// configure USB for 48 MHz clock
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // USB = 96 MHz PLL / 2
// USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0
SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6);
// initialize the SysTick counter
SYST_RVR = (F_CPU / 1000) - 1;
SYST_CSR = SYST_CSR_CLKSOURCE | SYST_CSR_TICKINT | SYST_CSR_ENABLE;
//init_pins();
__enable_irq();
_init_Teensyduino_internal_();
if (RTC_SR & RTC_SR_TIF) rtc_set(TIME_T);
__libc_init_array();
/*
for (ptr = &__init_array_start; ptr < &__init_array_end; ptr++) {
(*ptr)();
}
*/
startup_late_hook();
main();
while (1) ;
}
void ResetHandler(void)
{
/*
* Enable watchdog timer. Allow settings to be changed later, in case the
* application firmware wants to adjust its settings or disable it.
*
* Originally I tried using the 1 kHz low-power oscillator here, but that seemed to
* run into an issue where refreshes weren't taking effect. It seems similar to
* this problem on the Freescale forums, which didn't really have a satisfactory
* solution:
*
* https://community.freescale.com/thread/309519
*
* As a workaround, I'm using the "alternate" system clock.
*/
{
const uint32_t watchdog_timeout = F_BUS / 100; // 10ms
WDOG_UNLOCK = WDOG_UNLOCK_SEQ1;
WDOG_UNLOCK = WDOG_UNLOCK_SEQ2;
asm volatile ("nop");
asm volatile ("nop");
WDOG_STCTRLH = WDOG_STCTRLH_ALLOWUPDATE | WDOG_STCTRLH_WDOGEN |
WDOG_STCTRLH_WAITEN | WDOG_STCTRLH_STOPEN | WDOG_STCTRLH_CLKSRC;
WDOG_PRESC = 0;
WDOG_TOVALH = watchdog_timeout >> 16;
WDOG_TOVALL = watchdog_timeout;
}
// enable clocks to always-used peripherals
SIM_SCGC5 = 0x00043F82; // clocks active to all GPIO
SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;
// release I/O pins hold, if we woke up from VLLS mode
if (PMC_REGSC & PMC_REGSC_ACKISO) PMC_REGSC |= PMC_REGSC_ACKISO;
// start in FEI mode
// enable capacitors for crystal
OSC0_CR = OSC_SC8P | OSC_SC2P;
// enable osc, 8-32 MHz range, low power mode
MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS;
// switch to crystal as clock source, FLL input = 16 MHz / 512
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(4);
// wait for crystal oscillator to begin
while ((MCG_S & MCG_S_OSCINIT0) == 0) ;
// wait for FLL to use oscillator
while ((MCG_S & MCG_S_IREFST) != 0) ;
// wait for MCGOUT to use oscillator
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) ;
// now we're in FBE mode
// config PLL input for 16 MHz Crystal / 4 = 4 MHz
MCG_C5 = MCG_C5_PRDIV0(3);
// config PLL for 96 MHz output
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
// Copy things while we're waiting on the PLL
{
// Relocate data and text to RAM
uint32_t *src = &_eflash;
uint32_t *dest = &_sdtext;
while (dest < &_edtext) *dest++ = *src++;
// Clear BSS
dest = &_sbss;
while (dest < &_ebss) *dest++ = 0;
// Copy IVT to RAM
src = (uint32_t*) &gVectors[0];
dest = &ramVectors[0];
while (dest <= &ramVectors[63]) *dest++ = *src++;
// Switch to ram IVT
SCB_VTOR = (uint32_t) &ramVectors[0];
}
// wait for PLL to start using xtal as its input
while (!(MCG_S & MCG_S_PLLST)) ;
// wait for PLL to lock
while (!(MCG_S & MCG_S_LOCK0)) ;
// now we're in PBE mode
// config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3);
// switch to PLL as clock source, FLL input = 16 MHz / 512
MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4);
// wait for PLL clock to be used
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) ;
// now we're in PEE mode
// configure USB for 48 MHz clock
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // USB = 96 MHz PLL / 2
// USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0
SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6);
__enable_irq();
main();
}
/*! Sets up the clock out of RESET
*!
*/
void clock_initialise(void) {
#if (CLOCK_MODE == CLOCK_MODE_RESET)
// No clock setup
#else
// XTAL/EXTAL Pins
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
PORTA_PCR3 = PORT_PCR_MUX(0);
PORTA_PCR4 = PORT_PCR_MUX(0);
// Configure the Crystal Oscillator
OSC0_CR = OSC_CR_ERCLKEN_M|OSC_CR_EREFSTEN_M|OSC_CR_SCP_M;
// Fast Internal Clock divider
MCG_SC = MCG_SC_FCRDIV_M;
// Out of reset MCG is in FEI mode
// =============================================================
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(7) | SIM_CLKDIV1_OUTDIV3(3) | SIM_CLKDIV1_OUTDIV4(7);
// Switch from FEI -> FEI/FBI/FEE/FBE
// =============================================================
// Set up crystal or external clock source
MCG_C2 =
MCG_C2_LOCRE0_M | // LOCRE0 = 0,1 -> Loss of clock reset
MCG_C2_RANGE0_M | // RANGE0 = 0,1,2 -> Oscillator low/high/very high clock range
MCG_C2_HGO0_M | // HGO0 = 0,1 -> Oscillator low power/high gain
MCG_C2_EREFS0_M | // EREFS0 = 0,1 -> Select external clock/crystal oscillator
MCG_C2_IRCS_M; // IRCS = 0,1 -> Select slow/fast internal clock for internal reference
#if ((CLOCK_MODE == CLOCK_MODE_FEI) || (CLOCK_MODE == CLOCK_MODE_FBI) || (CLOCK_MODE == CLOCK_MODE_BLPI) )
// Transition via FBI
//=====================================
#define BYPASS (1) // CLKS value used while FLL locks
MCG_C1 = MCG_C1_CLKS(BYPASS) | // CLKS = 2 -> External reference source while PLL locks
MCG_C1_FRDIV_M | // FRDIV = N -> XTAL/2^n ~ 31.25 kHz
MCG_C1_IREFS_M | // IREFS = 0,1 -> External/Slow IRC for FLL source
MCG_C1_IRCLKEN_M | // IRCLKEN = 0,1 -> IRCLK disable/enable
MCG_C1_IREFSTEN_M; // IREFSTEN = 0,1 -> Internal reference enabled in STOP mode
// Wait for S_IREFST to indicate FLL Reference has switched
do {
__asm__("nop");
} while ((MCG_S & MCG_S_IREFST_MASK) != (MCG_C1_IREFS_V<<MCG_S_IREFST_SHIFT));
// Wait for S_CLKST to indicating that OUTCLK has switched to bypass PLL/FLL
do {
__asm__("nop");
} while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(BYPASS));
// Set FLL Parameters
MCG_C4 = (MCG_C4&~(MCG_C4_DMX32_MASK|MCG_C4_DRST_DRS_MASK))|MCG_C4_DMX32_M|MCG_C4_DRST_DRS_M;
#endif
#if ((CLOCK_MODE == CLOCK_MODE_FBE) || (CLOCK_MODE == CLOCK_MODE_FEE) || (CLOCK_MODE == CLOCK_MODE_PLBE) || (CLOCK_MODE == CLOCK_MODE_PBE) || (CLOCK_MODE == CLOCK_MODE_PEE))
// Transition via FBE
//=====================================
#define BYPASS (2) // CLKS value used while PLL locks
MCG_C1 = MCG_C1_CLKS(BYPASS) | // CLKS = 2 -> External reference source while PLL locks
MCG_C1_FRDIV_M | // FRDIV = N -> XTAL/2^n ~ 31.25 kHz
MCG_C1_IREFS_M | // IREFS = 0,1 -> External/Slow IRC for FLL source
MCG_C1_IRCLKEN_M | // IRCLKEN = 0,1 -> IRCLK disable/enable
MCG_C1_IREFSTEN_M; // IREFSTEN = 0,1 -> Internal reference enabled in STOP mode
#if (MCG_C2_EREFS_V != 0)
// Wait for oscillator stable (if used)
do {
__asm__("nop");
} while ((MCG_S & MCG_S_OSCINIT0_MASK) == 0);
#endif
// Wait for S_IREFST to indicate FLL Reference has switched
do {
__asm__("nop");
} while ((MCG_S & MCG_S_IREFST_MASK) != (MCG_C1_IREFS_V<<MCG_S_IREFST_SHIFT));
// Wait for S_CLKST to indicating that OUTCLK has switched to bypass PLL/FLL
do {
__asm__("nop");
} while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(BYPASS));
// Set FLL Parameters
MCG_C4 = (MCG_C4&~(MCG_C4_DMX32_MASK|MCG_C4_DRST_DRS_MASK))|MCG_C4_DMX32_M|MCG_C4_DRST_DRS_M;
#endif
// Select FEI/FBI/FEE/FBE clock mode
MCG_C1 = MCG_C1_CLKS_M | // CLKS = 0,1,2 -> Select FLL/IRCSCLK/ERCLK
MCG_C1_FRDIV_M | // FRDIV = N -> XTAL/2^n ~ 31.25 kHz
MCG_C1_IREFS_M | // IREFS = 0,1 -> External/Slow IRC for FLL source
MCG_C1_IRCLKEN_M | // IRCLKEN = 0,1 -> IRCLK disable/enable
MCG_C1_IREFSTEN_M; // IREFSTEN = 0,1 -> Internal reference enabled in STOP mode
// Wait for mode change
do {
__asm__("nop");
} while ((MCG_S & MCG_S_IREFST_MASK) != (MCG_C1_IREFS_V<<MCG_S_IREFST_SHIFT));
#if defined (MCG_C6_PLLS_V) && (MCG_C1_CLKS_V == 0) // FLL or PLL
#define MCG_S_CLKST_M MCG_S_CLKST(MCG_C6_PLLS_V?3:0)
#else
#define MCG_S_CLKST_M MCG_S_CLKST(MCG_C1_CLKS_V)
#endif
// Wait for S_CLKST to indicating that OUTCLK has switched
do {
__asm__("nop");
} while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_M);
// Set the SIM _CLKDIV dividers
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1_M | SIM_CLKDIV1_OUTDIV2_M | SIM_CLKDIV1_OUTDIV3_M | SIM_CLKDIV1_OUTDIV4_M;
#if (CLOCK_MODE == CLOCK_MODE_BLPE) || (CLOCK_MODE == CLOCK_MODE_BLPI)
// Select BLPE/BLPI clock mode
MCG_C2 =
MCG_C2_LOCRE0_M | // LOCRE0 = 0,1 -> Loss of clock reset
MCG_C2_RANGE0_M | // RANGE0 = 0,1,2 -> Oscillator low/high/very high clock range
MCG_C2_HGO0_M | // HGO0 = 0,1 -> Oscillator low power/high gain
MCG_C2_EREFS0_M | // EREFS0 = 0,1 -> Select external clock/crystal oscillator
MCG_C2_LP_M | // LP = 0,1 -> Select FLL enabled/disabled in bypass mode
MCG_C2_IRCS_M; // IRCS = 0,1 -> Select slow/fast internal clock for internal reference
#endif // (CLOCK_MODE == CLOCK_MODE_BLPE) || (CLOCK_MODE == CLOCK_MODE_BLPI)
#endif // (CLOCK_MODE == CLOCK_MODE_RESET)
// Basic clock multiplexing
#if defined(MCU_MK20D5) || defined(MCU_MK20D7) || defined(MCU_MK40D10) || defined(MCU_MK40DZ10)
// Peripheral clock choice (incl. USB), USBCLK = MCGCLK
SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_M | // PLL rather than FLL for peripheral clock
SIM_SOPT2_USBSRC_MASK; // MCGPLLCLK/2 Source as USB clock (48MHz req.)
SIM_SOPT1 = (SIM_SOPT1&~SIM_SOPT1_OSC32KSEL_MASK)|SIM_SOPT1_OSC32KSEL_M; // ERCLK32K source
#elif defined(MCU_MK60D10) || defined(MCU_MK60DZ10)
// Peripheral clock choice (incl. USB), USBCLK = MCGCLK
SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK | // PLL rather than FLL for peripheral clock
SIM_SOPT2_USBSRC_MASK; // MCGPLLCLK/2 Source as USB clock (48MHz req.)
#elif defined(MCU_MKL24Z4) || defined(MCU_MKL25Z4) || defined(MCU_MKL26Z4) || defined(MCU_MKL46Z4)
SIM_SOPT2 = SIM_SOPT2_UART0SRC_M | // UART0 clock - 0,1,2,3 -> Disabled, (MCGFLLCLK, MCGPLLCLK/2), OSCERCLK, MCGIRCLK
SIM_SOPT2_TPMSRC_M | // TPM clock - 0,1,2,3 -> Disabled, (MCGFLLCLK, MCGPLLCLK/2), OSCERCLK, MCGIRCLK
SIM_SOPT2_PLLFLLSEL_M | // Peripheral clock - 0,1 -> MCGFLLCLK,MCGPLLCLK/2
SIM_SOPT2_USBSRC_MASK; // MCGPLLCLK/2 Source as USB clock (48MHz req.)
SIM_SOPT1 = (SIM_SOPT1&~SIM_SOPT1_OSC32KSEL_MASK)|SIM_SOPT1_OSC32KSEL_M; // ERCLK32K clock - 0,1,2,3 -> OSC32KCLK, - , RTC_CLKIN, LPO (1kHz)
#elif defined(MCU_MKL14Z4) || defined(MCU_MKL15Z4) || defined(MCU_MKL16Z4) || defined(MCU_MKL34Z4) || defined(MCU_MKL36Z4)
SIM_SOPT2 = SIM_SOPT2_UART0SRC_M | // UART0 clock - 0,1,2,3 -> Disabled, (MCGFLLCLK, MCGPLLCLK/2), OSCERCLK, MCGIRCLK
SIM_SOPT2_TPMSRC_M | // TPM clock - 0,1,2,3 -> Disabled, (MCGFLLCLK, MCGPLLCLK/2), OSCERCLK, MCGIRCLK
SIM_SOPT2_PLLFLLSEL_M; // Peripheral clock - 0,1 -> MCGFLLCLK,MCGPLLCLK/2
SIM_SOPT1 = (SIM_SOPT1&~SIM_SOPT1_OSC32KSEL_MASK)|SIM_SOPT1_OSC32KSEL_M; // ERCLK32K clock - 0,1,2,3 -> OSC32KCLK, - , RTC_CLKIN, LPO (1kHz)
#elif defined(MCU_MKL02Z4) || defined(MCU_MKL04Z4) || defined(MCU_MKL05Z4)
SIM_SOPT2 = SIM_SOPT2_UART0SRC_M | // UART0 clock - 0,1,2,3 -> Disabled, (MCGFLLCLK, MCGPLLCLK/2), OSCERCLK, MCGIRCLK
SIM_SOPT2_TPMSRC_M ; // TPM2 source
#else
#error "CPU not set"
#endif
SystemCoreClockUpdate();
}
void __pe_initialize_hardware(void)
{
/*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/
/*** ### MK21FN1M0VMC12 "Cpu" init code ... ***/
/*** PE initialization code after reset ***/
/* Disable the WDOG module */
/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
/* WDOG_UNLOCK: WDOGUNLOCK=0xD928 */
WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
/* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG_STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
WDOG_STCTRLH_WAITEN_MASK |
WDOG_STCTRLH_STOPEN_MASK |
WDOG_STCTRLH_ALLOWUPDATE_MASK |
WDOG_STCTRLH_CLKSRC_MASK |
0x0100U;
#if MQX_ENABLE_LOW_POWER
/* Reset from LLWU wake up source */
if (_lpm_get_reset_source() == MQX_RESET_SOURCE_LLWU)
{
PMC_REGSC |= PMC_REGSC_ACKISO_MASK;
}
#endif
/* SIM_SCGC6: RTC=1 */
SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
if ((RTC_CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */
/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
RTC_CR &= (uint32_t)~(uint32_t)(
RTC_CR_SC2P_MASK |
RTC_CR_SC4P_MASK |
RTC_CR_SC8P_MASK |
RTC_CR_SC16P_MASK
);
/* RTC_CR: OSCE=1 */
RTC_CR |= RTC_CR_OSCE_MASK;
/* RTC_CR: CLKO=0 */
RTC_CR &= (uint32_t)~(uint32_t)(RTC_CR_CLKO_MASK);
}
/* System clock initialization */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x01) |
SIM_CLKDIV1_OUTDIV3(0x03) |
SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */
/* SIM_SCGC5: PORTD=1,PORTC=1,PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK |
SIM_SCGC5_PORTC_MASK |
SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=2,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x01) |
SIM_CLKDIV1_OUTDIV3(0x02) |
SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */
/* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */
SIM_CLKDIV2 = (uint32_t)0x09UL; /* Update USB clock prescalers */
/* SIM_SOPT2: PLLFLLSEL=1 */
SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=0 */
SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* PORTA_PCR19: ISF=0,MUX=0 */
PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* Switch to FBE Mode */
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK);
/* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=1,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC_CR = (OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK);
/* MCG_C7: OSCSEL=0 */
MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03));
/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
MCG_C5 = MCG_C5_PRDIV0(0x01);
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=6 */
MCG_C6 = MCG_C6_VDIV0(0x06);
while((MCG_S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
}
while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to PBE Mode */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x06));
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
}
/* Switch to PEE Mode */
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03));
while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
}
/*** End of PE initialization code after reset ***/
/*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/
}
/*
* LPLD_PLL_Setup
* 初始化内核时钟及其他系统时钟
*
* 参数:
* core_clk_mhz--期望内核时钟频率
* |__PLLx--参见HAL_MCG.h中的PLL_option定义
*
* 输出:
* 内核频率，单位MHz
*/
uint8 LPLD_PLL_Setup(PllOptionEnum_Type core_clk_mhz)
{
uint8 pll_freq;
uint8 prdiv, vdiv;
uint8 core_div, bus_div, flexbus_div, flash_div;
/*
*************************************************
【LPLD注解】MCG关键系数
prdiv(PLL分频系数): 0~31(1~32)
vdiv(PLL倍频系数): 0~31(24~55)
PLL参考时钟范围: 2MHz~4MHz
PLL参考时钟 = 外部参考时钟(CPU_XTAL_CLK_HZ)/prdiv
CoreClk = PLL参考时钟 x PLL倍频系数 /OUTDIV1
*************************************************
*/
// 对于MK60DZ10来说，core_clk_mhz建议不要超过100，这里限制为最高200
core_clk_mhz = (PllOptionEnum_Type)(core_clk_mhz>200u?200u:core_clk_mhz);
// 根据期望主频选择分频和倍频系数
switch(core_clk_mhz)
{
case PLL_48:
prdiv = 24u;
vdiv = 0u;
break;
case PLL_50:
prdiv = 24u;
vdiv = 1u;
break;
case PLL_96:
prdiv = 24u;
vdiv = 24u;
break;
case PLL_100:
prdiv = 24u;
vdiv = 26u;
break;
case PLL_120:
prdiv = 19u;
vdiv = 24u;
break;
case PLL_150:
prdiv = 15u;
vdiv = 24u;
break;
case PLL_180:
prdiv = 14u;
vdiv = 30u;
break;
case PLL_200:
prdiv = 12u;
vdiv = 28u;
break;
default:
return LPLD_PLL_Setup(PLL_96);
}
pll_freq = core_clk_mhz * 1;
core_div = 0;
if((bus_div = (uint8)(core_clk_mhz/BUS_CLK_MHZ - 1u)) == (uint8)-1)
{
bus_div = 0;
}
else if(core_clk_mhz/(bus_div+1) > BUS_CLK_MHZ)
{
bus_div += 1;
}
if((flexbus_div = (core_clk_mhz/FLEXBUS_CLK_MHZ - 1u)) == (uint8)-1)
{
flexbus_div = 0;
}
else if(core_clk_mhz/(flexbus_div+1) > FLEXBUS_CLK_MHZ)
{
flexbus_div += 1;
}
if((flash_div = (core_clk_mhz/FLASH_CLK_MHZ - 1u)) == (uint8)-1)
{
flash_div = 0;
}
else if(core_clk_mhz/(flash_div+1) > FLASH_CLK_MHZ)
{
flash_div += 1;
}
// 这里假设复位后 MCG 模块默认为 FEI 模式
// 首先移动到 FBE 模式
MCG->C2 = 0;
// 振荡器初始化完成后,释放锁存状态下的 oscillator 和 GPIO
SIM->SCGC4 |= SIM_SCGC4_LLWU_MASK;
LLWU->CS |= LLWU_CS_ACKISO_MASK;
// 选择外部 oscilator 、参考分频器 and 清零 IREFS 启动外部osc
// CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
while (MCG->S & MCG_S_IREFST_MASK){}; // 等待参考时钟清零
while (((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}; // 等待时钟状态显示为外部参考时钟(ext ref clk)
// 进入FBE模式
// 配置 PLL 参考分频器, PLLCLKEN=0, PLLSTEN=0, PRDIV=5
// 用晶振频率来选择 PRDIV 值. 仅在有频率晶振的时候支持
// 产生 2MHz 的参考时钟给 PLL.
MCG->C5 = MCG_C5_PRDIV(prdiv); // 设置 PLL 匹配晶振的参考分频数
// 确保MCG_C6处于复位状态,禁止LOLIE、PLL、和时钟控制器,清PLL VCO分频器
MCG->C6 = 0x0;
//设置系统时钟分频系数
LPLD_Set_SYS_DIV(core_div, bus_div, flexbus_div, flash_div);
//设置倍频系数
MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(vdiv);
while (!(MCG->S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG->S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
// 已经进入PBE模式
// Transition into PEE by setting CLKS to 0
// CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
MCG->C1 &= ~MCG_C1_CLKS_MASK;
// Wait for clock status bits to update
while (((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};
// 已经进入PEE模式
return pll_freq;
}
/**
* @brief KL2x clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function should be invoked just after the system reset.
*
* @special
*/
void kl2x_clock_init(void) {
#if !KINETIS_NO_INIT
/* Disable COP watchdog */
SIM->COPC = 0;
/* Enable PORTA */
SIM->SCGC5 |= SIM_SCGC5_PORTA;
/* --- MCG mode: FEI (default out of reset) ---
f_MCGOUTCLK = f_int * F
F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits.
Typical f_MCGOUTCLK = 21 MHz immediately after reset.
C4[DMX32]=0 and C4[DRST_DRS]=00 => FLL factor=640.
C3[SCTRIM] and C4[SCFTRIM] factory trim values apply to f_int. */
/* System oscillator drives 32 kHz clock (OSC32KSEL=0) */
SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
/* This is the default mode at reset. */
/* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
* OUTDIV1 (divider for core/system and bus/flash clock)
* OUTDIV4 (additional divider for bus/flash clock) */
SIM->CLKDIV1 =
SIM_CLKDIV1_OUTDIV1(1) | /* OUTDIV1 = divide-by-2 => 24 MHz */
SIM_CLKDIV1_OUTDIV4(0); /* OUTDIV4 = divide-by-1 => 24 MHz */
#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEE
/*
* FLL Enabled External (FEE) MCG Mode
* 24 MHz core, 12 MHz bus - using 32.768 kHz crystal with FLL.
* f_MCGOUTCLK = (f_ext / FLL_R) * F
* = (32.768 kHz ) *
* FLL_R is the reference divider selected by C1[FRDIV]
* F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32].
*
* Then the core/system and bus/flash clocks are divided:
* f_SYS = f_MCGOUTCLK / OUTDIV1 = 48 MHz / 1 = 48 MHz
* f_BUS = f_MCGOUTCLK / OUTDIV1 / OUTDIV4 = MHz / 4 = 24 MHz
*/
SIM->SOPT2 =
SIM_SOPT2_TPMSRC(1); /* MCGFLLCLK clock or MCGPLLCLK/2 */
/* PLLFLLSEL=0 -> MCGFLLCLK */
/* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
* OUTDIV1 (divider for core/system and bus/flash clock)
* OUTDIV4 (additional divider for bus/flash clock) */
SIM->CLKDIV1 =
SIM_CLKDIV1_OUTDIV1(KINETIS_MCG_FLL_OUTDIV1 - 1) |
SIM_CLKDIV1_OUTDIV4(KINETIS_MCG_FLL_OUTDIV4 - 1);
/* EXTAL0 and XTAL0 */
PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
OSC0->CR = 0;
/* From KL25P80M48SF0RM section 24.5.1.1 "Initializing the MCG". */
/* To change from FEI mode to FEE mode: */
/* (1) Select the external clock source in C2 register.
Use low-power OSC mode (HGO0=0) which enables internal feedback
resistor, for 32.768 kHz crystal configuration. */
MCG->C2 =
MCG_C2_RANGE0(0) | /* low frequency range (<= 40 kHz) */
MCG_C2_EREFS0; /* external reference (using a crystal) */
/* (2) Write to C1 to select the clock mode. */
MCG->C1 = /* Clear the IREFS bit to switch to the external reference. */
MCG_C1_CLKS_FLLPLL | /* Use FLL for system clock, MCGCLKOUT. */
MCG_C1_FRDIV(0); /* Don't divide 32kHz ERCLK FLL reference. */
MCG->C6 = 0; /* PLLS=0: Select FLL as MCG source, not PLL */
/* Loop until S[OSCINIT0] is 1, indicating the
crystal selected by C2[EREFS0] has been initialized. */
while ((MCG->S & MCG_S_OSCINIT0) == 0)
;
/* Loop until S[IREFST] is 0, indicating the
external reference is the current reference clock source. */
while ((MCG->S & MCG_S_IREFST) != 0)
; /* Wait until external reference clock is FLL reference. */
/* (1)(e) Loop until S[CLKST] indicates FLL feeds MCGOUTCLK. */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_FLL)
; /* Wait until FLL has been selected. */
/* --- MCG mode: FEE --- */
/* Set frequency range for DCO output (MCGFLLCLK). */
MCG->C4 = (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0) |
MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS);
/* Wait for the FLL lock time; t[fll_acquire][max] = 1 ms */
/* TODO - not implemented - is it required? Freescale example code
seems to omit it. */
#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
/*
* PLL Enabled External (PEE) MCG Mode
* 48 MHz core, 24 MHz bus - using 8 MHz crystal with PLL.
* f_MCGOUTCLK = (OSCCLK / PLL_R) * M
* = 8 MHz / 2 * 24 = 96 MHz
* PLL_R is the reference divider selected by C5[PRDIV0]
* M is the multiplier selected by C6[VDIV0]
*
* Then the core/system and bus/flash clocks are divided:
* f_SYS = f_MCGOUTCLK / OUTDIV1 = 96 MHz / 2 = 48 MHz
* f_BUS = f_MCGOUTCLK / OUTDIV1 / OUTDIV4 = 96 MHz / 4 = 24 MHz
*/
/* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
* OUTDIV1 (divider for core/system and bus/flash clock)
* OUTDIV4 (additional divider for bus/flash clock) */
SIM->CLKDIV1 =
SIM_CLKDIV1_OUTDIV1(1) | /* OUTDIV1 = divide-by-2 => 48 MHz */
SIM_CLKDIV1_OUTDIV4(1); /* OUTDIV4 = divide-by-2 => 24 MHz */
SIM->SOPT2 =
SIM_SOPT2_TPMSRC(1) | /* MCGFLLCLK clock or MCGPLLCLK/2 */
SIM_SOPT2_PLLFLLSEL; /* PLLFLLSEL=MCGPLLCLK/2 */
/* EXTAL0 and XTAL0 */
PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
OSC0->CR = 0;
/* From KL25P80M48SF0RM section 24.5.1.1 "Initializing the MCG". */
/* To change from FEI mode to FBE mode: */
/* (1) Select the external clock source in C2 register.
Use low-power OSC mode (HGO0=0) which enables internal feedback
resistor since FRDM-KL25Z has feedback resistor R25 unpopulated.
Use high-gain mode by setting C2[HGO0] instead if external
feedback resistor Rf is installed. */
MCG->C2 =
MCG_C2_RANGE0(2) | /* very high frequency range */
MCG_C2_EREFS0; /* external reference (using a crystal) */
/* (2) Write to C1 to select the clock mode. */
MCG->C1 = /* Clear the IREFS bit to switch to the external reference. */
MCG_C1_CLKS_ERCLK | /* Use ERCLK for system clock, MCGCLKOUT. */
MCG_C1_FRDIV(3); /* Divide ERCLK / 256 for FLL reference. */
/* Note: FLL reference frequency must be 31.25 kHz to 39.0625 kHz.
8 MHz / 256 = 31.25 kHz. */
MCG->C4 &= ~(MCG_C4_DMX32 | MCG_C4_DRST_DRS_MASK);
MCG->C6 = 0; /* PLLS=0: Select FLL as MCG source, not PLL */
/* (3) Once configuration is set, wait for MCG mode change. */
/* From KL25P80M48SF0RM section 24.5.31: */
/* (1)(c) Loop until S[OSCINIT0] is 1, indicating the
crystal selected by C2[EREFS0] has been initialized. */
while ((MCG->S & MCG_S_OSCINIT0) == 0)
;
/* (1)(d) Loop until S[IREFST] is 0, indicating the
external reference is the current reference clock source. */
while ((MCG->S & MCG_S_IREFST) != 0)
; /* Wait until external reference clock is FLL reference. */
/* (1)(e) Loop until S[CLKST] is 2'b10, indicating
the external reference clock is selected to feed MCGOUTCLK. */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_ERCLK)
; /* Wait until external reference clock has been selected. */
/* --- MCG mode: FBE (FLL bypassed, external crystal) ---
Now the MCG is in FBE mode.
Although the FLL is bypassed, it is still on. */
/* (2) Then configure C5[PRDIV0] to generate the
correct PLL reference frequency. */
MCG->C5 = MCG_C5_PRDIV0(1); /* PLL External Reference Divide by 2 */
/* (3) Then from FBE transition to PBE mode. */
/* (3)(b) C6[PLLS]=1 to select PLL. */
/* (3)(b) C6[VDIV0]=5'b0000 (x24) 2 MHz * 24 = 48 MHz. */
MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
/* (3)(d) Loop until S[PLLST], indicating PLL
is the PLLS clock source. */
while ((MCG->S & MCG_S_PLLST) == 0)
; /* wait until PLL is the PLLS clock source. */
/* (3)(e) Loop until S[LOCK0] is set, indicating the PLL has acquired lock. */
/* PLL selected as MCG source. VDIV0=00000 (Multiply=24). */
while ((MCG->S & MCG_S_LOCK0) == 0)
; /* wait until PLL locked */
/* --- MCG mode: PBE (PLL bypassed, external crystal) --- */
/* (4) Transition from PBE mode to PEE mode. */
/* (4)(a) C1[CLKS] = 2'b00 to select PLL output as system clock source. */
// Switch to PEE mode
// Select PLL output (CLKS=0)
// FLL external reference divider (FRDIV=3)
// External reference clock for FLL (IREFS=0)
MCG->C1 = MCG_C1_CLKS(0) |
MCG_C1_FRDIV(3);
/* (4)(b) Loop until S[CLKST] are 2'b11, indicating the PLL output is selected for MCGOUTCLK. */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL)
; /* wait until clock switched to PLL output */
/* --- MCG mode: PEE (PLL enabled, external crystal) --- */
#else /* KINETIS_MCG_MODE != KINETIS_MCG_MODE_PEE */
#error Unimplemented KINETIS_MCG_MODE
#endif /* KINETIS_MCG_MODE != KINETIS_MCG_MODE_PEE */
#endif /* !KINETIS_NO_INIT */
}
status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
{
uint8_t mcg_c4;
bool change_drs = false;
#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
mcg_mode_t mode = CLOCK_GetMode();
if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
(kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
{
return kStatus_MCG_ModeUnreachable;
}
#endif
/* Change to FLL mode. */
MCG->C6 &= ~MCG_C6_PLLS_MASK;
while (MCG->S & MCG_S_PLLST_MASK)
{
}
/* Set LP bit to enable the FLL */
MCG->C2 &= ~MCG_C2_LP_MASK;
mcg_c4 = MCG->C4;
/*
Errata: ERR007993
Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
reference clock source changes, then reset to previous value after
reference clock changes.
*/
if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
{
change_drs = true;
/* Change the LSB of DRST_DRS. */
MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
}
/* Set CLKS and IREFS. */
MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
(MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
| MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
/* Wait for Reference clock Status bit to clear */
while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
{
}
/* Errata: ERR007993 */
if (change_drs)
{
MCG->C4 = mcg_c4;
}
/* Set DRST_DRS and DMX32. */
mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
/* Wait for clock status bits to show clock source is ext ref clk */
while (kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
{
}
/* Wait for fll stable time. */
if (fllStableDelay)
{
fllStableDelay();
}
return kStatus_Success;
}
/*! @brief Sets up the clock out of RESET
*
*/
void clock_initialise(void) {
#if (CLOCK_MODE == CLOCK_MODE_NONE)
// No clock setup
#else
// XTAL0/EXTAL0 Pins
// Shouldn't be needed as default
// SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
// PORTA->PCR[18] = PORT_PCR_MUX(0);
// PORTA->PCR[19] = PORT_PCR_MUX(0);
// Configure the Crystal Oscillators
OSC0->CR = OSC0_CR_ERCLKEN_M|OSC0_CR_EREFSTEN_M|OSC0_CR_SCP_M;
// XTAL/EXTAL Pins
// Shouldn't be needed as default
// SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
// PORTE_PCR24 = PORT_PCR_MUX(0);
// PORTE_PCR25 = PORT_PCR_MUX(0);
SIM->SCGC1 |= SIM_SCGC1_OSC1_MASK;
OSC1->CR = OSC1_CR_ERCLKEN_M|OSC1_CR_EREFSTEN_M|OSC1_CR_SCP_M;
#if (MCG_C7_OSCSEL_V != 0)
SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
// Configure the RTC Crystal Oscillator
RTC->CR = RTC_CR_SCP_M|RTC_CR_CLKO_M|RTC_CR_OSCE_M|RTC_CR_UM_M|RTC_CR_SUP_M|RTC_CR_WPE_M;
#endif
// Select OSCCLK Source
MCG->C7 = MCG_C7_OSCSEL_M; // OSCSEL = 0,1 -> XTAL/XTAL32
// Fast Internal Clock divider
MCG->SC = MCG_SC_FCRDIV_M;
// Out of reset MCG is in FEI mode
// =============================================================
// Set conservative SIM clock dividers BEFORE switching to ensure the clock speed remain within specification
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(7) | SIM_CLKDIV1_OUTDIV3(3) | SIM_CLKDIV1_OUTDIV4(7);
// Switch from FEI -> FEI/FBI/FEE/FBE
// =============================================================
// Set up crystal or external clock source for OSC0
MCG->C2 =
MCG_C2_LOCRE0_M | // LOCRE0 = 0,1 -> Loss of clock reset enable
MCG_C2_RANGE0_M | // RANGE0 = 0,1,2 -> Oscillator low/high/very high clock range
MCG_C2_HGO0_M | // HGO0 = 0,1 -> Oscillator low power/high gain
MCG_C2_EREFS0_M | // EREFS0 = 0,1 -> Select external clock/crystal oscillator
MCG_C2_IRCS_M; // IRCS = 0,1 -> Select slow/fast internal clock for internal reference
// Set up crystal or external clock source for OSC1
MCG->C10 = MCG_C10_LOCRE2_M | // LOCRE1 = 0,1 -> Loss of clock reset enable
MCG_C10_RANGE1_M | // RANGE1 = 0,1,2 -> Oscillator low/high/very high clock range
MCG_C10_HGO1_M | // HGO1 = 0,1 -> Oscillator low power/high gain
MCG_C10_EREFS1_M; // EREFS1 = 0,1 -> Select external clock/crystal oscillator
// Set up RTC clock monitor
MCG->C8 = MCG_C8_LOCRE1_M | // LOCRE1 = 0,1 -> Loss of Lock Reset enable
MCG_C8_CME1_M; // CME1 = 0,1 -> Clock monitor enable
#if ((CLOCK_MODE == CLOCK_MODE_FEI) || (CLOCK_MODE == CLOCK_MODE_FBI) || (CLOCK_MODE == CLOCK_MODE_BLPI) )
// Transition via FBI
//=====================================
#define BYPASS (1) // CLKS value used while FLL locks
MCG->C1 = MCG_C1_CLKS(BYPASS) | // CLKS = X -> External reference source while PLL locks
MCG_C1_FRDIV_M | // FRDIV = N -> XTAL/2^n ~ 31.25 kHz
MCG_C1_IREFS_M | // IREFS = 0,1 -> External/Slow IRC for FLL source
MCG_C1_IRCLKEN_M | // IRCLKEN = 0,1 -> IRCLK disable/enable
MCG_C1_IREFSTEN_M; // IREFSTEN = 0,1 -> Internal reference enabled in STOP mode
// Wait for S_IREFST to indicate FLL Reference has switched
do {
__asm__("nop");
} while ((MCG->S & MCG_S_IREFST_MASK) != (MCG_C1_IREFS_V<<MCG_S_IREFST_SHIFT));
// Wait for S_CLKST to indicating that OUTCLK has switched to bypass PLL/FLL
do {
__asm__("nop");
} while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(BYPASS));
// Set FLL Parameters
MCG->C4 = (MCG->C4&~(MCG_C4_DMX32_MASK|MCG_C4_DRST_DRS_MASK))|MCG_C4_DMX32_M|MCG_C4_DRST_DRS_M;
#endif
#if ((CLOCK_MODE == CLOCK_MODE_FBE) || (CLOCK_MODE == CLOCK_MODE_FEE) || (CLOCK_MODE == CLOCK_MODE_PLBE) || (CLOCK_MODE == CLOCK_MODE_PBE) || (CLOCK_MODE == CLOCK_MODE_PEE))
// Transition via FBE
//=====================================
#define BYPASS (2) // CLKS value used while PLL locks
MCG->C1 = MCG_C1_CLKS(BYPASS) | // CLKS = 2 -> External reference source while PLL locks
MCG_C1_FRDIV_M | // FRDIV = N -> XTAL/2^n ~ 31.25 kHz
MCG_C1_IREFS_M | // IREFS = 0,1 -> External/Slow IRC for FLL source
MCG_C1_IRCLKEN_M | // IRCLKEN = 0,1 -> IRCLK disable/enable
MCG_C1_IREFSTEN_M; // IREFSTEN = 0,1 -> Internal reference enabled in STOP mode
#if (MCG_C2_EREFS0_V != 0)
// Wait for oscillator 0 stable (if used)
do {
__asm__("nop");
} while ((MCG->S & MCG_S_OSCINIT0_MASK) == 0);
#endif
#if (MCG_C10_EREFS1_V != 0)
// Wait for oscillator 1 stable (if used)
do {
__asm__("nop");
} while ((MCG->S2 & MCG_S2_OSCINIT1_MASK) == 0);
#endif
// Wait for S_IREFST to indicate FLL Reference has switched
do {
__asm__("nop");
} while ((MCG->S & MCG_S_IREFST_MASK) != (MCG_C1_IREFS_V<<MCG_S_IREFST_SHIFT));
// Wait for S_CLKST to indicating that OUTCLK has switched to bypass PLL/FLL
do {
__asm__("nop");
} while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(BYPASS));
// Set FLL Parameters
MCG->C4 = (MCG->C4&~(MCG_C4_DMX32_MASK|MCG_C4_DRST_DRS_MASK))|MCG_C4_DMX32_M|MCG_C4_DRST_DRS_M;
#endif
// Configure PLL0 Reference Frequency
// =============================================================
MCG->C5 = MCG_C5_PLLREFSEL0_M | // PLLREFSEL0 = 0,1 -> OSC0/OSC1 select
MCG_C5_PLLCLKEN0_M | // PLLCLKEN0 = 0,1 -> PLL -/enabled (irrespective of PLLS)
MCG_C5_PLLSTEN0_M | // PLLSTEN0 = 0,1 -> disabled/enabled in normal stop mode
MCG_C5_PRDIV0_M; // PRDIV0 = N -> PLL divider so PLL Ref. Freq. = 8-16 MHz
// Configure PLL1 Reference Frequency
// =============================================================
MCG->C11 = MCG_C11_PLLREFSEL1_M | // PLLREFSEL1 = 0,1 -> OSC0/OSC1 select
MCG_C11_PLLCLKEN1_M | // PLLCLKEN = 0,1 -> PLL -/enabled (irrespective of PLLS)
MCG_C11_PLLSTEN1_M | // PLLSTEN0 = 0,1 -> disabled/enabled in normal stop mode
MCG_C11_PLLCS_M | // PLLCS = 0,1 -> PLL0/PLL1 used as MCG source
MCG_C11_PRDIV1_M; // PRDIV0 = N -> PLL divider so PLL Ref. Freq. = 8-16 MHz
// Set up PLL0
// =============================================================
MCG->C6 = MCG_C6_LOLIE0_M | // LOLIE0 = 0,1 -> Loss of Lock interrupt
MCG_C6_PLLS_M | // PLLS = 0,1 -> Enable PLL
MCG_C6_CME0_M | // CME0 = 0,1 -> Disable/enable clock monitor
MCG_C6_VDIV0_M; // VDIV0 = N -> PLL Multiplication factor
// Set up PLL1
// =============================================================
MCG->C12 = MCG_C12_LOLIE1_M | // LOLIE1 = 0,1 -> Loss of Lock interrupt
MCG_C12_CME2_M | // CME2 = 0,1 -> Disable/enable clock monitor
MCG_C12_VDIV1_M; // VDIV1 = N -> PLL Multiplication factor
#if ((CLOCK_MODE == CLOCK_MODE_PBE) || (CLOCK_MODE == CLOCK_MODE_PEE))
// Transition via PBE
// =============================================================
#if (MCG_C11_PLLCS_M == 0)
// Wait for PLL0 to lock
do {
__asm__("nop");
} while((MCG->S & MCG_S_LOCK0_MASK) == 0);
#else
// Wait for PLL1 to lock
do {
__asm__("nop");
} while((MCG->S2 & MCG_S2_LOCK1_MASK) == 0);
#endif
// Wait until PLLS clock source changes to the PLL clock out
do {
__asm__("nop");
} while((MCG->S & MCG_S_PLLST_MASK) == 0);
#endif
#if ((CLOCK_MODE == CLOCK_MODE_FEI) || (CLOCK_MODE == CLOCK_MODE_FEE))
// Wait for FLL to lock
do {
__asm__("nop");
} while ((MCG->C4&MCG_C4_DRST_DRS_MASK) != MCG_C4_DRST_DRS_M);
#endif
// Select FEI/FBI/FEE/FBE/PBE/PEE clock mode
MCG->C1 = MCG_C1_CLKS_M | // CLKS = 0,1,2 -> Select FLL/IRCSCLK/ERCLK
MCG_C1_FRDIV_M | // FRDIV = N -> XTAL/2^n ~ 31.25 kHz
MCG_C1_IREFS_M | // IREFS = 0,1 -> External/Slow IRC for FLL source
MCG_C1_IRCLKEN_M | // IRCLKEN = 0,1 -> IRCLK disable/enable
MCG_C1_IREFSTEN_M; // IREFSTEN = 0,1 -> Internal reference enabled in STOP mode
// Wait for mode change
do {
__asm__("nop");
} while ((MCG->S & MCG_S_IREFST_MASK) != (MCG_C1_IREFS_V<<MCG_S_IREFST_SHIFT));
#if defined (MCG_C6_PLLS_V) && (MCG_C1_CLKS_V == 0) // FLL or PLL
#define MCG_S_CLKST_M MCG_S_CLKST(MCG_C6_PLLS_V?3:0)
#else
#define MCG_S_CLKST_M MCG_S_CLKST(MCG_C1_CLKS_V)
#endif
// Wait for S_CLKST to indicating that OUTCLK has switched
do {
__asm__("nop");
} while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_M);
// Set the SIM _CLKDIV dividers
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1_M | SIM_CLKDIV1_OUTDIV2_M | SIM_CLKDIV1_OUTDIV3_M | SIM_CLKDIV1_OUTDIV4_M;
#if (CLOCK_MODE == CLOCK_MODE_BLPE) || (CLOCK_MODE == CLOCK_MODE_BLPI)
// Select BLPE/BLPI clock mode
MCG->C2 =
MCG_C2_LOCRE0_M | // LOCRE0 = 0,1 -> Loss of clock reset
MCG_C2_RANGE0_M | // RANGE0 = 0,1,2 -> Oscillator low/high/very high clock range
MCG_C2_HGO0_M | // HGO0 = 0,1 -> Oscillator low power/high gain
MCG_C2_EREFS0_M | // EREFS0 = 0,1 -> Select external clock/crystal oscillator
MCG_C2_LP_M | // LP = 0,1 -> Select FLL enabled/disabled in bypass mode
MCG_C2_IRCS_M; // IRCS = 0,1 -> Select slow/fast internal clock for internal reference
#endif // (CLOCK_MODE == CLOCK_MODE_BLPE) || (CLOCK_MODE == CLOCK_MODE_BLPI)
#endif // (CLOCK_MODE == CLOCK_MODE_NONE)
/*!
* SOPT1 Clock multiplexing
*/
#if defined(SIM_SOPT1_OSC32KSEL_MASK) && defined(SIM_SOPT1_OSC32KSEL_M) // ERCLK32K source
SIM->SOPT1 = (SIM->SOPT1&~SIM_SOPT1_OSC32KSEL_MASK)|SIM_SOPT1_OSC32KSEL_M;
#endif
/*!
* SOPT2 Clock multiplexing
*/
#if defined(SIM_SOPT2_SDHCSRC_MASK) && defined(SIM_SOPT2_SDHCSRC_M) // SDHC clock
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_SDHCSRC_MASK)|SIM_SOPT2_SDHCSRC_M;
#endif
#if defined(SIM_SOPT2_TIMESRC_MASK) && defined(SIM_SOPT2_TIMESRC_M) // Ethernet time-stamp clock
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_TIMESRC_MASK)|SIM_SOPT2_TIMESRC_M;
#endif
#if defined(SIM_SOPT2_RMIISRC_MASK) && defined(SIM_SOPT2_RMIISRC_M) // RMII clock
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_RMIISRC_MASK)|SIM_SOPT2_RMIISRC_M;
#endif
#ifdef SIM_SCGC4_USBOTG_MASK
// !! WARNING !! The USB interface must be disabled for clock changes to have effect !! WARNING !!
SIM->SCGC4 &= ~SIM_SCGC4_USBOTG_MASK;
#endif
#if defined(SIM_SOPT2_USBSRC_MASK) && defined(SIM_SOPT2_USBSRC_M) // USB clock (48MHz req.)
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_USBSRC_MASK)|SIM_SOPT2_USBSRC_M;
#endif
#if defined(SIM_SOPT2_USBFSRC_MASK) && defined(SIM_SOPT2_USBFSRC_M) // USB clock (48MHz req.)
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_USBFSRC_MASK)|SIM_SOPT2_USBFSRC_M;
#endif
#if defined(SIM_SOPT2_PLLFLLSEL_MASK) && defined(SIM_SOPT2_PLLFLLSEL_M) // Peripheral clock
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_PLLFLLSEL_MASK)|SIM_SOPT2_PLLFLLSEL_M;
#endif
#if defined(SIM_SOPT2_UART0SRC_MASK) && defined(SIM_SOPT2_UART0SRC_M) // UART0 clock
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_UART0SRC_MASK)|SIM_SOPT2_UART0SRC_M;
#endif
#if defined(SIM_SOPT2_TPMSRC_MASK) && defined(SIM_SOPT2_TPMSRC_M) // TPM clock
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_TPMSRC_MASK)|SIM_SOPT2_TPMSRC_M;
#endif
#if defined(SIM_SOPT2_CLKOUTSEL_MASK) && defined(SIM_SOPT2_CLKOUTSEL_M)
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_CLKOUTSEL_MASK)|SIM_SOPT2_CLKOUTSEL_M;
#endif
#if defined(SIM_SOPT2_RTCCLKOUTSEL_MASK) && defined(SIM_SOPT2_RTCCLKOUTSEL_M)
SIM->SOPT2 = (SIM->SOPT2&~SIM_SOPT2_RTCCLKOUTSEL_MASK)|SIM_SOPT2_RTCCLKOUTSEL_M;
#endif
#if defined(SIM_CLKDIV2_USBDIV_MASK) && defined(SIM_CLKDIV2_USBFRAC_MASK) && defined(SIM_CLKDIV2_USB_M)
SIM->CLKDIV2 = (SIM->CLKDIV2&~(SIM_CLKDIV2_USBDIV_MASK|SIM_CLKDIV2_USBFRAC_MASK)) | SIM_CLKDIV2_USB_M;
#endif
SystemCoreClockUpdate();
}
// =============================================================================
// 功能：PLL初始化部分，主要对PLL和晶振初始化，是时间从内部时钟切换到外部时钟的主要部
// 分，此处使用PLL0和OSC0作为内部时钟源，经分频和倍频，使内核时钟达到150M
// 参数：crystal_fre_hz,外部晶振频率
// prdiv,PLL分频参数
// vdiv,PLL倍频参数
// 返回：实际配置的MCG输出频率
// =============================================================================
u32 PLL_Init(u32 crystal_fre_hz, u8 prdiv, u8 vdiv)
{
//reset后，系统处于FEI模式，时钟配置过程为：
//FEI--->FBE--->PBE--->PEE(手册640页table25-22)
//默认使用振荡器0，设置振荡器0
// 配置控制寄存器MCG_C2
// 先清bit位，配置高速晶振，high-gain operation，外部晶振
MCG->C2 &= ~(MCG_C2_RANGE0_MASK | MCG_C2_HGO0_MASK | MCG_C2_EREFS0_MASK);
MCG->C2 |= (MCG_C2_RANGE0(1)
| (0 << MCG_C2_HGO0_SHIFT)
| (0 << MCG_C2_EREFS0_SHIFT));
// 配置控制寄存器MCG_C1
//先清bit位，CLK为外部时钟，FRDIV为5时，配置分频为1024，即配置FLL处于
//31.25-39.0625 kHz 之间
MCG->C1 &= ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK);
MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(5);
while((MCG->S & MCG_S_IREFST_MASK)); //等待FLL时钟转为外部源
while(((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2);
// Now in FBE
MCG->C6 |= MCG_C6_CME0_MASK;
// start Configure PLL0
MCG->C5 &= ~MCG_C5_PLLREFSEL0_MASK; // ensure OSC0
MCG->C11 &= ~MCG_C11_PLLCS_MASK; // select PLL0
// Configure MCG_C5
MCG->C5 &= ~MCG_C5_PRDIV0_MASK; // clear settings
MCG->C5 |= MCG_C5_PRDIV0(prdiv - 1); //set PLL ref divider
// Configure MCG_C6
MCG->C6 &= ~MCG_C6_VDIV0_MASK; // clear settings
MCG->C6 |= MCG_C6_PLLS_MASK | MCG_C6_VDIV0(vdiv - 16); // write new VDIV
while(!(MCG->S & MCG_S_PLLST_MASK)); // wait for PLLST status bit to set
while(!(MCG->S & MCG_S_LOCK0_MASK)); // Wait for LOCK bit to set
// Use actual PLL settings to calculate PLL frequency
prdiv = ((MCG->C5 & MCG_C5_PRDIV0_MASK) + 1);
vdiv = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 16);
// now in PBE
MCG->C1 &= ~MCG_C1_CLKS_MASK; // 清CLKS，选择MCG_OUT源为PLL
while(((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3);
// start Configure PLL1 if needed, for DDR,so, CLK = 100MHz
#if (CN_CFG_DDR_USED == 1)
// Configure MCG_C12
MCG->C11 &= ~MCG_C11_PLLREFSEL1_MASK; // Clear select bit to choose OSC0
MCG->C11 &= ~MCG_C11_PRDIV1_MASK;
MCG->C11 |= MCG_C11_PRDIV1(5 - 1);
MCG->C12 &= ~MCG_C12_VDIV1_MASK; // clear VDIV settings
MCG->C12 |= MCG_C12_VDIV1(24 - 16); // write new VDIV and enable PLL
// Now enable the PLL
MCG->C11 |= MCG_C11_PLLCLKEN1_MASK; // Set PLLCLKEN2 to enable PLL1
while(!(MCG->S2 & MCG_S2_LOCK1_MASK)); // Wait for PLL1 locked
#endif
//MCGOUT equals PLL output frequency/2
return (((crystal_fre_hz / prdiv) * vdiv) / 2);
}
/**
* @brief MK20D5 clock initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function is meant to be invoked early during the system
* initialization, it is usually invoked from the file
* @p board.c.
* @todo This function needs to be more generic.
*
* @special
*/
void mk20d50_clock_init(void) {
/* Disable the watchdog */
WDOG->UNLOCK = 0xC520;
WDOG->UNLOCK = 0xD928;
WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN;
SIM->SCGC5 |= SIM_SCGC5_PORTA |
SIM_SCGC5_PORTB |
SIM_SCGC5_PORTC |
SIM_SCGC5_PORTD |
SIM_SCGC5_PORTE;
/* EXTAL0 and XTAL0 */
PORTA->PCR[18] = 0;
PORTA->PCR[19] = 0;
/*
* Start in FEI mode
*/
/* Disable capacitors for crystal */
OSC->CR = 0;
/* Enable OSC, 8-32 MHz range, low power mode */
MCG->C2 = MCG_C2_RANGE0(1) | MCG_C2_LOCRE0 | MCG_C2_EREFS0;
/* Switch to crystal as clock source, FLL input of 8 MHz / 256 = 31.25 KHz */
MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
/* Wait for crystal oscillator to begin */
while (!(MCG->S & MCG_S_OSCINIT0));
/* Wait for the FLL to use the oscillator */
while (MCG->S & MCG_S_IREFST);
/* Wait for the MCGOUTCLK to use the oscillator */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));
/*
* Now in FBE mode
*/
/* Config PLL input for 2 MHz (8 MHz crystal / 4) */
MCG->C5 = MCG_C5_PRDIV0(3);
/* Config PLL for 96 MHz output */
MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
/* Wait for PLL to start using crystal as its input */
while (!(MCG->S & MCG_S_PLLST));
/* Wait for PLL to lock */
while (!(MCG->S & MCG_S_LOCK0));
/*
* Now in PBE mode
*/
/* Switch to PLL as clock source */
MCG->C1 = MCG_C1_CLKS(0);
/* Wait for PLL clock to be used */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
/*
* Now in PEE mode
*/
}
/*lint -esym(765,Cpu_Interrupt) Disable MISRA rule (8.10) checking for symbols (Cpu_Interrupt). */
void __init_hardware(void)
{
/*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/
/*** ### MK22FX512VLQ12 "Cpu" init code ... ***/
/*** PE initialization code after reset ***/
SCB_VTOR = (uint32_t)(&__vect_table); /* Set the interrupt vector table position */
/* Disable the WDOG module */
/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
/* WDOG_UNLOCK: WDOGUNLOCK=0xD928 */
WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
/* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG_STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
WDOG_STCTRLH_WAITEN_MASK |
WDOG_STCTRLH_STOPEN_MASK |
WDOG_STCTRLH_ALLOWUPDATE_MASK |
WDOG_STCTRLH_CLKSRC_MASK |
0x0100U;
/* System clock initialization */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x01) |
SIM_CLKDIV1_OUTDIV3(0x03) |
SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */
/* SIM_SCGC5: PORTE=1,PORTD=1,PORTB=1,PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK |
SIM_SCGC5_PORTD_MASK |
SIM_SCGC5_PORTB_MASK |
SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
/* SIM_SCGC5: LPTMR=1 */
SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK;
if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {
/* PMC_REGSC: ACKISO=1 */
PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */
}
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x01) |
SIM_CLKDIV1_OUTDIV3(0x04) |
SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */
/* SIM_SOPT2: PLLFLLSEL=1 */
SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=3 */
SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* PORTA_PCR19: ISF=0,MUX=0 */
PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* Switch to FBE Mode */
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK);
/* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC_CR = OSC_CR_ERCLKEN_MASK;
/* MCG_C7: OSCSEL=0 */
MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK);
/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
MCG_C5 = MCG_C5_PRDIV0(0x01);
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=6 */
MCG_C6 = MCG_C6_VDIV0(0x06);
while((MCG_S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
}
while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to PBE Mode */
/* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK);
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x06));
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
}
/* Switch to PEE Mode */
/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK);
while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
}
/*** End of PE initialization code after reset ***/
/*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/
}
/*lint -esym(765,Cpu_Interrupt) Disable MISRA rule (8.10) checking for symbols (Cpu_Interrupt). */
void __init_hardware(void)
{
/*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/
/*** ### MK70FN1M0VMJ12 "Cpu" init code ... ***/
/*** PE initialization code after reset ***/
SCB_VTOR = (uint32_t)(&__vect_table); /* Set the interrupt vector table position */
/* Disable the WDOG module */
/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
/* WDOG_UNLOCK: WDOGUNLOCK=0xD928 */
WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
/* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG_STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
WDOG_STCTRLH_WAITEN_MASK |
WDOG_STCTRLH_STOPEN_MASK |
WDOG_STCTRLH_ALLOWUPDATE_MASK |
WDOG_STCTRLH_CLKSRC_MASK |
0x0100U;
/* System clock initialization */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x01) |
SIM_CLKDIV1_OUTDIV3(0x03) |
SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */
/* SIM_SCGC5: PORTE=1,PORTA=1 */
SIM_SCGC5 |= (SIM_SCGC5_PORTE_MASK | SIM_SCGC5_PORTA_MASK); /* Enable clock gate for ports to enable pin routing */
if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {
/* PMC_REGSC: ACKISO=1 */
PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */
}
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x00) |
SIM_CLKDIV1_OUTDIV3(0x01) |
SIM_CLKDIV1_OUTDIV4(0x01); /* Update system prescalers */
/* SIM_SOPT2: PLLFLLSEL=0 */
SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL(0x03)); /* Select FLL as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=0 */
SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL_MASK); /* System oscillator drives 32 kHz clock for various peripherals */
/* SIM_SCGC1: OSC1=1 */
SIM_SCGC1 |= SIM_SCGC1_OSC1_MASK;
/* Switch to FEI Mode */
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG_C1 = MCG_C1_CLKS(0x00) |
MCG_C1_FRDIV(0x00) |
MCG_C1_IREFS_MASK |
MCG_C1_IRCLKEN_MASK;
/* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG_C2 = MCG_C2_RANGE0(0x00);
/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0_CR = OSC_CR_ERCLKEN_MASK;
/* MCG_C10: LOCRE2=0,??=0,RANGE1=0,HGO1=0,EREFS1=0,??=0,??=0 */
MCG_C10 = MCG_C10_RANGE1(0x00);
/* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC1_CR = OSC_CR_ERCLKEN_MASK;
/* MCG_C7: OSCSEL=0 */
MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
/* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=0 */
MCG_C5 = MCG_C5_PRDIV0(0x00);
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG_C6 = MCG_C6_VDIV0(0x00);
/* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
MCG_C11 = MCG_C11_PRDIV1(0x00);
/* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
MCG_C12 = MCG_C12_VDIV1(0x00); /* 3 */
while((MCG_S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG_S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
}
/*** End of PE initialization code after reset ***/
/*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/
}
