int
pqmdio_miibus_readreg(device_t dev, int phy, int reg)
{
struct pqmdio_softc *sc;
int rv;
sc = device_get_softc(dev);
MDIO_LOCK();
MDIO_WRITE4(sc, MDIO_MIIMADD, (phy << 8) | reg);
MDIO_WRITE4(sc, MDIO_MIIMCOM, MIIMCOM_READ_CYCLE);
MDIO_READ4(sc, MDIO_MIIMCOM);
while ((MDIO_READ4(sc, MDIO_MIIMIND)) & MIIMIND_BUSY)
;
rv = MDIO_READ4(sc, MDIO_MIIMSTAT);
MDIO_WRITE4(sc, MDIO_MIIMCOM, 0);
MDIO_READ4(sc, MDIO_MIIMCOM);
MDIO_UNLOCK();
return (rv);
}
/**
* Perform an MII write. Called by the generic MII routines
*
* @param dev Device to perform write for
* @param phy_id The MII phy id
* @param location Register location to write
* @param val Value to write
*/
void cvm_oct_mdio_write(struct ifnet *ifp, int phy_id, int location, int val)
{
cvmx_smi_cmd_t smi_cmd;
cvmx_smi_wr_dat_t smi_wr;
MDIO_LOCK();
smi_wr.u64 = 0;
smi_wr.s.dat = val;
cvmx_write_csr(CVMX_SMI_WR_DAT, smi_wr.u64);
smi_cmd.u64 = 0;
smi_cmd.s.phy_op = 0;
smi_cmd.s.phy_adr = phy_id;
smi_cmd.s.reg_adr = location;
cvmx_write_csr(CVMX_SMI_CMD, smi_cmd.u64);
do {
smi_wr.u64 = cvmx_read_csr(CVMX_SMI_WR_DAT);
} while (smi_wr.s.pending);
MDIO_UNLOCK();
}
/**
* Perform an MII read. Called by the generic MII routines
*
* @param dev Device to perform read for
* @param phy_id The MII phy id
* @param location Register location to read
* @return Result from the read or zero on failure
*/
int cvm_oct_mdio_read(struct ifnet *ifp, int phy_id, int location)
{
cvmx_smi_cmd_t smi_cmd;
cvmx_smi_rd_dat_t smi_rd;
MDIO_LOCK();
smi_cmd.u64 = 0;
smi_cmd.s.phy_op = 1;
smi_cmd.s.phy_adr = phy_id;
smi_cmd.s.reg_adr = location;
cvmx_write_csr(CVMX_SMI_CMD, smi_cmd.u64);
do {
smi_rd.u64 = cvmx_read_csr(CVMX_SMI_RD_DAT);
} while (smi_rd.s.pending);
MDIO_UNLOCK();
if (smi_rd.s.val)
return smi_rd.s.dat;
else
return 0;
}
int
pqmdio_miibus_writereg(device_t dev, int phy, int reg, int value)
{
struct pqmdio_softc *sc;
sc = device_get_softc(dev);
MDIO_LOCK();
/* Stop the MII management read cycle */
MDIO_WRITE4(sc, MDIO_MIIMCOM, 0);
MDIO_READ4(sc, MDIO_MIIMCOM);
MDIO_WRITE4(sc, MDIO_MIIMADD, (phy << 8) | reg);
MDIO_WRITE4(sc, MDIO_MIIMCON, value);
MDIO_READ4(sc, MDIO_MIIMCON);
/* Wait till MII management write is complete */
while ((MDIO_READ4(sc, MDIO_MIIMIND)) & MIIMIND_BUSY)
;
MDIO_UNLOCK();
return (0);
}