static u32 mdss_mdp_res_init(struct platform_device *pdev)
{
u32 rc;
rc = mdss_mdp_irq_clk_setup(pdev);
if (rc)
return rc;
mdss_res->clk_ctrl_wq = create_singlethread_workqueue("mdp_clk_wq");
INIT_DELAYED_WORK(&mdss_res->clk_ctrl_worker,
mdss_mdp_clk_ctrl_workqueue_handler);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
mdss_res->rev = MDSS_MDP_REG_READ(MDSS_REG_HW_VERSION);
mdss_res->mdp_rev = MDSS_MDP_REG_READ(MDSS_MDP_REG_HW_VERSION);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
mdss_res->smp_mb_cnt = MDSS_MDP_SMP_MMB_BLOCKS;
mdss_res->smp_mb_size = MDSS_MDP_SMP_MMB_SIZE;
mdss_res->pipe_type_map = mdss_mdp_pipe_type_map;
mdss_res->mixer_type_map = mdss_mdp_mixer_type_map;
pr_info("mdss_revision=%x\n", mdss_res->rev);
pr_info("mdp_hw_revision=%x\n", mdss_res->mdp_rev);
mdss_res->res_init = true;
mdss_res->timeout = HZ/20;
mdss_res->clk_ena = false;
mdss_res->irq_mask = MDSS_MDP_DEFAULT_INTR_MASK;
mdss_res->suspend = false;
mdss_res->prim_ptype = NO_PANEL;
mdss_res->irq_ena = false;
return 0;
}
void mdss_interrupts_dump(void)
{
u32 isr, mask;
isr = MDSS_MDP_REG_READ(MDSS_MDP_REG_INTR_STATUS);
mask = MDSS_MDP_REG_READ(MDSS_MDP_REG_INTR_EN);
MDSS_TIMEOUT_LOG("MDSS_MDP_REG_INTR_STATUS: 0x%08X\n", isr);
MDSS_TIMEOUT_LOG("MDSS_MDP_REG_INTR_EN: 0x%08X\n", mask);
MDSS_TIMEOUT_LOG("global irqs disabled: %d\n", irqs_disabled());
}
irqreturn_t mdss_mdp_isr(int irq, void *ptr)
{
u32 isr, mask;
isr = MDSS_MDP_REG_READ(MDSS_MDP_REG_INTR_STATUS);
pr_debug("isr=%x\n", isr);
if (isr == 0)
goto done;
mask = MDSS_MDP_REG_READ(MDSS_MDP_REG_INTR_EN);
MDSS_MDP_REG_WRITE(MDSS_MDP_REG_INTR_CLEAR, isr);
isr &= mask;
if (isr == 0)
goto done;
if (isr & MDSS_MDP_INTR_PING_PONG_0_DONE)
mdss_mdp_intr_done(MDP_INTR_PING_PONG_0);
if (isr & MDSS_MDP_INTR_PING_PONG_1_DONE)
mdss_mdp_intr_done(MDP_INTR_PING_PONG_1);
if (isr & MDSS_MDP_INTR_PING_PONG_2_DONE)
mdss_mdp_intr_done(MDP_INTR_PING_PONG_2);
if (isr & MDSS_MDP_INTR_INTF_0_VSYNC)
mdss_mdp_intr_done(MDP_INTR_VSYNC_INTF_0);
if (isr & MDSS_MDP_INTR_INTF_1_VSYNC)
mdss_mdp_intr_done(MDP_INTR_VSYNC_INTF_1);
if (isr & MDSS_MDP_INTR_INTF_2_VSYNC)
mdss_mdp_intr_done(MDP_INTR_VSYNC_INTF_2);
if (isr & MDSS_MDP_INTR_INTF_3_VSYNC)
mdss_mdp_intr_done(MDP_INTR_VSYNC_INTF_3);
if (isr & MDSS_MDP_INTR_WB_0_DONE)
mdss_mdp_intr_done(MDP_INTR_WB_0);
if (isr & MDSS_MDP_INTR_WB_1_DONE)
mdss_mdp_intr_done(MDP_INTR_WB_1);
if (isr & MDSS_MDP_INTR_WB_2_DONE)
mdss_mdp_intr_done(MDP_INTR_WB_2);
done:
return IRQ_HANDLED;
}
static u32 mdss_mdp_res_init(struct mdss_data_type *mdata)
{
u32 rc = 0;
rc = mdss_mdp_irq_clk_setup(mdata);
if (rc)
return rc;
mdata->clk_ctrl_wq = create_singlethread_workqueue("mdp_clk_wq");
INIT_DELAYED_WORK(&mdata->clk_ctrl_worker,
mdss_mdp_clk_ctrl_workqueue_handler);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
mdata->rev = MDSS_MDP_REG_READ(MDSS_REG_HW_VERSION);
mdata->mdp_rev = MDSS_MDP_REG_READ(MDSS_MDP_REG_HW_VERSION);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
mdata->smp_mb_cnt = MDSS_MDP_SMP_MMB_BLOCKS;
mdata->smp_mb_size = MDSS_MDP_SMP_MMB_SIZE;
mdata->pipe_type_map = mdss_mdp_pipe_type_map;
mdata->mixer_type_map = mdss_mdp_mixer_type_map;
pr_info("mdss_revision=%x\n", mdata->rev);
pr_info("mdp_hw_revision=%x\n", mdata->mdp_rev);
mdata->res_init = true;
mdata->timeout = HZ/20;
mdata->clk_ena = false;
mdata->irq_mask = MDSS_MDP_DEFAULT_INTR_MASK;
mdata->suspend = false;
mdata->prim_ptype = NO_PANEL;
mdata->irq_ena = false;
mdata->iclient = msm_ion_client_create(-1, mdata->pdev->name);
if (IS_ERR_OR_NULL(mdata->iclient)) {
pr_err("msm_ion_client_create() return error (%p)\n",
mdata->iclient);
mdata->iclient = NULL;
}
rc = mdss_iommu_init();
if (!IS_ERR_VALUE(rc))
mdss_iommu_attach();
rc = mdss_hw_init(mdata);
return rc;
}
static irqreturn_t mdss_irq_handler(int irq, void *ptr)
{
struct mdss_data_type *mdata = ptr;
u32 intr = MDSS_MDP_REG_READ(MDSS_REG_HW_INTR_STATUS);
if (!mdata)
return IRQ_NONE;
mdata->irq_buzy = true;
if (intr & MDSS_INTR_MDP) {
spin_lock(&mdp_lock);
mdss_irq_dispatch(MDSS_HW_MDP, irq, ptr);
spin_unlock(&mdp_lock);
}
if (intr & MDSS_INTR_DSI0)
mdss_irq_dispatch(MDSS_HW_DSI0, irq, ptr);
if (intr & MDSS_INTR_DSI1)
mdss_irq_dispatch(MDSS_HW_DSI1, irq, ptr);
if (intr & MDSS_INTR_EDP)
mdss_irq_dispatch(MDSS_HW_EDP, irq, ptr);
if (intr & MDSS_INTR_HDMI)
mdss_irq_dispatch(MDSS_HW_HDMI, irq, ptr);
mdata->irq_buzy = false;
return IRQ_HANDLED;
}
static irqreturn_t mdss_irq_handler(int irq, void *ptr)
{
u32 intr = MDSS_MDP_REG_READ(MDSS_REG_HW_INTR_STATUS);
mdss_res->irq_buzy = true;
if (intr & MDSS_INTR_MDP)
mdss_irq_dispatch(MDSS_HW_MDP, irq, ptr);
if (intr & MDSS_INTR_DSI0)
mdss_irq_dispatch(MDSS_HW_DSI0, irq, ptr);
if (intr & MDSS_INTR_DSI1)
mdss_irq_dispatch(MDSS_HW_DSI1, irq, ptr);
if (intr & MDSS_INTR_EDP)
mdss_irq_dispatch(MDSS_HW_EDP, irq, ptr);
if (intr & MDSS_INTR_HDMI)
mdss_irq_dispatch(MDSS_HW_HDMI, irq, ptr);
mdss_res->irq_buzy = false;
return IRQ_HANDLED;
}
static void mdss_mdp_smp_mmb_set(int client_id, unsigned long *smp)
{
u32 mmb, off, data, s;
for_each_set_bit(mmb, smp, SMP_MB_CNT) {
off = (mmb / 3) * 4;
s = (mmb % 3) * 8;
data = MDSS_MDP_REG_READ(MDSS_MDP_REG_SMP_ALLOC_W0 + off);
data &= ~(0xFF << s);
data |= client_id << s;
MDSS_MDP_REG_WRITE(MDSS_MDP_REG_SMP_ALLOC_W0 + off, data);
MDSS_MDP_REG_WRITE(MDSS_MDP_REG_SMP_ALLOC_R0 + off, data);
}
int mdss_hw_init(struct mdss_data_type *mdata)
{
int i, j;
char *offset;
struct mdss_mdp_pipe *vig;
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
mdata->mdp_rev = MDSS_MDP_REG_READ(MDSS_MDP_REG_HW_VERSION);
pr_info_once("MDP Rev=%x\n", mdata->mdp_rev);
if (mdata->hw_settings) {
struct mdss_hw_settings *hws = mdata->hw_settings;
while (hws->reg) {
writel_relaxed(hws->val, hws->reg);
hws++;
}
}
for (i = 0; i < mdata->nmixers_intf; i++) {
offset = mdata->mixer_intf[i].dspp_base +
MDSS_MDP_REG_DSPP_HIST_LUT_BASE;
for (j = 0; j < ENHIST_LUT_ENTRIES; j++)
writel_relaxed(j, offset);
/* swap */
writel_relaxed(1, offset + 4);
}
vig = mdata->vig_pipes;
for (i = 0; i < mdata->nvig_pipes; i++) {
offset = vig[i].base +
MDSS_MDP_REG_VIG_HIST_LUT_BASE;
for (j = 0; j < ENHIST_LUT_ENTRIES; j++)
writel_relaxed(j, offset);
/* swap */
writel_relaxed(1, offset + 16);
}
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
pr_debug("MDP hw init done\n");
return 0;
}
void htc_set_pp_pa(struct mdss_mdp_ctl *ctl)
{
struct mdss_data_type *mdata;
struct mdss_mdp_mixer *mixer;
u32 base = 0, opmode;
char __iomem *basel;
if (htc_mdss_pp_pa[HUE_INDEX].req_value == htc_mdss_pp_pa[HUE_INDEX].cur_value)
return;
if (htc_mdss_pp_pa[HUE_INDEX].req_value >= HUE_MAX)
return;
mdata = mdss_mdp_get_mdata();
mixer = mdata->mixer_intf;
base = MDSS_MDP_REG_DSPP_OFFSET(0);
basel = mixer->dspp_base;
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
MDSS_MDP_REG_WRITE(base + MDSS_MDP_REG_DSPP_PA_BASE, htc_mdss_pp_pa[HUE_INDEX].req_value);
opmode = MDSS_MDP_REG_READ(base);
opmode |= (1 << 20);
writel_relaxed(opmode, basel + MDSS_MDP_REG_DSPP_OP_MODE);
ctl->flush_bits |= BIT(13);
wmb();
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
htc_mdss_pp_pa[HUE_INDEX].cur_value = htc_mdss_pp_pa[HUE_INDEX].req_value;
PR_DISP_INFO("%s pp_hue = 0x%x\n", __func__, htc_mdss_pp_pa[HUE_INDEX].req_value);
}
static int mdss_mdp_ctl_init(struct msm_fb_data_type *mfd)
{
struct mdss_mdp_ctl *ctl;
struct mdss_panel_data *pdata;
u32 width, height;
int ret = 0;
if (!mfd)
return -ENODEV;
pdata = dev_get_platdata(&mfd->pdev->dev);
if (!pdata) {
pr_err("no panel connected for fb%d\n", mfd->index);
return -ENODEV;
}
width = pdata->panel_info.xres;
height = pdata->panel_info.yres;
if (width > (2 * MAX_MIXER_WIDTH)) {
pr_err("unsupported resolution\n");
return -EINVAL;
}
if (!mfd->ctl) {
ctl = mdss_mdp_ctl_alloc();
if (!ctl) {
pr_err("unable to allocate ctl\n");
return -ENOMEM;
}
ctl->mfd = mfd;
mfd->ctl = ctl;
ctl->panel_data = pdata;
} else {
ctl = mfd->ctl;
}
ctl->width = width;
ctl->height = height;
if (!ctl->mixer_left) {
ctl->mixer_left =
mdss_mdp_mixer_alloc(MDSS_MDP_MIXER_TYPE_INTF);
if (!ctl->mixer_left) {
pr_err("unable to allocate layer mixer\n");
ret = -ENOMEM;
goto ctl_init_fail;
}
}
if (width > MAX_MIXER_WIDTH)
width /= 2;
ctl->mixer_left->width = width;
ctl->mixer_left->height = height;
ctl->mixer_left->ctl = ctl;
if (width < ctl->width) {
if (ctl->mixer_right == NULL) {
ctl->mixer_right =
mdss_mdp_mixer_alloc(MDSS_MDP_MIXER_TYPE_INTF);
if (!ctl->mixer_right) {
pr_err("unable to allocate right mixer\n");
ret = -ENOMEM;
goto ctl_init_fail;
}
}
ctl->mixer_right->width = width;
ctl->mixer_right->height = height;
ctl->mixer_right->ctl = ctl;
} else if (ctl->mixer_right) {
mdss_mdp_mixer_free(ctl->mixer_right);
}
switch (pdata->panel_info.type) {
case EDP_PANEL:
ctl->intf_num = MDSS_MDP_INTF0;
ctl->intf_type = MDSS_INTF_EDP;
ctl->opmode = MDSS_MDP_CTL_OP_VIDEO_MODE;
ctl->start_fnc = mdss_mdp_video_start;
break;
case MIPI_VIDEO_PANEL:
if (pdata->panel_info.pdest == DISPLAY_1)
ctl->intf_num = MDSS_MDP_INTF1;
else
ctl->intf_num = MDSS_MDP_INTF2;
ctl->intf_type = MDSS_INTF_DSI;
ctl->opmode = MDSS_MDP_CTL_OP_VIDEO_MODE;
ctl->start_fnc = mdss_mdp_video_start;
break;
case DTV_PANEL:
ctl->intf_num = MDSS_MDP_INTF3;
ctl->intf_type = MDSS_INTF_HDMI;
ctl->opmode = MDSS_MDP_CTL_OP_VIDEO_MODE;
ctl->start_fnc = mdss_mdp_video_start;
break;
case WRITEBACK_PANEL:
ctl->intf_num = MDSS_MDP_NO_INTF;
ctl->opmode = MDSS_MDP_CTL_OP_WFD_MODE;
ctl->start_fnc = mdss_mdp_writeback_start;
break;
default:
pr_err("unsupported panel type (%d)\n", pdata->panel_info.type);
ret = -EINVAL;
goto ctl_init_fail;
}
ctl->opmode |= (ctl->intf_num << 4);
if (ctl->intf_num == MDSS_MDP_NO_INTF) {
ctl->dst_format = pdata->panel_info.out_format;
} else {
struct mdp_dither_cfg_data dither = {
.block = mfd->index + MDP_LOGICAL_BLOCK_DISP_0,
.flags = MDP_PP_OPS_DISABLE,
};
switch (pdata->panel_info.bpp) {
case 18:
ctl->dst_format = MDSS_MDP_PANEL_FORMAT_RGB666;
dither.flags = MDP_PP_OPS_ENABLE | MDP_PP_OPS_WRITE;
dither.g_y_depth = 2;
dither.r_cr_depth = 2;
dither.b_cb_depth = 2;
break;
case 24:
default:
ctl->dst_format = MDSS_MDP_PANEL_FORMAT_RGB888;
break;
}
mdss_mdp_dither_config(&dither, NULL);
}
if (ctl->mixer_right) {
ctl->opmode |= MDSS_MDP_CTL_OP_PACK_3D_ENABLE |
MDSS_MDP_CTL_OP_PACK_3D_H_ROW_INT;
}
ctl_init_fail:
if (IS_ERR_VALUE(ret)) {
if (ctl->mixer_left)
mdss_mdp_mixer_free(ctl->mixer_left);
if (ctl->mixer_right)
mdss_mdp_mixer_free(ctl->mixer_right);
mdss_mdp_ctl_free(ctl);
mfd->ctl = NULL;
}
return ret;
}
static int mdss_mdp_ctl_destroy(struct msm_fb_data_type *mfd)
{
struct mdss_mdp_ctl *ctl;
if (!mfd || !mfd->ctl)
return -ENODEV;
ctl = mfd->ctl;
mfd->ctl = NULL;
if (ctl->mixer_left)
mdss_mdp_mixer_free(ctl->mixer_left);
if (ctl->mixer_right)
mdss_mdp_mixer_free(ctl->mixer_right);
mdss_mdp_ctl_free(ctl);
return 0;
}
int mdss_mdp_ctl_intf_event(struct mdss_mdp_ctl *ctl, int event, void *arg)
{
struct mdss_panel_data *pdata;
if (!ctl || !ctl->panel_data)
return -ENODEV;
pdata = ctl->panel_data;
pr_debug("sending ctl=%d event=%d\n", ctl->num, event);
if (pdata->event_handler)
return pdata->event_handler(pdata, event, arg);
return 0;
}
int mdss_mdp_ctl_on(struct msm_fb_data_type *mfd)
{
struct mdss_mdp_ctl *ctl;
struct mdss_mdp_mixer *mixer;
u32 outsize, temp, off;
int ret = 0;
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
if (mdss_mdp_ctl_init(mfd)) {
pr_err("unable to initialize ctl\n");
return -ENODEV;
}
ctl = mfd->ctl;
if (ctl->power_on) {
WARN(1, "already on!\n");
return 0;
}
mutex_lock(&ctl->lock);
ctl->power_on = true;
ctl->bus_ab_quota = 0;
ctl->bus_ib_quota = 0;
ctl->clk_rate = 0;
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
ret = mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_RESET, NULL);
if (ret) {
pr_err("panel power on failed ctl=%d\n", ctl->num);
goto start_fail;
}
if (ctl->start_fnc)
ret = ctl->start_fnc(ctl);
else
pr_warn("no start function for ctl=%d type=%d\n", ctl->num,
ctl->panel_data->panel_info.type);
if (ret) {
pr_err("unable to start intf\n");
goto start_fail;
}
pr_debug("ctl_num=%d\n", ctl->num);
mixer = ctl->mixer_left;
mixer->params_changed++;
temp = MDSS_MDP_REG_READ(MDSS_MDP_REG_DISP_INTF_SEL);
temp |= (ctl->intf_type << ((ctl->intf_num - MDSS_MDP_INTF0) * 8));
MDSS_MDP_REG_WRITE(MDSS_MDP_REG_DISP_INTF_SEL, temp);
if (ctl->intf_num != MDSS_MDP_NO_INTF) {
off = MDSS_MDP_REG_INTF_OFFSET(ctl->intf_num);
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_INTF_PANEL_FORMAT,
ctl->dst_format);
}
outsize = (mixer->height << 16) | mixer->width;
off = MDSS_MDP_REG_LM_OFFSET(mixer->num);
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_LM_OUT_SIZE, outsize);
if (ctl->mixer_right) {
mixer = ctl->mixer_right;
mixer->params_changed++;
outsize = (mixer->height << 16) | mixer->width;
off = MDSS_MDP_REG_LM_OFFSET(mixer->num);
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_LM_OUT_SIZE, outsize);
mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_PACK_3D, 0);
}
start_fail:
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
mutex_unlock(&ctl->lock);
if (ret)
mdss_mdp_ctl_destroy(mfd);
return ret;
}
int mdss_mdp_ctl_off(struct msm_fb_data_type *mfd)
{
struct mdss_mdp_ctl *ctl;
int ret = 0;
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
if (!mfd->ctl) {
pr_err("ctl not initialized\n");
return -ENODEV;
}
ctl = mfd->ctl;
if (!ctl->power_on) {
WARN(1, "already off!\n");
return 0;
}
pr_debug("ctl_num=%d\n", mfd->ctl->num);
mutex_lock(&ctl->lock);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
if (ctl->stop_fnc)
ret = ctl->stop_fnc(ctl);
else
pr_warn("no stop func for ctl=%d\n", ctl->num);
if (ret) {
pr_warn("error powering off intf ctl=%d\n", ctl->num);
} else {
ctl->power_on = false;
ctl->play_cnt = 0;
ctl->clk_rate = 0;
mdss_mdp_ctl_perf_commit(MDSS_MDP_PERF_UPDATE_ALL);
}
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
mutex_unlock(&ctl->lock);
if (!ret && !mfd->ref_cnt) {
ret = mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_CLOSE, NULL);
WARN(ret, "unable to close intf %d\n", ctl->intf_num);
mdss_mdp_ctl_destroy(mfd);
}
return ret;
}
static int mdss_mdp_mixer_setup(struct mdss_mdp_ctl *ctl,
struct mdss_mdp_mixer *mixer)
{
struct mdss_mdp_pipe *pipe;
u32 off, blend_op, blend_stage;
u32 mixercfg = 0, blend_color_out = 0, bgalpha = 0;
int stage;
if (!mixer)
return -ENODEV;
pr_debug("setup mixer=%d\n", mixer->num);
pipe = mixer->stage_pipe[MDSS_MDP_STAGE_BASE];
if (pipe == NULL) {
mixercfg = MDSS_MDP_LM_BORDER_COLOR;
} else {
mixercfg = 1 << (3 * pipe->num);
if (pipe->src_fmt->alpha_enable)
bgalpha = 1;
}
for (stage = MDSS_MDP_STAGE_0; stage < MDSS_MDP_MAX_STAGE; stage++) {
pipe = mixer->stage_pipe[stage];
if (pipe == NULL)
continue;
if (stage != pipe->mixer_stage) {
mixer->stage_pipe[stage] = NULL;
continue;
}
blend_stage = stage - MDSS_MDP_STAGE_0;
off = MDSS_MDP_REG_LM_OFFSET(mixer->num) +
MDSS_MDP_REG_LM_BLEND_OFFSET(blend_stage);
if (pipe->is_fg) {
bgalpha = 0;
mixercfg = MDSS_MDP_LM_BORDER_COLOR;
blend_op = (MDSS_MDP_BLEND_FG_ALPHA_FG_CONST |
MDSS_MDP_BLEND_BG_ALPHA_BG_CONST);
/* keep fg alpha */
blend_color_out |= 1 << (blend_stage + 1);
pr_debug("pnum=%d stg=%d alpha=IS_FG\n", pipe->num,
stage);
} else if (pipe->src_fmt->alpha_enable) {
bgalpha = 0;
blend_op = (MDSS_MDP_BLEND_BG_ALPHA_FG_PIXEL |
MDSS_MDP_BLEND_BG_INV_ALPHA);
/* keep fg alpha */
blend_color_out |= 1 << (blend_stage + 1);
pr_debug("pnum=%d stg=%d alpha=FG PIXEL\n", pipe->num,
stage);
} else if (bgalpha) {
blend_op = (MDSS_MDP_BLEND_BG_ALPHA_BG_PIXEL |
MDSS_MDP_BLEND_FG_ALPHA_BG_PIXEL |
MDSS_MDP_BLEND_FG_INV_ALPHA);
/* keep bg alpha */
pr_debug("pnum=%d stg=%d alpha=BG_PIXEL\n", pipe->num,
stage);
} else {
blend_op = (MDSS_MDP_BLEND_FG_ALPHA_FG_CONST |
MDSS_MDP_BLEND_BG_ALPHA_BG_CONST);
pr_debug("pnum=%d stg=%d alpha=CONST\n", pipe->num,
stage);
}
mixercfg |= stage << (3 * pipe->num);
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_LM_OP_MODE, blend_op);
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_LM_BLEND_FG_ALPHA,
pipe->alpha);
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_LM_BLEND_BG_ALPHA,
0xFF - pipe->alpha);
}
if (mixer->cursor_enabled)
mixercfg |= MDSS_MDP_LM_CURSOR_OUT;
pr_debug("mixer=%d mixer_cfg=%x\n", mixer->num, mixercfg);
ctl->flush_bits |= BIT(6) << mixer->num; /* LAYER_MIXER */
off = MDSS_MDP_REG_LM_OFFSET(mixer->num);
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_LM_OP_MODE, blend_color_out);
mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_LAYER(mixer->num), mixercfg);
return 0;
}
struct mdss_mdp_mixer *mdss_mdp_mixer_get(struct mdss_mdp_ctl *ctl, int mux)
{
struct mdss_mdp_mixer *mixer = NULL;
if (!ctl)
return NULL;
switch (mux) {
case MDSS_MDP_MIXER_MUX_DEFAULT:
case MDSS_MDP_MIXER_MUX_LEFT:
mixer = ctl->mixer_left;
break;
case MDSS_MDP_MIXER_MUX_RIGHT:
mixer = ctl->mixer_right;
break;
}
return mixer;
}
struct mdss_mdp_pipe *mdss_mdp_mixer_stage_pipe(struct mdss_mdp_ctl *ctl,
int mux, int stage)
{
struct mdss_mdp_pipe *pipe = NULL;
struct mdss_mdp_mixer *mixer;
if (!ctl)
return NULL;
if (mutex_lock_interruptible(&ctl->lock))
return NULL;
mixer = mdss_mdp_mixer_get(ctl, mux);
if (mixer)
pipe = mixer->stage_pipe[stage];
mutex_unlock(&ctl->lock);
return pipe;
}
int mdss_mdp_mixer_pipe_update(struct mdss_mdp_pipe *pipe, int params_changed)
{
struct mdss_mdp_ctl *ctl;
struct mdss_mdp_mixer *mixer;
if (!pipe)
return -EINVAL;
mixer = pipe->mixer;
if (!mixer)
return -EINVAL;
ctl = mixer->ctl;
if (!ctl)
return -EINVAL;
if (pipe->mixer_stage >= MDSS_MDP_MAX_STAGE) {
pr_err("invalid mixer stage\n");
return -EINVAL;
}
pr_debug("pnum=%x mixer=%d stage=%d\n", pipe->num, mixer->num,
pipe->mixer_stage);
if (mutex_lock_interruptible(&ctl->lock))
return -EINTR;
if (params_changed) {
mixer->params_changed++;
mixer->stage_pipe[pipe->mixer_stage] = pipe;
}
if (pipe->type == MDSS_MDP_PIPE_TYPE_DMA)
ctl->flush_bits |= BIT(pipe->num) << 5;
else /* RGB/VIG pipe */
ctl->flush_bits |= BIT(pipe->num);
mutex_unlock(&ctl->lock);
return 0;
}
int mdss_mdp_mixer_pipe_unstage(struct mdss_mdp_pipe *pipe)
{
struct mdss_mdp_ctl *ctl;
struct mdss_mdp_mixer *mixer;
if (!pipe)
return -EINVAL;
mixer = pipe->mixer;
if (!mixer)
return -EINVAL;
ctl = mixer->ctl;
if (!ctl)
return -EINVAL;
pr_debug("unstage pnum=%d stage=%d mixer=%d\n", pipe->num,
pipe->mixer_stage, mixer->num);
if (mutex_lock_interruptible(&ctl->lock))
return -EINTR;
mixer->params_changed++;
mixer->stage_pipe[pipe->mixer_stage] = NULL;
mutex_unlock(&ctl->lock);
return 0;
}
static int mdss_mdp_mixer_update(struct mdss_mdp_mixer *mixer)
{
mixer->params_changed = 0;
/* skip mixer setup for rotator */
if (!mixer->rotator_mode)
mdss_mdp_mixer_setup(mixer->ctl, mixer);
return 0;
}
static struct msm_panel_common_pdata *mdss_mdp_populate_pdata(
struct device *dev)
{
struct msm_panel_common_pdata *pdata;
struct msm_iova_layout layout;
struct iommu_domain *domain;
struct mdss_iommu_map_type *iomap;
int i;
if (mdata->iommu_map) {
pr_warn("iommu already initialized\n");
return 0;
}
for (i = 0; i < MDSS_IOMMU_MAX_DOMAIN; i++) {
iomap = &mdss_iommu_map[i];
layout.client_name = iomap->client_name;
layout.partitions = iomap->partitions;
layout.npartitions = iomap->npartitions;
layout.is_secure = (i == MDSS_IOMMU_DOMAIN_SECURE);
iomap->domain_idx = msm_register_domain(&layout);
if (IS_ERR_VALUE(iomap->domain_idx))
return -EINVAL;
domain = msm_get_iommu_domain(iomap->domain_idx);
if (!domain) {
pr_err("unable to get iommu domain(%d)\n",
iomap->domain_idx);
return -EINVAL;
}
iommu_set_fault_handler(domain, mdss_iommu_fault_handler, NULL);
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
dev_err(dev, "could not allocate memory for pdata\n");
return pdata;
}
static u32 mdss_mdp_res_init(struct platform_device *pdev)
{
u32 rc;
rc = mdss_mdp_irq_clk_setup(pdev);
if (rc)
return rc;
mdss_res->clk_ctrl_wq = create_singlethread_workqueue("mdp_clk_wq");
INIT_DELAYED_WORK(&mdss_res->clk_ctrl_worker,
mdss_mdp_clk_ctrl_workqueue_handler);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
mdss_res->rev = MDSS_MDP_REG_READ(MDSS_REG_HW_VERSION);
mdss_res->mdp_rev = MDSS_MDP_REG_READ(MDSS_MDP_REG_HW_VERSION);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
mdss_res->smp_mb_cnt = MDSS_MDP_SMP_MMB_BLOCKS;
mdss_res->smp_mb_size = MDSS_MDP_SMP_MMB_SIZE;
mdss_res->pipe_type_map = mdss_mdp_pipe_type_map;
mdss_res->mixer_type_map = mdss_mdp_mixer_type_map;
pr_info("mdss_revision=%x\n", mdss_res->rev);
pr_info("mdp_hw_revision=%x\n", mdss_res->mdp_rev);
mdss_res->res_init = true;
mdss_res->timeout = HZ/20;
mdss_res->clk_ena = false;
mdss_res->irq_mask = MDSS_MDP_DEFAULT_INTR_MASK;
mdss_res->suspend = false;
mdss_res->prim_ptype = NO_PANEL;
mdss_res->irq_ena = false;
return 0;
}
static int mdss_mdp_hw_cursor_update(struct msm_fb_data_type *mfd,
struct fb_cursor *cursor)
{
struct mdss_mdp_mixer *mixer;
struct fb_image *img = &cursor->image;
u32 blendcfg;
int off, ret = 0;
if (!mfd->cursor_buf) {
mfd->cursor_buf = dma_alloc_coherent(NULL, MDSS_MDP_CURSOR_SIZE,
(dma_addr_t *) &mfd->cursor_buf_phys,
GFP_KERNEL);
if (!mfd->cursor_buf) {
pr_err("can't allocate cursor buffer\n");
return -ENOMEM;
}
}
mixer = mdss_mdp_mixer_get(mfd->ctl, MDSS_MDP_MIXER_MUX_DEFAULT);
off = MDSS_MDP_REG_LM_OFFSET(mixer->num);
if ((img->width > MDSS_MDP_CURSOR_WIDTH) ||
(img->height > MDSS_MDP_CURSOR_HEIGHT) ||
(img->depth != 32))
return -EINVAL;
pr_debug("mixer=%d enable=%x set=%x\n", mixer->num, cursor->enable,
cursor->set);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
blendcfg = MDSS_MDP_REG_READ(off + MDSS_MDP_REG_LM_CURSOR_BLEND_CONFIG);
if (cursor->set & FB_CUR_SETPOS)
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_LM_CURSOR_START_XY,
(img->dy << 16) | img->dx);
if (cursor->set & FB_CUR_SETIMAGE) {
int calpha_en, transp_en, alpha, size;
ret = copy_from_user(mfd->cursor_buf, img->data,
img->width * img->height * 4);
if (ret)
return ret;
if (img->bg_color == 0xffffffff)
transp_en = 0;
else
transp_en = 1;
alpha = (img->fg_color & 0xff000000) >> 24;
if (alpha)
calpha_en = 0x0; /* xrgb */
else
calpha_en = 0x2; /* argb */
size = (img->height << 16) | img->width;
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_LM_CURSOR_IMG_SIZE, size);
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_LM_CURSOR_SIZE, size);
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_LM_CURSOR_STRIDE,
img->width * 4);
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_LM_CURSOR_BASE_ADDR,
mfd->cursor_buf_phys);
wmb();
blendcfg &= ~0x1;
blendcfg |= (transp_en << 3) | (calpha_en << 1);
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_LM_CURSOR_BLEND_CONFIG,
blendcfg);
if (calpha_en)
MDSS_MDP_REG_WRITE(off +
MDSS_MDP_REG_LM_CURSOR_BLEND_PARAM,
alpha);
if (transp_en) {
MDSS_MDP_REG_WRITE(off +
MDSS_MDP_REG_LM_CURSOR_BLEND_TRANSP_LOW0,
((img->bg_color & 0xff00) << 8) |
(img->bg_color & 0xff));
MDSS_MDP_REG_WRITE(off +
MDSS_MDP_REG_LM_CURSOR_BLEND_TRANSP_LOW1,
((img->bg_color & 0xff0000) >> 16));
MDSS_MDP_REG_WRITE(off +
MDSS_MDP_REG_LM_CURSOR_BLEND_TRANSP_HIGH0,
((img->bg_color & 0xff00) << 8) |
(img->bg_color & 0xff));
MDSS_MDP_REG_WRITE(off +
MDSS_MDP_REG_LM_CURSOR_BLEND_TRANSP_HIGH1,
((img->bg_color & 0xff0000) >> 16));
}
}
irqreturn_t mdss_mdp_isr(int irq, void *ptr)
{
u32 isr, mask, hist_isr, hist_mask;
isr = MDSS_MDP_REG_READ(MDSS_MDP_REG_INTR_STATUS);
if (isr == 0)
goto mdp_isr_done;
mask = MDSS_MDP_REG_READ(MDSS_MDP_REG_INTR_EN);
MDSS_MDP_REG_WRITE(MDSS_MDP_REG_INTR_CLEAR, isr);
pr_debug("%s: isr=%x mask=%x\n", __func__, isr, mask);
isr &= mask;
if (isr == 0)
goto mdp_isr_done;
if (isr & MDSS_MDP_INTR_INTF_0_UNDERRUN)
mdss_mdp_intr_done(MDP_INTR_UNDERRUN_INTF_0);
if (isr & MDSS_MDP_INTR_INTF_1_UNDERRUN)
mdss_mdp_intr_done(MDP_INTR_UNDERRUN_INTF_1);
if (isr & MDSS_MDP_INTR_INTF_2_UNDERRUN)
mdss_mdp_intr_done(MDP_INTR_UNDERRUN_INTF_2);
if (isr & MDSS_MDP_INTR_INTF_3_UNDERRUN)
mdss_mdp_intr_done(MDP_INTR_UNDERRUN_INTF_3);
if (isr & MDSS_MDP_INTR_PING_PONG_0_DONE)
mdss_mdp_intr_done(MDP_INTR_PING_PONG_0);
if (isr & MDSS_MDP_INTR_PING_PONG_1_DONE)
mdss_mdp_intr_done(MDP_INTR_PING_PONG_1);
if (isr & MDSS_MDP_INTR_PING_PONG_2_DONE)
mdss_mdp_intr_done(MDP_INTR_PING_PONG_2);
if (isr & MDSS_MDP_INTR_PING_PONG_0_RD_PTR)
mdss_mdp_intr_done(MDP_INTR_PING_PONG_0_RD_PTR);
if (isr & MDSS_MDP_INTR_PING_PONG_1_RD_PTR)
mdss_mdp_intr_done(MDP_INTR_PING_PONG_1_RD_PTR);
if (isr & MDSS_MDP_INTR_PING_PONG_2_RD_PTR)
mdss_mdp_intr_done(MDP_INTR_PING_PONG_2_RD_PTR);
if (isr & MDSS_MDP_INTR_INTF_0_VSYNC)
mdss_mdp_intr_done(MDP_INTR_VSYNC_INTF_0);
if (isr & MDSS_MDP_INTR_INTF_1_VSYNC)
mdss_mdp_intr_done(MDP_INTR_VSYNC_INTF_1);
if (isr & MDSS_MDP_INTR_INTF_2_VSYNC)
mdss_mdp_intr_done(MDP_INTR_VSYNC_INTF_2);
if (isr & MDSS_MDP_INTR_INTF_3_VSYNC)
mdss_mdp_intr_done(MDP_INTR_VSYNC_INTF_3);
if (isr & MDSS_MDP_INTR_WB_0_DONE)
mdss_mdp_intr_done(MDP_INTR_WB_0);
if (isr & MDSS_MDP_INTR_WB_1_DONE)
mdss_mdp_intr_done(MDP_INTR_WB_1);
if (isr & MDSS_MDP_INTR_WB_2_DONE)
mdss_mdp_intr_done(MDP_INTR_WB_2);
mdp_isr_done:
hist_isr = MDSS_MDP_REG_READ(MDSS_MDP_REG_HIST_INTR_STATUS);
if (hist_isr == 0)
goto hist_isr_done;
hist_mask = MDSS_MDP_REG_READ(MDSS_MDP_REG_HIST_INTR_EN);
MDSS_MDP_REG_WRITE(MDSS_MDP_REG_HIST_INTR_CLEAR, hist_isr);
hist_isr &= hist_mask;
if (hist_isr == 0)
goto hist_isr_done;
mdss_mdp_hist_intr_done(hist_isr);
hist_isr_done:
return IRQ_HANDLED;
}
