int md_cd_let_md_go(struct ccci_modem *md)
{
struct md_cd_ctrl *md_ctrl = (struct md_cd_ctrl *)md->private_data;
if(MD_IN_DEBUG(md))
return -1;
CCCI_INF_MSG(md->index, TAG, "set MD boot slave\n");
// set the start address to let modem to run
cldma_write32(md_ctrl->md_boot_slave_Key, 0, 0x3567C766); // make boot vector programmable
cldma_write32(md_ctrl->md_boot_slave_Vector, 0, 0x00000001); // after remap, MD ROM address is 0 from MD's view, MT6595 uses Thumb code
cldma_write32(md_ctrl->md_boot_slave_En, 0, 0xA3B66175); // make boot vector take effect
return 0;
}
int md_ccif_let_md_go(struct ccci_modem *md)
{
struct md_ccif_ctrl *md_ctrl = (struct md_ccif_ctrl *)md->private_data;
if(MD_IN_DEBUG(md))
{
CCCI_INF_MSG(md->index, TAG, "DBG_FLAG_JTAG is set\n");
return -1;
}
CCCI_INF_MSG(md->index, TAG, "md_ccif_let_md_go\n");
// set the start address to let modem to run
ccif_write32(md_ctrl->md_boot_slave_Key, 0, MD2_BOOT_VECTOR_KEY_VALUE); // make boot vector programmable
ccif_write32(md_ctrl->md_boot_slave_Vector, 0, MD2_BOOT_VECTOR_VALUE); // after remap, MD ROM address is 0 from MD's view
ccif_write32(md_ctrl->md_boot_slave_En, 0, MD2_BOOT_VECTOR_EN_VALUE); // make boot vector take effect
return 0;
}
/*need modify according to dummy ap*/
int md_ccif_let_md_go(struct ccci_modem *md)
{
struct md_ccif_ctrl *md_ctrl = (struct md_ccif_ctrl *)md->private_data;
if (MD_IN_DEBUG(md)) {
CCCI_INF_MSG(md->index, TAG, "DBG_FLAG_JTAG is set\n");
return -1;
}
CCCI_INF_MSG(md->index, TAG, "md_ccif_let_md_go\n");
switch (md->index) {
case MD_SYS2:
/*set the start address to let modem to run */
/*make boot vector programmable */
ccif_write32(md_ctrl->md_boot_slave_Key, 0, MD2_BOOT_VECTOR_KEY_VALUE);
/*after remap, MD ROM address is 0 from MD's view */
ccif_write32(md_ctrl->md_boot_slave_Vector, 0, MD2_BOOT_VECTOR_VALUE);
/*make boot vector take effect */
ccif_write32(md_ctrl->md_boot_slave_En, 0, MD2_BOOT_VECTOR_EN_VALUE);
break;
case MD_SYS3:
/*check if meta mode */
if (is_meta_mode() || get_boot_mode() == FACTORY_BOOT) {
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG,
(ccif_read32
(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG) | ETS_SEL_BIT));
}
/*step 1: set C2K boot mode */
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG,
(ccif_read32
(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG) & (~(0x7 << 8))) | (0x5 <<
8));
CCCI_INF_MSG(md->index, TAG, "C2K_CONFIG = 0x%x\n",
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG));
/*step 2: config srcclkena selection mask */
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL,
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL) & (~(0x3 <<
4)));
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL,
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL) | (0x2 << 4));
CCCI_INF_MSG(md->index, TAG, "C2K_SPM_CTRL = 0x%x\n",
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL));
ccif_write32(md_ctrl->hw_info->sleep_base, SLEEP_CLK_CON,
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON) | 0xc);
ccif_write32(md_ctrl->hw_info->sleep_base, SLEEP_CLK_CON,
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON) & (~(0x1 << 14)));
ccif_write32(md_ctrl->hw_info->sleep_base, SLEEP_CLK_CON,
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON) | (0x1 << 12));
ccif_write32(md_ctrl->hw_info->sleep_base, SLEEP_CLK_CON,
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON) | (0x1 << 27));
CCCI_INF_MSG(md->index, TAG, "SLEEP_CLK_CON = 0x%x\n",
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON));
/*step 3: PMIC VTCXO_1 enable */
pmic_config_interface(0x0A02, 0xA12E, 0xFFFF, 0x0);
/*step 4: reset C2K */
#if 0
ccif_write32(md_ctrl->hw_info->toprgu_base,
TOP_RGU_WDT_SWSYSRST,
(ccif_read32
(md_ctrl->hw_info->toprgu_base,
TOP_RGU_WDT_SWSYSRST) | 0x88000000) & (~(0x1 <<
15)));
#else
mtk_wdt_set_c2k_sysrst(1);
#endif
CCCI_INF_MSG(md->index, TAG,
"[C2K] TOP_RGU_WDT_SWSYSRST = 0x%x\n",
ccif_read32(md_ctrl->hw_info->toprgu_base,
TOP_RGU_WDT_SWSYSRST));
/*step 5: mpu already set */
/*step 6: wake up C2K */
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL,
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL) | 0x1);
while (!
((ccif_read32
(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_STATUS) >> 1) & 0x1)) {
CCCI_INF_MSG(md->index, TAG,
"[C2K] C2K_STATUS = 0x%x\n",
ccif_read32(md_ctrl->hw_info->
infra_ao_base,
INFRA_AO_C2K_STATUS));
}
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL,
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL) & (~0x1));
CCCI_INF_MSG(md->index, TAG,
"[C2K] C2K_SPM_CTRL = 0x%x, C2K_STATUS = 0x%x\n",
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL),
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_STATUS));
break;
}
return 0;
}