static void
gxpcic_socket_setup(struct pxapcic_socket *so)
{
#if 0
struct pxapcic_softc *sc = so->sc;
#endif
/* 3.3V only? */
so->power_capability = PXAPCIC_POWER_3V;
so->pcictag_cookie = NULL;
so->pcictag = &gxpcic_functions;
#if 0 /* We use already set values by u-boot. */
bus_space_write_4(sc->sc_iot, sc->sc_memctl_ioh,
MEMCTL_MCMEM(so->socket), MC_TIMING_VAL(9 ,9, 29));
bus_space_write_4(sc->sc_iot, sc->sc_memctl_ioh,
MEMCTL_MCATT(so->socket), MC_TIMING_VAL(9 ,9, 29));
bus_space_write_4(sc->sc_iot, sc->sc_memctl_ioh,
MEMCTL_MCIO(so->socket), MC_TIMING_VAL(5 ,5, 16));
#endif
}
void
pxa2x0_apm_sleep(struct pxa2x0_apm_softc *sc)
{
struct pxa2x0_sleep_data sd;
bus_space_handle_t ost_ioh;
int save;
u_int32_t rv;
ost_ioh = (bus_space_handle_t)0;
if (bus_space_map(sc->sc_iot, PXA2X0_OST_BASE, PXA2X0_OST_SIZE, 0,
&ost_ioh)) {
printf("pxa2x0_apm_sleep: can't map OST\n");
goto out;
}
save = disable_interrupts(I32_bit|F32_bit);
sd.sd_oscr0 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSCR0);
sd.sd_oscr4 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSCR4);
sd.sd_omcr4 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OMCR4);
sd.sd_omcr5 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OMCR5);
sd.sd_osmr0 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR0);
sd.sd_osmr1 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR1);
sd.sd_osmr2 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR2);
sd.sd_osmr3 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR3);
sd.sd_osmr4 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR4);
sd.sd_osmr5 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR5);
sd.sd_oier = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OIER);
/* Bring the PXA27x into 416MHz turbo mode. */
if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA27X &&
bus_space_read_4(sc->sc_iot, pxa2x0_clkman_ioh, CLKMAN_CCCR) !=
(CCCR_A | CCCR_TURBO_X2 | CCCR_RUN_X16)) {
#if 0
pxa27x_cpu_speed_high();
#else
#define CLKCFG_T (1<<0) /* turbo */
#define CLKCFG_F (1<<1) /* frequency change */
#define CLKCFG_B (1<<3) /* fast-bus */
pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X2 |
CCCR_RUN_X16, CLKCFG_B | CLKCFG_F | CLKCFG_T,
&pxa2x0_memcfg);
#endif
delay(500000); /* XXX */
}
suspend_again:
/* Clear wake-up status. */
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PEDR,
0xffffffff);
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PKSR,
0xffffffff);
/* XXX control battery charging in sleep mode. */
/* XXX schedule RTC alarm to check the battery, or schedule
XXX wake-up shortly before an already programmed alarm? */
pxa27x_run_mode();
#define MDREFR_LOW (MDREFR_C3000 | 0x00b)
pxa27x_fastbus_run_mode(0, MDREFR_LOW);
delay(1);
#if 1
pxa27x_cpu_speed_91();
#else
pxa27x_frequency_change(CCCR_TURBO_X1 | CCCR_RUN_X7, CLKCFG_F,
&pxa2x0_memcfg);
#endif
pxa2x0_pi2c_setvoltage(sc->sc_iot, sc->sc_pm_ioh, PI2C_VOLTAGE_LOW);
sd.sd_gpdr0 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR0);
sd.sd_gpdr1 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR1);
sd.sd_gpdr2 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR2);
sd.sd_gpdr3 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR3);
sd.sd_grer0 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER0);
sd.sd_grer1 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER1);
sd.sd_grer2 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER2);
sd.sd_grer3 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER3);
sd.sd_gfer0 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER0);
sd.sd_gfer1 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER1);
sd.sd_gfer2 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER2);
sd.sd_gfer3 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER3);
sd.sd_gafr0_l = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR0_L);
sd.sd_gafr1_l = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR1_L);
sd.sd_gafr2_l = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR2_L);
sd.sd_gafr3_l = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR3_L);
sd.sd_gafr0_u = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR0_U);
sd.sd_gafr1_u = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR1_U);
sd.sd_gafr2_u = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR2_U);
sd.sd_gafr3_u = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR3_U);
sd.sd_gplr0 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPLR0);
sd.sd_gplr1 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPLR1);
sd.sd_gplr2 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPLR2);
sd.sd_gplr3 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPLR3);
sd.sd_iclr = read_icu(INTCTL_ICLR);
sd.sd_icmr = read_icu(INTCTL_ICMR);
sd.sd_iccr = read_icu(INTCTL_ICCR);
write_icu(INTCTL_ICMR, 0);
sd.sd_mecr = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh,
MEMCTL_MECR);
sd.sd_mcmem0 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh,
MEMCTL_MCMEM(0));
sd.sd_mcmem1 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh,
MEMCTL_MCMEM(1));
sd.sd_mcatt0 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh,
MEMCTL_MCATT(0));
sd.sd_mcatt1 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh,
MEMCTL_MCATT(1));
sd.sd_mcio0 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh,
MEMCTL_MCIO(0));
sd.sd_mcio1 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh,
MEMCTL_MCIO(1));
sd.sd_cken = bus_space_read_4(sc->sc_iot, pxa2x0_clkman_ioh,
CLKMAN_CKEN);
/*
* Stop clocks to all units except to the memory controller, and
* to the keypad controller if it is enabled as a wake-up source.
*/
rv = CKEN_MEM;
if ((sc->sc_wakeon & PXA2X0_WAKEUP_KEYNS_ALL) != 0)
rv |= CKEN_KEY;
bus_space_write_4(sc->sc_iot, pxa2x0_clkman_ioh, CLKMAN_CKEN, rv);
/* Disable nRESET_OUT. */
rv = bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PSLR);
#define PSLR_SL_ROD (1<<20)
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PSLR,
rv | PSLR_SL_ROD);
/* Clear all reset status flags. */
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_RCSR,
RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR);
/* Stop 3/13MHz oscillator; do not float PCMCIA and chip-selects. */
rv = PCFR_OPDE;
if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA27X)
/* Enable nRESET_GPIO as a GPIO reset input. */
rv |= PCFR_GPR_EN;
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PCFR, rv);
/* XXX C3000 */
#define GPIO_G0_STROBE_BIT 0x0f800000
#define GPIO_G1_STROBE_BIT 0x00100000
#define GPIO_G2_STROBE_BIT 0x01000000
#define GPIO_G3_STROBE_BIT 0x00041880
#define GPIO_KEY_STROBE0 88
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR0,
0x00144018);
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR1,
0x00ef0000);
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR2,
0x0121c000);
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR3,
0x00600000);
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR0,
0x00144018 & ~GPIO_G0_STROBE_BIT);
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR1,
0x00ef0000 & ~GPIO_G1_STROBE_BIT);
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR2,
0x0121c000 & ~GPIO_G2_STROBE_BIT);
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR3,
0x00600000 & ~GPIO_G3_STROBE_BIT);
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR2,
(0x0121c000 & ~GPIO_G2_STROBE_BIT) |
GPIO_BIT(GPIO_KEY_STROBE0));
/* C3000 */
#define GPIO_EXT_BUS_READY 18
pxa2x0_gpio_set_function(GPIO_EXT_BUS_READY, GPIO_SET | GPIO_OUT);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR0, 0xd01c4418);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR1, 0xfcefbd21);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR2, 0x13a5ffff);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR3, 0x01e3e10c);
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PSPR,
(u_int32_t)&pxa2x0_cpu_resume - 0xc0200000 + 0xa0200000);
pxa2x0_cpu_suspend();
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PSPR, 0);
pxa2x0_clkman_config(CKEN_SSP|CKEN_PWM0|CKEN_PWM1, 1);
pxa2x0_clkman_config(CKEN_KEY, 0);
#if 1
/* Clear all GPIO interrupt sources. */
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GEDR0, 0xffffffff);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GEDR1, 0xffffffff);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GEDR2, 0xffffffff);
#endif
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR0, sd.sd_gpdr0);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR1, sd.sd_gpdr1);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR2, sd.sd_gpdr2);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER0, sd.sd_grer0);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER1, sd.sd_grer1);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER2, sd.sd_grer2);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER0, sd.sd_gfer0);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER1, sd.sd_gfer1);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER2, sd.sd_gfer2);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR0_L, sd.sd_gafr0_l);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR1_L, sd.sd_gafr1_l);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR2_L, sd.sd_gafr2_l);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR0_U, sd.sd_gafr0_u);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR1_U, sd.sd_gafr1_u);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR2_U, sd.sd_gafr2_u);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPSR0, sd.sd_gplr0 &
sd.sd_gpdr0);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPSR1, sd.sd_gplr1 &
sd.sd_gpdr1);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPSR2, sd.sd_gplr2 &
sd.sd_gpdr2);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPCR0, ~sd.sd_gplr0 &
sd.sd_gpdr0);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPCR1, ~sd.sd_gplr1 &
sd.sd_gpdr1);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPCR2, ~sd.sd_gplr2 &
sd.sd_gpdr2);
/* PXA27x */
#if 0
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GEDR3, 0xffffffff);
#endif
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR3, sd.sd_gpdr3);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER3, sd.sd_grer3);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER3, sd.sd_gfer3);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR3_L, sd.sd_gafr3_l);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR3_U, sd.sd_gafr3_u);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPSR3, sd.sd_gplr3 &
sd.sd_gpdr3);
bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPCR3, ~sd.sd_gplr3 &
sd.sd_gpdr3);
bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MECR,
sd.sd_mecr);
bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCMEM(0),
sd.sd_mcmem0);
bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCMEM(1),
sd.sd_mcmem1);
bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCATT(0),
sd.sd_mcatt0);
bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCATT(1),
sd.sd_mcatt1);
bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCIO(0),
sd.sd_mcio0);
bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCIO(1),
sd.sd_mcio1);
bus_space_write_4(sc->sc_iot, pxa2x0_clkman_ioh, CLKMAN_CKEN,
sd.sd_cken);
write_icu(INTCTL_ICLR, sd.sd_iclr);
write_icu(INTCTL_ICCR, sd.sd_iccr);
write_icu(INTCTL_ICMR, sd.sd_icmr);
if ((read_icu(INTCTL_ICIP) & 0x1) != 0)
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PEDR, 0x1);
bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSMR0, sd.sd_osmr0);
bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSMR1, sd.sd_osmr1);
bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSMR2, sd.sd_osmr2);
bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSMR3, sd.sd_osmr3);
bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSMR4, sd.sd_osmr4);
bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSMR5, sd.sd_osmr5);
bus_space_write_4(sc->sc_iot, ost_ioh, OST_OMCR4, sd.sd_omcr4);
bus_space_write_4(sc->sc_iot, ost_ioh, OST_OMCR5, sd.sd_omcr5);
bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSCR0, sd.sd_oscr0);
bus_space_write_4(sc->sc_iot, ost_ioh, OST_OSCR4, sd.sd_oscr4);
bus_space_write_4(sc->sc_iot, ost_ioh, OST_OIER, sd.sd_oier);
pxa2x0_pi2c_setvoltage(sc->sc_iot, sc->sc_pm_ioh, PI2C_VOLTAGE_HIGH);
/* Change to 208MHz run mode with fast-bus still disabled. */
pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X2 | CCCR_RUN_X16,
CLKCFG_F, &pxa2x0_memcfg);
delay(1); /* XXX is the delay long enough, and necessary at all? */
pxa27x_fastbus_run_mode(1, pxa2x0_memcfg.mdrefr_high);
/* Change to 416MHz turbo mode with fast-bus enabled. */
pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X2 | CCCR_RUN_X16,
CLKCFG_B | CLKCFG_F | CLKCFG_T, &pxa2x0_memcfg);
if (sc->sc_resume != NULL) {
if (!sc->sc_resume(sc))
goto suspend_again;
}
/*
* Allow immediate entry into deep-sleep mode if power fails.
* Resume from immediate deep-sleep is not implemented yet.
*/
bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PMCR, 0);
restore_interrupts(save);
pxa2x0_setperf(perflevel);
out:
if (ost_ioh != (bus_space_handle_t)0)
bus_space_unmap(sc->sc_iot, ost_ioh, PXA2X0_OST_SIZE);
}
