void Dis_FPU2op(MIPSOpcode op, char *out)
{
int fs = _FS;
int fd = _FD;
const char *name = MIPSGetName(op);
sprintf(out, "%s\t%s, %s",name,FN(fd),FN(fs));
}
void Dis_Cache(MIPSOpcode op, char *out)
{
int imm = (s16)(op & 0xFFFF);
int rs = _RS;
int func = (op >> 16) & 0x1F;
sprintf(out, "%s\tfunc=%i, %s(%s)", MIPSGetName(op), func, RN(rs), SignedHex(imm));
}
void Dis_mxc1(MIPSOpcode op, char *out)
{
int fs = _FS;
int rt = _RT;
const char *name = MIPSGetName(op);
sprintf(out, "%s\t%s, %s",name,RN(rt),FN(fs));
}
void Dis_FPUComp(MIPSOpcode op, char *out)
{
int fs = _FS;
int ft = _FT;
const char *name = MIPSGetName(op);
sprintf(out, "%s\t%s, %s",name,FN(fs),FN(ft));
}
static void JitLogMiss(MIPSOpcode op)
{
if (USE_JIT_MISSMAP)
notJitOps[MIPSGetName(op)]++;
MIPSInterpretFunc func = MIPSGetInterpretFunc(op);
func(op);
}
void Dis_FPULS(MIPSOpcode op, char *out)
{
int offset = (signed short)(op&0xFFFF);
int ft = _FT;
int rs = _RS;
const char *name = MIPSGetName(op);
sprintf(out, "%s\t%s, %s(%s)",name,FN(ft),SignedHex(offset),RN(rs));
}
void Dis_FPUBranch(MIPSOpcode op, char *out)
{
u32 off = disPC;
int imm = (signed short)(op&0xFFFF)<<2;
off += imm + 4;
const char *name = MIPSGetName(op);
sprintf(out, "%s\t->$%08x",name,off);
}
void Dis_FPULS(u32 op, char *out)
{
int offset = (signed short)(op&0xFFFF);
int ft = _FT;
int rs = _RS;
const char *name = MIPSGetName(op);
sprintf(out, "%s\t%s, %d(%s)",name,FN(ft),offset,RN(rs));
}
void Dis_FPU3op(u32 op, char *out)
{
int ft = _FT;
int fs = _FS;
int fd = _FD;;
const char *name = MIPSGetName(op);
sprintf(out, "%s\t%s, %s, %s",name,FN(fd),FN(fs),FN(ft));
}
void Dis_RelBranch(MIPSOpcode op, char *out)
{
u32 off = disPC;
int imm = (signed short)(op&0xFFFF)<<2;
int rs = _RS;
off += imm + 4;
const char *name = MIPSGetName(op);
sprintf(out, "%s\t%s, ->$%08x",name,RN(rs),off);
}
void DisassemblyFunction::load()
{
generateBranchLines();
// gather all branch targets
std::set<u32> branchTargets;
for (size_t i = 0; i < lines.size(); i++)
{
switch (lines[i].type)
{
case LINE_DOWN:
branchTargets.insert(lines[i].second);
break;
case LINE_UP:
branchTargets.insert(lines[i].first);
break;
default:
break;
}
}
DebugInterface* cpu = DisassemblyManager::getCpu();
u32 funcPos = address;
u32 funcEnd = address+size;
u32 nextData = symbolMap.GetNextSymbolAddress(funcPos-1,ST_DATA);
u32 opcodeSequenceStart = funcPos;
while (funcPos < funcEnd)
{
if (funcPos == nextData)
{
if (opcodeSequenceStart != funcPos)
addOpcodeSequence(opcodeSequenceStart,funcPos);
DisassemblyData* data = new DisassemblyData(funcPos,symbolMap.GetDataSize(funcPos),symbolMap.GetDataType(funcPos));
entries[funcPos] = data;
lineAddresses.push_back(funcPos);
funcPos += data->getTotalSize();
nextData = symbolMap.GetNextSymbolAddress(funcPos-1,ST_DATA);
opcodeSequenceStart = funcPos;
continue;
}
// force align
if (funcPos % 4)
{
u32 nextPos = (funcPos+3) & ~3;
DisassemblyComment* comment = new DisassemblyComment(funcPos,nextPos-funcPos,".align","4");
entries[funcPos] = comment;
lineAddresses.push_back(funcPos);
funcPos = nextPos;
opcodeSequenceStart = funcPos;
continue;
}
MIPSAnalyst::MipsOpcodeInfo opInfo = MIPSAnalyst::GetOpcodeInfo(cpu,funcPos);
u32 opAddress = funcPos;
funcPos += 4;
// skip branches and their delay slots
if (opInfo.isBranch)
{
funcPos += 4;
continue;
}
// lui
if (MIPS_GET_OP(opInfo.encodedOpcode) == 0x0F && funcPos < funcEnd && funcPos != nextData)
{
MIPSOpcode next = Memory::Read_Instruction(funcPos);
MIPSInfo nextInfo = MIPSGetInfo(next);
u32 immediate = ((opInfo.encodedOpcode & 0xFFFF) << 16) + (s16)(next.encoding & 0xFFFF);
int rt = MIPS_GET_RT(opInfo.encodedOpcode);
int nextRs = MIPS_GET_RS(next.encoding);
int nextRt = MIPS_GET_RT(next.encoding);
// both rs and rt of the second op have to match rt of the first,
// otherwise there may be hidden consequences if the macro is displayed.
// also, don't create a macro if something branches into the middle of it
if (nextRs == rt && nextRt == rt && branchTargets.find(funcPos) == branchTargets.end())
{
DisassemblyMacro* macro = NULL;
switch (MIPS_GET_OP(next.encoding))
{
case 0x09: // addiu
macro = new DisassemblyMacro(opAddress);
macro->setMacroLi(immediate,rt);
funcPos += 4;
break;
case 0x20: // lb
case 0x21: // lh
case 0x23: // lw
case 0x24: // lbu
case 0x25: // lhu
case 0x28: // sb
case 0x29: // sh
case 0x2B: // sw
macro = new DisassemblyMacro(opAddress);
int dataSize;
switch (nextInfo & MEMTYPE_MASK) {
case MEMTYPE_BYTE:
dataSize = 1;
break;
case MEMTYPE_HWORD:
dataSize = 2;
break;
case MEMTYPE_WORD:
case MEMTYPE_FLOAT:
dataSize = 4;
break;
case MEMTYPE_VQUAD:
dataSize = 16;
break;
default:
return;
}
macro->setMacroMemory(MIPSGetName(next),immediate,rt,dataSize);
funcPos += 4;
break;
}
if (macro != NULL)
{
if (opcodeSequenceStart != opAddress)
addOpcodeSequence(opcodeSequenceStart,opAddress);
entries[opAddress] = macro;
for (int i = 0; i < macro->getNumLines(); i++)
{
lineAddresses.push_back(macro->getLineAddress(i));
}
opcodeSequenceStart = funcPos;
continue;
}
}
}
// just a normal opcode
}
if (opcodeSequenceStart != funcPos)
addOpcodeSequence(opcodeSequenceStart,funcPos);
}
