static int sq_match(device_t parent, cfdata_t cf, void *aux) { struct hpc_attach_args *ha = aux; if (strcmp(ha->ha_name, cf->cf_name) == 0) { vaddr_t reset, txstat; reset = MIPS_PHYS_TO_KSEG1(ha->ha_sh + ha->ha_dmaoff + ha->hpc_regs->enetr_reset); txstat = MIPS_PHYS_TO_KSEG1(ha->ha_sh + ha->ha_devoff + (SEEQ_TXSTAT << 2)); if (platform.badaddr((void *)reset, sizeof(reset))) return 0; *(volatile uint32_t *)reset = 0x1; delay(20); *(volatile uint32_t *)reset = 0x0; if (platform.badaddr((void *)txstat, sizeof(txstat))) return 0; if ((*(volatile uint32_t *)txstat & 0xff) == TXSTAT_OLDNEW) return 1; } return 0; }
/* * Handle write-to-nonexistent-address memory errors on MIPS_INT_MASK_3. * These are reported asynchronously, due to hardware write buffering. * we can't easily figure out process context, so just panic. * * XXX drain writebuffer on contextswitch to avoid panic? */ static void dec_5100_memintr(void) { uint32_t icsr; /* read icsr and clear error */ icsr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR); icsr |= KN230_CSR_INTR_WMERR; *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR) = icsr; kn230_wbflush(); #ifdef DIAGNOSTIC printf("\nMemory interrupt\n"); #endif /* ignore errors during probes */ if (cold) return; if (icsr & KN230_CSR_INTR_WMERR) { panic("write to non-existent memory"); } else { panic("stray memory error interrupt"); } }
void dt_cninit(void) { dt_state.ds_poll = (volatile u_int *) MIPS_PHYS_TO_KSEG1(XINE_REG_INTR); dt_state.ds_data = (volatile u_int *) MIPS_PHYS_TO_KSEG1(XINE_PHYS_TC_3_START + 0x280000); }
static __inline uint8_t rtcin(uint8_t addr) { *((volatile uint8_t *) MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCADR))) = addr; return (*((volatile uint8_t *) MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCDAT)))); }
static __inline void writertc(uint8_t addr, uint8_t val) { *((volatile uint8_t *) MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCADR))) = addr; *((volatile uint8_t *) MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCDAT))) = val; }
void dec_3maxplus_init(void) { uint32_t prodtype; platform.iobus = "tcbus"; platform.bus_reset = dec_3maxplus_bus_reset; platform.cons_init = dec_3maxplus_cons_init; platform.iointr = dec_3maxplus_intr; platform.intr_establish = dec_3maxplus_intr_establish; platform.memsize = memsize_bitmap; /* 3MAX+ has IOASIC free-running high resolution timer */ platform.tc_init = dec_3maxplus_tc_init; /* clear any memory errors */ *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0; kn03_wbflush(); ioasic_base = MIPS_PHYS_TO_KSEG1(KN03_SYS_ASIC); ipl_sr_map = dec_3maxplus_ipl_sr_map; /* calibrate cpu_mhz value */ mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_1); *(volatile uint32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; *(volatile uint32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; #if 0 *(volatile uint32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); *(volatile uint32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); *(volatile uint32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; #endif /* XXX hard-reset LANCE */ *(volatile uint32_t *)(ioasic_base + IOASIC_CSR) |= 0x100; /* sanitize interrupt mask */ kn03_tc3_imask = KN03_INTR_PSWARN; *(volatile uint32_t *)(ioasic_base + IOASIC_INTR) = 0; *(volatile uint32_t *)(ioasic_base + IOASIC_IMSK) = kn03_tc3_imask; kn03_wbflush(); prodtype = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_REG_INTR); prodtype &= KN03_INTR_PROD_JUMPER; /* the bit persists even if INTR register is assigned value 0 */ if (prodtype) cpu_setmodel("DECstation 5000/%s (3MAXPLUS)", (CPUISMIPS3) ? "260" : "240"); else cpu_setmodel("DECsystem 5900%s (3MAXPLUS)", (CPUISMIPS3) ? "-260" : ""); }
/* * Initialize the memory system and I/O buses. */ static void dec_5100_bus_reset(void) { uint32_t icsr; /* clear any memory error condition */ icsr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR); icsr |= KN230_CSR_INTR_WMERR; *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR) = icsr; /* nothing else to do */ kn230_wbflush(); }
static struct resource * iodi_alloc_resource(device_t bus, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct resource *res = malloc(sizeof(*res), M_DEVBUF, M_WAITOK); const char *name = device_get_name(child); int unit; #ifdef DEBUG switch (type) { case SYS_RES_IRQ: device_printf(bus, "IRQ resource - for %s %lx-%lx\n", device_get_nameunit(child), start, end); break; case SYS_RES_IOPORT: device_printf(bus, "IOPORT resource - for %s %lx-%lx\n", device_get_nameunit(child), start, end); break; case SYS_RES_MEMORY: device_printf(bus, "MEMORY resource - for %s %lx-%lx\n", device_get_nameunit(child), start, end); break; } #endif if (strcmp(name, "uart") == 0) { if ((unit = device_get_unit(child)) == 0) { /* uart 0 */ res->r_bushandle = (xlr_io_base + XLR_IO_UART_0_OFFSET); } else if (unit == 1) { res->r_bushandle = (xlr_io_base + XLR_IO_UART_1_OFFSET); } else printf("%s: Unknown uart unit\n", __FUNCTION__); res->r_bustag = uart_bus_space_mem; } else if (strcmp(name, "ehci") == 0) { res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1ef24000); res->r_bustag = rmi_pci_bus_space; } else if (strcmp(name, "cfi") == 0) { res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1c000000); res->r_bustag = 0; } else if (strcmp(name, "ata") == 0) { res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1d000000); res->r_bustag = rmi_pci_bus_space; /* byte swapping (not really PCI) */ } /* res->r_start = *rid; */ return (res); }
static int uart_iodi_probe(device_t dev) { struct uart_softc *sc; sc = device_get_softc(dev); sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); sc->sc_class = &uart_ns8250_class; bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); sc->sc_sysdev->bas.bst = rmi_bus_space; sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR); sc->sc_bas.bst = rmi_bus_space; sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR); /* regshft = 2, rclk = 66000000, rid = 0, chan = 0 */ return (uart_bus_probe(dev, 2, 66000000, 0, 0)); }
static int uart_malta_probe(device_t dev) { struct uart_softc *sc; sc = device_get_softc(dev); sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); sc->sc_class = &uart_ns8250_class; bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); sc->sc_sysdev->bas.bst = mips_bus_space_generic; sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR); sc->sc_bas.bst = mips_bus_space_generic; sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR); return(uart_bus_probe(dev, 0, 0, 0, 0)); }
static void __find_pcic(void) { int i, j, step, found; u_int32_t addr; u_int8_t reg; int __read_revid (u_int32_t port) { addr = MIPS_PHYS_TO_KSEG1(i + port); printf("%#x\r", i); for (found = 0, j = 0; j < 0x100; j += 0x40) { *((volatile u_int8_t *)addr) = j; reg = *((volatile u_int8_t *)(addr + 1)); #ifdef DEBUG_FIND_PCIC_I82365SL_ONLY if (reg == 0x82 || reg == 0x83) { #else if ((reg & 0xc0) == 0x80) { #endif found++; } if (found) printf("\nfound %d socket at %#x" "(base from %#x)\n", found, addr, i + port - VR_ISA_PORT_BASE); } } step = 0x1000000; printf("\nFinding PCIC. Trying ISA port %#x-%#x step %#x\n", VR_ISA_PORT_BASE, VR_ISA_PORT_BASE + VR_ISA_PORT_SIZE, step); for (i = VR_ISA_PORT_BASE; i < VR_ISA_PORT_BASE+VR_ISA_PORT_SIZE; i+= step) { __read_revid (0x3e0); __read_revid (0x3e2); } }
/* * Handle Memory error. 3max, 3maxplus has ECC. * Correct single-bit error, panic on double-bit error. * XXX on double-error on clean user page, mark bad and reload frame? */ static void dec_3maxplus_errintr(void) { uint32_t erradr, csr; vaddr_t errsyn; /* Fetch error address, ECC chk/syn bits, clear interrupt */ erradr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR); errsyn = MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRSYN); *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0; kn03_wbflush(); csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_CSR); /* Send to kn02/kn03 memory subsystem handler */ dec_mtasic_err(erradr, errsyn, csr & KN03_CSR_BNK32M); }
/* * Locate the radio configuration data; it is located relative to the * board configuration data. */ static const void * ar5315_get_radio_info(void) { static const void *radio = NULL; const struct ar531x_boarddata *board; const uint8_t *baddr, *ptr, *end; if (radio) goto done; board = ar5315_get_board_info(); if (board == NULL) return NULL; baddr = (const uint8_t *) board; end = (const uint8_t *)MIPS_PHYS_TO_KSEG1(AR5315_RADIO_END); for (ptr = baddr + 0x1000; ptr < end; ptr += 0x1000) if (*(const uint32_t *)ptr != 0xffffffffU) { radio = ptr; goto done; } /* AR2316 moves radio data */ for (ptr = baddr + 0xf8; ptr < end; ptr += 0x1000) if (*(const uint32_t *)ptr != 0xffffffffU) { radio = ptr; goto done; } done: return radio; }
void led_display_word(uint32_t val) { uint32_t *ledbar = (uint32_t *)MIPS_PHYS_TO_KSEG1(MALTA_ASCIIWORD); *ledbar = val; }
void led_bar(uint8_t val) { uint8_t *ledbar = (uint8_t *)MIPS_PHYS_TO_KSEG1(MALTA_LEDBAR); *ledbar = val; }
void zscninit(struct consdev *cn) { struct zs_chanstate *cs; extern const struct cdevsw zstty_cdevsw; cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0); zs_cons = (uint8_t *)MIPS_PHYS_TO_KSEG1(ZS_BASE) + ZS_CHAN_A; /* XXX */ zs_conschan = cs = &zs_conschan_store; /* Setup temporary chanstate. */ cs->cs_reg_csr = zs_cons + ZS_CSR; cs->cs_reg_data = zs_cons + ZS_DATA; /* Initialize the pending registers. */ memcpy(cs->cs_preg, zs_init_reg, 16); cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; cs->cs_preg[12] = BPS_TO_TCONST(PCLK / 16, ZS_DEFSPEED); cs->cs_preg[13] = 0; cs->cs_defspeed = ZS_DEFSPEED; /* Clear the master interrupt enable. */ zs_write_reg(cs, 9, 0); /* Reset the whole SCC chip. */ zs_write_reg(cs, 9, ZSWR9_HARD_RESET); /* Copy "pending" to "current" and H/W */ zs_loadchannelregs(cs); }
/* * Common function for mapping DMA-safe memory. May be called by * bus-specific DMA memory map functions. */ int _bus_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs, size_t size, void **kvap, int flags) { vaddr_t va; bus_addr_t addr; int curseg; const uvm_flag_t kmflags = (flags & BUS_DMA_NOWAIT) != 0 ? UVM_KMF_NOWAIT : 0; /* * If we're only mapping 1 segment, use K0SEG, to avoid * TLB thrashing. */ #ifdef _LP64 if (nsegs == 1) { if (((mips_options.mips_cpu_flags & CPU_MIPS_D_CACHE_COHERENT) == 0) && (flags & BUS_DMA_COHERENT)) *kvap = (void *)MIPS_PHYS_TO_XKPHYS_UNCACHED( segs[0].ds_addr); else *kvap = (void *)MIPS_PHYS_TO_XKPHYS_CACHED( segs[0].ds_addr); return 0; } #else if ((nsegs == 1) && (segs[0].ds_addr < MIPS_PHYS_MASK)) { if (((mips_options.mips_cpu_flags & CPU_MIPS_D_CACHE_COHERENT) == 0) && (flags & BUS_DMA_COHERENT)) *kvap = (void *)MIPS_PHYS_TO_KSEG1(segs[0].ds_addr); else *kvap = (void *)MIPS_PHYS_TO_KSEG0(segs[0].ds_addr); return (0); } #endif /* _LP64 */ size = round_page(size); va = uvm_km_alloc(kernel_map, size, 0, UVM_KMF_VAONLY | kmflags); if (va == 0) return (ENOMEM); *kvap = (void *)va; for (curseg = 0; curseg < nsegs; curseg++) { for (addr = segs[curseg].ds_addr; addr < (segs[curseg].ds_addr + segs[curseg].ds_len); addr += PAGE_SIZE, va += PAGE_SIZE, size -= PAGE_SIZE) { if (size == 0) panic("_bus_dmamem_map: size botch"); pmap_enter(pmap_kernel(), va, addr, VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED | VM_PROT_READ | VM_PROT_WRITE); } } pmap_update(pmap_kernel()); return (0); }
void ingenic_putchar_init(void) { /* * XXX don't screw with the UART's speed until we know what clock * we're on */ #if 0 int rate; #endif extern int comspeed(long, long, int); com0addr = (uint32_t *)MIPS_PHYS_TO_KSEG1(JZ_UART0); #if 0 if (comcnfreq != -1) { rate = comspeed(comcnspeed, comcnfreq, COM_TYPE_INGENIC); if (rate < 0) return; /* XXX */ #endif com0addr[com_ier] = 0; com0addr[com_lctl] = htole32(LCR_DLAB); #if 0 com0addr[com_dlbl] = htole32(rate & 0xff); com0addr[com_dlbh] = htole32(rate >> 8); #endif com0addr[com_lctl] = htole32(LCR_8BITS); /* XXX */ com0addr[com_mcr] = htole32(MCR_DTR|MCR_RTS); com0addr[com_fifo] = htole32( FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1 | FIFO_UART_ON); #if 0 }
static int mace_serial_init(const char *consdev) { #if (NCOM > 0) const char *dbaud; int speed; u_int32_t base; if ((strlen(consdev) == 9) && (!strncmp(consdev, "serial", 6)) && (consdev[7] == '0' || consdev[7] == '1')) { /* Get comm speed from ARCS */ dbaud = ARCBIOS->GetEnvironmentVariable("dbaud"); speed = strtoul(dbaud, NULL, 10); base = (consdev[7] == '0') ? MACE_ISA_SER1_BASE : MACE_ISA_SER2_BASE; delay(10000); /* XXX: hardcoded MACE iotag */ if (comcnattach(3, MIPS_PHYS_TO_KSEG1(MACE_BASE + base), speed, COM_FREQ, COM_TYPE_NORMAL, comcnmode) == 0) return (1); } #endif return (0); }
int obio_attach(device_t dev) { struct obio_softc *sc = device_get_softc(dev); sc->oba_st = MIPS_BUS_SPACE_IO; sc->oba_addr = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR); sc->oba_size = MALTA_PCIMEM3_SIZE; sc->oba_rman.rm_type = RMAN_ARRAY; sc->oba_rman.rm_descr = "OBIO I/O"; if (rman_init(&sc->oba_rman) != 0 || rman_manage_region(&sc->oba_rman, sc->oba_addr, sc->oba_addr + sc->oba_size) != 0) panic("obio_attach: failed to set up I/O rman"); sc->oba_irq_rman.rm_type = RMAN_ARRAY; sc->oba_irq_rman.rm_descr = "OBIO IRQ"; /* * This module is intended for UART purposes only and * it's IRQ is 4 */ if (rman_init(&sc->oba_irq_rman) != 0 || rman_manage_region(&sc->oba_irq_rman, 4, 4) != 0) panic("obio_attach: failed to set up IRQ rman"); device_add_child(dev, "uart", 0); bus_generic_probe(dev); bus_generic_attach(dev); return (0); }
static void sbwdog_attach(device_t parent, device_t self, void *aux) { struct sbwdog_softc *sc = device_private(self); struct sbscd_attach_args *sa = aux; sc->sc_dev = self; sc->sc_wdog_period = SBWDOG_DEFAULT_PERIOD; sc->sc_addr = MIPS_PHYS_TO_KSEG1(sa->sa_base + sa->sa_locs.sa_offset); aprint_normal(": %d second period\n", sc->sc_wdog_period); sc->sc_smw.smw_name = device_xname(sc->sc_dev); sc->sc_smw.smw_cookie = sc; sc->sc_smw.smw_setmode = sbwdog_setmode; sc->sc_smw.smw_tickle = sbwdog_tickle; sc->sc_smw.smw_period = sc->sc_wdog_period; if (sysmon_wdog_register(&sc->sc_smw) != 0) aprint_error_dev(self, "unable to register with sysmon\n"); if (sa->sa_locs.sa_intr[0] != SBOBIOCF_INTR_DEFAULT) cpu_intr_establish(sa->sa_locs.sa_intr[0], IPL_HIGH, sbwdog_intr, sc); }
void tx3912video_hpcfbinit(struct tx3912video_softc *sc) { struct video_chip *chip = sc->sc_chip; struct hpcfb_fbconf *fb = &sc->sc_fbconf; vaddr_t fbvaddr = (vaddr_t)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); memset(fb, 0, sizeof(struct hpcfb_fbconf)); fb->hf_conf_index = 0; /* configuration index */ fb->hf_nconfs = 1; /* how many configurations */ strncpy(fb->hf_name, "TX3912 built-in video", HPCFB_MAXNAMELEN); /* frame buffer name */ strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN); /* configuration name */ fb->hf_height = chip->vc_fbheight; fb->hf_width = chip->vc_fbwidth; fb->hf_baseaddr = (u_long)fbvaddr; fb->hf_offset = (u_long)fbvaddr - mips_ptob(mips_btop(fbvaddr)); /* frame buffer start offset */ fb->hf_bytes_per_line = (chip->vc_fbwidth * chip->vc_fbdepth) / NBBY; fb->hf_nplanes = 1; fb->hf_bytes_per_plane = chip->vc_fbheight * fb->hf_bytes_per_line; fb->hf_access_flags |= HPCFB_ACCESS_BYTE; fb->hf_access_flags |= HPCFB_ACCESS_WORD; fb->hf_access_flags |= HPCFB_ACCESS_DWORD; if (video_reverse_color()) fb->hf_access_flags |= HPCFB_ACCESS_REVERSE; switch (chip->vc_fbdepth) { default: panic("tx3912video_hpcfbinit: not supported color depth"); /* NOTREACHED */ case 2: fb->hf_class = HPCFB_CLASS_GRAYSCALE; fb->hf_access_flags |= HPCFB_ACCESS_STATIC; fb->hf_pack_width = 8; fb->hf_pixels_per_pack = 4; fb->hf_pixel_width = 2; fb->hf_class_data_length = sizeof(struct hf_gray_tag); /* reserved for future use */ fb->hf_u.hf_gray.hf_flags = 0; break; case 8: fb->hf_class = HPCFB_CLASS_INDEXCOLOR; fb->hf_access_flags |= HPCFB_ACCESS_STATIC; fb->hf_pack_width = 8; fb->hf_pixels_per_pack = 1; fb->hf_pixel_width = 8; fb->hf_class_data_length = sizeof(struct hf_indexed_tag); /* reserved for future use */ fb->hf_u.hf_indexed.hf_flags = 0; break; } }
int tx3912video_init(paddr_t fb_start, paddr_t *fb_end) { struct video_chip *chip = &tx3912video_chip; tx_chipset_tag_t tc; txreg_t reg; int fbdepth, reverse, error; reverse = video_reverse_color(); chip->vc_v = tc = tx_conf_get_tag(); reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); fbdepth = 1 << (TX3912_VIDEOCTRL1_BITSEL(reg)); switch (fbdepth) { case 2: bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; break; case 4: /* XXX should implement rasops4.c */ fbdepth = 2; bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); TX3912_VIDEOCTRL1_BITSEL_CLR(reg); reg = TX3912_VIDEOCTRL1_BITSEL_SET(reg, TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE); tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); break; case 8: bootinfo->fb_type = reverse ? BIFB_D8_FF : BIFB_D8_00; break; } chip->vc_fbdepth = fbdepth; chip->vc_fbwidth = bootinfo->fb_width; chip->vc_fbheight= bootinfo->fb_height; /* Allocate framebuffer area */ error = tx3912video_framebuffer_alloc(chip, fb_start, fb_end); if (error != 0) return (1); #if notyet tx3912video_resolution_init(chip); #else /* Use Windows CE setting. */ #endif /* Set DMA transfer address to VID module */ tx3912video_framebuffer_init(chip); /* Syncronize framebuffer addr to frame signal */ tx3912video_reset(chip); bootinfo->fb_line_bytes = (chip->vc_fbwidth * fbdepth) / NBBY; bootinfo->fb_addr = (void *)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); return (0); }
static void panel_attach(device_t parent, device_t self, void *aux) { struct panel_softc *sc = device_private(self); struct mainbus_attach_args *maa = aux; struct hd44780_io io; static struct lcdkp_xlate keys[] = { { 0xfa, 'h' }, { 0xf6, 'k' }, { 0xde, 'l' }, { 0xee, 'j' }, { 0x7e, 's' }, { 0xbe, 'e' } }; sc->sc_lcd.sc_dev = self; sc->sc_lcd.sc_iot = maa->ma_iot; if (bus_space_map(sc->sc_lcd.sc_iot, maa->ma_addr, PANEL_REGION, 0, &sc->sc_lcd.sc_ioir)) { aprint_error(": unable to map registers\n"); return; } bus_space_subregion(sc->sc_lcd.sc_iot, sc->sc_lcd.sc_ioir, DATA_OFFSET, 1, &sc->sc_lcd.sc_iodr); printf("\n"); sc->sc_lcd.sc_dev_ok = 1; sc->sc_lcd.sc_cols = PANEL_COLS; sc->sc_lcd.sc_vcols = PANEL_VCOLS; sc->sc_lcd.sc_flags = HD_8BIT | HD_MULTILINE | HD_KEYPAD; sc->sc_lcd.sc_writereg = panel_cbt_hdwritereg; sc->sc_lcd.sc_readreg = panel_cbt_hdreadreg; hd44780_attach_subr(&sc->sc_lcd); /* Hello World */ io.dat = 0; io.len = PANEL_VCOLS * PANEL_ROWS; memcpy(io.buf, &startup_message, io.len); hd44780_ddram_io(&sc->sc_lcd, sc->sc_lcd.sc_curchip, &io, HD_DDRAM_WRITE); pmf_device_register1(self, NULL, NULL, panel_shutdown); sc->sc_kp.sc_iot = maa->ma_iot; sc->sc_kp.sc_ioh = MIPS_PHYS_TO_KSEG1(PANEL_BASE); /* XXX */ sc->sc_kp.sc_knum = sizeof(keys) / sizeof(struct lcdkp_xlate); sc->sc_kp.sc_kpad = keys; sc->sc_kp.sc_rread = panel_cbt_kprread; lcdkp_attach_subr(&sc->sc_kp); callout_init(&sc->sc_callout, 0); selinit(&sc->sc_selq); }
satime_t getsecs(void) { volatile uint8_t *mcclock_reg, *mcclock_data; u_int sec; mcclock_reg = (void *)MIPS_PHYS_TO_KSEG1(MCCLOCK_BASE + MCCLOCK_REG); mcclock_data = (void *)MIPS_PHYS_TO_KSEG1(MCCLOCK_BASE + MCCLOCK_DATA); *mcclock_reg = MC_SEC; sec = bcdtobin(*mcclock_data); *mcclock_reg = MC_MIN; sec += bcdtobin(*mcclock_data) * 60; *mcclock_reg = MC_HOUR; sec += bcdtobin(*mcclock_data) * 60 * 60; return (satime_t)sec; }
int uart_cpu_getdev(int devtype, struct uart_devinfo *di) { di->ops = uart_getops(&uart_ns8250_class); di->bas.chan = 0; di->bas.bst = 0; di->bas.regshft = 0; di->bas.rclk = 0; di->baudrate = 115200; di->databits = 8; di->stopbits = 1; di->parity = UART_PARITY_NONE; uart_bus_space_io = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR); uart_bus_space_mem = mips_bus_space_generic; di->bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR); return (0); }
static void cswarm_setled(u_int index, char c) { volatile u_char *led_ptr = (void *)MIPS_PHYS_TO_KSEG1(SWARM_LEDS_PHYS); if (index < 4) led_ptr[0x20 + ((3 - index) << 3)] = c; }
static int uart_rc32434_probe(device_t dev) { struct uart_softc *sc; sc = device_get_softc(dev); sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); sc->sc_class = &uart_ns8250_class; bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); sc->sc_sysdev->bas.regshft = 2; sc->sc_sysdev->bas.bst = 0; sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(IDT_BASE_UART0); sc->sc_bas.regshft = 2; sc->sc_bas.bst = 0; sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(IDT_BASE_UART0); return (uart_bus_probe(dev, 2, 330000000UL/2, 0, 0)); }
static void sbscn_attach(struct device *parent, struct device *self, void *aux) { struct sbscn_softc *sc = (struct sbscn_softc *)self; struct sbobio_attach_args *sap = aux; int i; sc->sc_addr = sap->sa_base + sap->sa_locs.sa_offset; printf("\n"); for (i = 0; i < 2; i++) sbscn_attach_channel(sc, i, sap->sa_locs.sa_intr[i]); /* init duart_opcr */ WRITE_REG(MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x270), 0); /* init duart_aux_ctrl */ WRITE_REG(MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x210), 0x0f); /* XXX */ }
void cpu_reboot(int howto, char *bootstr) { /* Take a snapshot before clobbering any registers. */ savectx(curpcb); if (cold) { howto |= RB_HALT; goto haltsys; } /* If "always halt" was specified as a boot flag, obey. */ if (boothowto & RB_HALT) howto |= RB_HALT; boothowto = howto; if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { waittime = 0; vfs_shutdown(); /* * If we've been adjusting the clock, the todr * will be out of synch; adjust it now. */ resettodr(); } splhigh(); if (howto & RB_DUMP) dumpsys(); haltsys: doshutdownhooks(); pmf_system_shutdown(boothowto); if (howto & RB_HALT) { printf("\n"); printf("The operating system has halted.\n"); printf("Please press any key to reboot.\n\n"); cnpollc(1); /* For proper keyboard command handling */ cngetc(); cnpollc(0); } printf("rebooting...\n\n"); delay(500000); *(volatile char *)MIPS_PHYS_TO_KSEG1(LED_ADDR) = LED_RESET; printf("WARNING: reboot failed!\n"); for (;;) ; }