void MMU_Init(void)
{
int i,j;
//========================== IMPORTANT NOTE =========================
//The current stack and code area can't be re-mapped in this routine.
//If you want memory map mapped freely, your own sophiscated MMU
//initialization code is needed.
//===================================================================
MMU_DisableDCache();
MMU_DisableICache();
//If write-back is used,the DCache should be cleared.
for(i=0;i<64;i++)
for(j=0;j<8;j++)
MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
MMU_InvalidateICache();
#if 0
//To complete MMU_Init() fast, Icache may be turned on here.
MMU_EnableICache();
#endif
MMU_DisableMMU();
MMU_InvalidateTLB();
//MMU_SetMTT(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
//MMU_SetMTT(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0
MMU_SetMTT(0x00000000,0x03f00000,(int)__ENTRY,RW_CB); //bank0
MMU_SetMTT(0x04000000,0x07f00000,0,RW_NCNB); //bank0
MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1
MMU_SetMTT(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
MMU_SetMTT(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
//MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_CNB); //bank4 for STRATA Flash
MMU_SetMTT(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
//30f00000->30100000, 31000000->30200000
MMU_SetMTT(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1
MMU_SetMTT(0x30200000,0x33e00000,0x30200000,RW_NCNB); //bank6-2
//
MMU_SetMTT(0x33f00000,0x33f00000,0x33f00000,RW_CB); //bank6-3
MMU_SetMTT(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
MMU_SetMTT(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
MMU_SetMTT(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
MMU_SetMTT(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
MMU_SetMTT(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used
MMU_SetTTBase(_MMUTT_STARTADDRESS);//设置一级映射描述符表的基地址
MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);//ARM处理器的16个域的访问权限
//DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)
MMU_SetProcessId(0x0);//设置进程标识符
MMU_EnableAlignFault();//使能地址对齐检查功能
MMU_EnableMMU();
MMU_EnableICache();
MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.
}
static void hal_mmu_init(void)
{
acoral_32 i,j;
/*========================== IMPORTANT NOTE =========================*/
/*The current stack and code area can't be re-mapped in this routine.*/
/*If you want memory map mapped freely, your own sophiscated MMU*/
/*initialization code is needed.*/
/*===================================================================*/
MMU_DisableDCache();
MMU_DisableICache();
/*If write-back is used,the DCache should be cleared.*/
for(i=0;i<64;i++)
for(j=0;j<8;j++)
MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
MMU_InvalidateICache();
#if 0
/*To complete MMU_Init() fast, Icache may be turned on here.*/
MMU_EnableICache();
#endif
MMU_DisableMMU();
MMU_InvalidateTLB();
/*hal_mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr)*/
/*hal_mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); /*bank0*/
hal_mmu_setmtt(0x00000000,0x03f00000,__ENTRY,RW_CB); /*bank0*/
hal_mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); /*bank0*/
hal_mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); /*bank1*/
hal_mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); /*bank2*/
hal_mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); /*bank3*/
/*hal_mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); /*bank4*/
hal_mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CNB); /*bank4 for STRATA Flash*/
hal_mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); /*bank5*/
/*30f00000->30100000, 31000000->30200000*/
hal_mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_NCNB); /*bank6-1*/
hal_mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_NCNB); /*bank6-2*/
/**/
hal_mmu_setmtt(0x33f00000,0x33f00000,0x33f00000,RW_NCNB); /*bank6-3*/
hal_mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); /*bank7*/
hal_mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); /*SFR*/
hal_mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); /*SFR*/
hal_mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); /*SFR*/
hal_mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);/*not used*/
MMU_SetTTBase(&MMU_base);
MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
/*DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)*/
MMU_SetProcessId(0x0);
MMU_EnableAlignFault();
MMU_EnableMMU();
MMU_EnableICache();
MMU_EnableDCache(); /*DCache should be turned on after MMU is turned on.*/
}
void MMU_Init(void)
{
int i,j;
MMU_DisableDCache();
MMU_DisableICache();
for(i=0;i<64;i++)
for(j=0;j<8;j++)
MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
MMU_InvalidateICache();
#if 0
MMU_EnableICache();
#endif
MMU_DisableMMU();
MMU_InvalidateTLB();
MMU_SetMTT(0x00000000,0x03f00000,(int)__ENTRY,RW_CB); //bank0
MMU_SetMTT(0x04000000,0x07f00000,0,RW_NCNB); //bank0
MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1
MMU_SetMTT(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
MMU_SetMTT(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
//MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_CNB); //bank4 for STRATA Flash
MMU_SetMTT(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
//30f00000->30100000, 31000000->30200000
MMU_SetMTT(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1
MMU_SetMTT(0x30200000,0x33e00000,0x30200000,RW_NCNB); //bank6-2
//
MMU_SetMTT(0x33f00000,0x33f00000,0x33f00000,RW_CB); //bank6-3
MMU_SetMTT(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
MMU_SetMTT(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
MMU_SetMTT(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
MMU_SetMTT(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
MMU_SetMTT(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used
MMU_SetTTBase(_MMUTT_STARTADDRESS);
MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
//DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)
MMU_SetProcessId(0x0);
MMU_EnableAlignFault();
MMU_EnableMMU();
MMU_EnableICache();
MMU_EnableDCache(); //
}
// attr=RW_CB,RW_CNB,RW_NCNB,RW_FAULT
void ChangeRomCacheStatus(int attr)
{
int i,j;
MMU_DisableDCache();
MMU_DisableICache();
//If write-back is used,the DCache should be cleared.
for(i=0;i<64;i++)
for(j=0;j<8;j++)
MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
MMU_InvalidateICache();
MMU_DisableMMU();
MMU_InvalidateTLB();
MMU_SetMTT(0x00000000,0x07f00000,0x00000000,attr); //bank0
MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,attr); //bank1
MMU_EnableMMU();
MMU_EnableICache();
MMU_EnableDCache();
}
void MMU_Init(void)
{
int i,j;
unsigned long * pTT;
//========================== IMPORTANT NOTE =========================
//The current stack and code area can't be re-mapped in this routine.
//If you want memory map mapped freely, your own sophiscated MMU
//initialization code is needed.
//===================================================================
Uart_Printf("MMU_Init test 1\n");
MMU_DisableDCache();
MMU_DisableICache();
Uart_Printf("MMU_Init test 2\n");
//If write-back is used,the DCache should be cleared.
for(i=0;i<64;i++)
for(j=0;j<8;j++)
MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
MMU_InvalidateICache();
#if 0
//To complete MMU_Init() fast, Icache may be turned on here.
MMU_EnableICache();
#endif
Uart_Printf("MMU_Init test 3\n");
MMU_DisableMMU();
Uart_Printf("MMU_Init test 4\n");
MMU_InvalidateTLB();
Uart_Printf("MMU_Init test 5\n");
MMU_SetMTT(0x00000000,0xffffffff,0,RW_FAULT); //bank0
MMU_SetMTT(0x00000000,0x08000000,(int)__ENTRY,RW_NCNB); //bank0
MMU_SetMTT(0x50000000,0x58000000,0x50000000,RW_NCNB); //bank0
MMU_SetMTT(0x70000000,0x70400000,0x70000000,RW_NCNB); //bank0
MMU_SetMTT(0x71000000,0x71400000,0x71000000,RW_NCNB); //bank0
MMU_SetMTT(0x72000000,0x73200000,0x72000000,RW_NCNB); //bank0
MMU_SetMTT(0x74000000,0x74500000,0x74000000,RW_NCNB); //bank0
MMU_SetMTT(0x75000000,0x75400000,0x75000000,RW_NCNB); //bank0
MMU_SetMTT(0x76000000,0x76400000,0x76000000,RW_NCNB); //bank0
MMU_SetMTT(0x77000000,0x77300000,0x77000000,RW_NCNB); //bank0
MMU_SetMTT(0x78000000,0x78c00000,0x78000000,RW_NCNB); //bank0
MMU_SetMTT(0x7c000000,0x7c500000,0x7c000000,RW_NCNB); //bank0
MMU_SetMTT(0x7d000000,0x7e100000,0x7d000000,RW_NCNB); //bank0
MMU_SetMTT(0x7f000000,0x7f100000,0x7f000000,RW_NCNB); //bank0
MMU_SetMTT(0xc0000000,0xc8000000,0x50000000,RW_NCNB);
//[email protected] test
//MMU_SetMTT(0x60000000,0x68000000,0x50000000,RW_NCNB); //bank0
MMU_SetTTBase(_MMUTT_STARTADDRESS);
MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
//DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)
MMU_SetProcessId(0x0);
MMU_EnableAlignFault();
MMU_EnableMMU();
MMU_EnableICache();
MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.
}
/**
* @brief Core/MMU Module initialization.
* @note This function is implicitly invoked on system initialization,
* there is no need to explicitly initialize the module.
*
* @notapi
*/
void __core_init(void) {
uint32_t pm;
/*
* Invalidate L1 D Cache if it was disabled
*/
pm = __get_SCTLR();
if ((pm & SCTLR_C_Msk) == 0) {
__L1C_CleanInvalidateCache(DCISW_INVALIDATE);
}
/*
* Default, undefined regions
*/
for (pm = 0; pm < 4096; ++pm)
mmuTable[pm] = TTE_SECT_UNDEF;
/*
* ROM region
*
* 0x00000000
*/
mmuTable[0] = TTE_SECT_SECTION(0x00000000) |
TTE_SECT_MEM_NO_CACHEABLE |
TTE_SECT_RO_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* NFC SRAM region
*
* 0x00100000
*/
mmuTable[1] = TTE_SECT_SECTION(0x00100000) |
TTE_SECT_DEVICE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* SRAM region
*
* 0x00200000
*/
mmuTable[2] = TTE_SECT_SECTION(0x00200000) |
TTE_SECT_MEM_CACHEABLE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* UDPHS RAM region
*
* 0x00300000
*/
mmuTable[3] = TTE_SECT_SECTION(0x00300000) |
TTE_SECT_DEVICE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* UHPHS region
*
* 0x00400000
*/
mmuTable[4] = TTE_SECT_SECTION(0x00400000) |
TTE_SECT_DEVICE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* UDPHS region
*
* 0x00500000
*/
mmuTable[5] = TTE_SECT_SECTION(0x00500000) |
TTE_SECT_DEVICE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* AXIMX region
*
* 0x00600000
*/
mmuTable[6] = TTE_SECT_SECTION(0x00600000) |
TTE_SECT_DEVICE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* DAP region
*
* 0x00700000
*/
mmuTable[7] = TTE_SECT_SECTION(0x00700000) |
TTE_SECT_DEVICE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* L2CC region, low
*
* 0x00a00000
*/
mmuTable[0xa] = TTE_SECT_SECTION(0x00a00000) |
TTE_SECT_DEVICE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* L2CC region, hi
*
* 0x00b00000
*/
mmuTable[0xb] = TTE_SECT_SECTION(0x00b00000) |
TTE_SECT_DEVICE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* EBI regions
*
* 0x10000000 - 0x1fffffff
*/
for (pm = 0x100; pm < 0x200; pm++)
mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
TTE_SECT_MEM_STRONGLY_ORD |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* DDR regions
*
* 0x20000000 - 0x3fffffff
*/
for (pm = 0x200; pm < 0x400; pm++)
mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
TTE_SECT_MEM_CACHEABLE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* DDR AESB regions
*
* 0x40000000 - 0x5fffffff
*/
for (pm = 0x400; pm < 0x600; pm++)
mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
TTE_SECT_MEM_CACHEABLE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* EBI 1, 2 and 3 regions
*
* 0x60000000 - 0x8fffffff
*/
for (pm = 0x600; pm < 0x900; pm++)
mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
TTE_SECT_MEM_STRONGLY_ORD |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* QSPI0/1 AESB MEM regions
*
* 0x90000000 - 0x9fffffff
*/
for (pm = 0x900; pm < 0xa00; pm++)
mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
TTE_SECT_MEM_STRONGLY_ORD |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* SDMMC0/1 regions
*
* 0xa0000000 - 0xbfffffff
*/
for (pm = 0xa00; pm < 0xc00; pm++)
mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
TTE_SECT_MEM_STRONGLY_ORD |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* NFC regions
*
* 0xc0000000 - 0xcfffffff
*/
for (pm = 0xc00; pm < 0xd00; pm++)
mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
TTE_SECT_MEM_STRONGLY_ORD |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* QSPI0/1 MEM regions
*
* 0xd0000000 - 0xdfffffff
*/
for (pm = 0xd00; pm < 0xe00; pm++)
mmuTable[pm] = TTE_SECT_SECTION(pm << 20) |
TTE_SECT_MEM_STRONGLY_ORD |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* Internal peripherals regions
*
* 0xf0000000
* 0xf8000000
* 0xfc000000
*/
mmuTable[0xf00] = TTE_SECT_SECTION(0xf0000000) |
TTE_SECT_DEVICE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
mmuTable[0xf80] = TTE_SECT_SECTION(0xf8000000) |
TTE_SECT_DEVICE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
mmuTable[0xfc0] = TTE_SECT_SECTION(0xfc000000) |
TTE_SECT_DEVICE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x0F) |
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
/*
* Invalidate TLB and L1 I cache
* Enable caches and MMU
*/
MMU_InvalidateTLB();
__set_TTBR0((uint32_t)mmuTable|0x5B);
__set_DACR(0xC0000000);
__DSB();
__ISB();
/*
* L1 I cache invalidate and enable
*/
pm = __get_SCTLR();
if ((pm & SCTLR_I_Msk) == 0) {
__set_ICIALLU(0);
__set_SCTLR(pm | SCTLR_I_Msk);
}
/*
* MMU enable
*/
pm = __get_SCTLR();
if ((pm & SCTLR_M_Msk) == 0)
__set_SCTLR(pm | SCTLR_M_Msk);
/*
* L1 D cache enable
*/
pm = __get_SCTLR();
if ((pm & SCTLR_C_Msk) == 0) {
__set_SCTLR(pm | SCTLR_C_Msk);
}
}
void MMU_Init(void)
{
int i,j;
//========================== IMPORTANT NOTE =========================
//The current stack and code area can't be re-mapped in this routine.
//If you want memory map mapped freely, your own sophiscated MMU
//initialization code is needed.
//===================================================================
MMU_DisableDCache();
MMU_DisableICache();
//If write-back is used,the DCache should be cleared.
for(i=0;i<64;i++)
for(j=0;j<8;j++)
MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
MMU_InvalidateICache();
#if 0
//To complete MMU_Init() fast, Icache may be turned on here.
MMU_EnableICache();
#endif
MMU_DisableMMU();
MMU_InvalidateTLB();
//MMU_SetMTT(int wVSAddr,int wVEAddr,int wPSAddr,int wAttrib)
#ifdef MY_SPL_BOARD
MMU_SetMTT(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0
MMU_SetMTT(0x08000000,0x081FFFFF,0x08000000,RW_CNB); //bank1
MMU_SetMTT(0x10000000,0x10400000,0x10000000,RW_CNB); //bank2
MMU_SetMTT(0x18000000,0x19f00000,0x18000000,RW_NCNB); //bank3
MMU_SetMTT(0x40000000,0x40000000,0x40000000,RW_NCNB); //SFR
MMU_SetMTT(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
#else
MMU_SetMTT(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0
MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1
MMU_SetMTT(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
MMU_SetMTT(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4
MMU_SetMTT(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
MMU_SetMTT(0x30000000,0x30f00000,0x30000000,RW_CB); //bank6-1
MMU_SetMTT(0x31000000,0x33e00000,0x31000000,RW_NCNB); //bank6-2
MMU_SetMTT(0x33f00000,0x33f00000,0x33f00000,RW_CB); //bank6-3
MMU_SetMTT(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
MMU_SetMTT(0x40000000,0x5af00000,0x40000000,RW_NCNB);//SFR+StepSram
MMU_SetMTT(0x5b000000,0xfff00000,0x5b000000,RW_FAULT);//not used
#endif
MMU_SetTTBase(MMUTT_SADDR);
MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
//DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)
MMU_SetProcessId(0x0);
MMU_EnableAlignFault();
MMU_EnableMMU();
MMU_EnableICache();
MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.
}
