static void USB_HostApplicationInit(void)
{
usb_status_t status = kStatus_USB_Success;
IRQn_Type usbIrq;
#if ((defined USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI))
IRQn_Type usbFsIrqs[] = USB_IRQS;
usbIrq = usbFsIrqs[CONTROLLER_ID - kUSB_ControllerKhci0];
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk));
#endif /* USB_HOST_CONFIG_KHCI */
#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI))
IRQn_Type usbHsIrqs[] = USBHS_IRQS;
usbIrq = usbHsIrqs[CONTROLLER_ID - kUSB_ControllerEhci0];
CLOCK_EnableUsbhs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk));
USB_EhciPhyInit(CONTROLLER_ID, BOARD_XTAL0_CLK_HZ);
#endif /* USB_HOST_CONFIG_EHCI */
#if ((defined FSL_FEATURE_SOC_MPU_COUNT) && (FSL_FEATURE_SOC_MPU_COUNT))
MPU_Enable(MPU, 0);
#endif /* FSL_FEATURE_SOC_MPU_COUNT */
status = USB_HostInit(CONTROLLER_ID, &g_HostHandle, USB_HostEvent);
if (status != kStatus_USB_Success)
{
usb_echo("host init error\r\n");
return;
}
NVIC_SetPriority(usbIrq, USB_HOST_INTERRUPT_PRIORITY);
NVIC_EnableIRQ(usbIrq);
usb_echo("host init done\r\n");
}
/*!
* @brief Application initialization function.
*
* This function initializes the application.
*
* @return None.
*/
void APPInit(void)
{
uint8_t irqNo;
#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0)
uint8_t ehciIrq[] = USBHS_IRQS;
irqNo = ehciIrq[CONTROLLER_ID - kUSB_ControllerEhci0];
CLOCK_EnableUsbhs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk));
USB_EhciPhyInit(CONTROLLER_ID, BOARD_XTAL0_CLK_HZ);
#endif
#if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0)
uint8_t khciIrq[] = USB_IRQS;
irqNo = khciIrq[CONTROLLER_ID - kUSB_ControllerKhci0];
SystemCoreClockUpdate();
#if ((defined FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && (FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED))
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U);
#else
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk));
#endif /* FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED */
#endif
#if (defined(FSL_FEATURE_SOC_MPU_COUNT) && (FSL_FEATURE_SOC_MPU_COUNT > 0U))
MPU_Enable(MPU, 0);
#endif /* FSL_FEATURE_SOC_MPU_COUNT */
/*
* If the SOC has USB KHCI dedicated RAM, the RAM memory needs to be clear after
* the KHCI clock is enabled. When the demo uses USB EHCI IP, the USB KHCI dedicated
* RAM can not be used and the memory can't be accessed.
*/
#if (defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U))
#if (defined(FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS) && (FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS > 0U))
for (int i = 0; i < FSL_FEATURE_USB_KHCI_USB_RAM; i++)
{
((uint8_t *)FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS)[i] = 0x00U;
}
#endif /* FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS */
#endif /* FSL_FEATURE_USB_KHCI_USB_RAM */
s_cdcVcom.speed = USB_SPEED_FULL;
s_cdcVcom.attach = 0;
s_cdcVcom.deviceHandle = NULL;
if (kStatus_USB_Success != USB_DeviceInit(CONTROLLER_ID, USB_DeviceCallback, &s_cdcVcom.deviceHandle))
{
usb_echo("USB device vcom failed\r\n");
return;
}
else
{
usb_echo("USB device CDC vcom demo\r\n");
}
NVIC_SetPriority((IRQn_Type)irqNo, USB_DEVICE_INTERRUPT_PRIORITY);
NVIC_EnableIRQ((IRQn_Type)irqNo);
USB_DeviceRun(s_cdcVcom.deviceHandle);
}
/*!
* @brief app initialization.
*/
void APP_init(void)
{
usb_status_t status = kStatus_USB_Success;
IRQn_Type usb_irq;
usb_uartConfiguration uartConfiguration;
g_xfer.buffer = (uint8_t *)&usbRecvUart[0];
g_xfer.size = USB_HOST_CDC_UART_RX_MAX_LEN;
USB_UartGetDefaultConfiguratoion(&uartConfiguration);
uartConfiguration.baudRate_Bps = BOARD_DEBUG_UART_BAUDRATE;
uartConfiguration.enableTx = true;
uartConfiguration.enableRx = true;
USB_UartInit((USB_UartType *)BOARD_DEBUG_UART_BASEADDR, &uartConfiguration, CLOCK_GetFreq(BOARD_DEBUG_UART_CLKSRC));
USB_UartCreateHandle((USB_UartType *)BOARD_DEBUG_UART_BASEADDR, &g_UartHandle, UART_UserCallback, NULL);
USB_UartReceiveDataIRQ((USB_UartType *)BOARD_DEBUG_UART_BASEADDR, &g_UartHandle, &g_xfer, NULL);
g_AttachFlag = 0;
USB_HostCdcInitBuffer();
#if ((defined USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI))
IRQn_Type usb_fs_irqs[] = USB_IRQS;
usb_irq = usb_fs_irqs[CONTROLLER_ID - kUSB_ControllerKhci0];
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk));
#endif
#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI))
IRQn_Type usb_hs_irqs[] = USBHS_IRQS;
usb_irq = usb_hs_irqs[CONTROLLER_ID - kUSB_ControllerEhci0];
CLOCK_EnableUsbhs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk));
USB_EhciPhyInit(CONTROLLER_ID, BOARD_XTAL0_CLK_HZ);
#endif
#if ((defined FSL_FEATURE_SOC_MPU_COUNT) && (FSL_FEATURE_SOC_MPU_COUNT))
MPU_Enable(MPU, 0);
#endif /* FSL_FEATURE_SOC_MPU_COUNT */
status = USB_HostInit(CONTROLLER_ID, &g_hostHandle, USB_HostEvent);
if (status != kStatus_USB_Success)
{
usb_echo("host init error\r\n");
return;
}
NVIC_SetPriority(usb_irq, USB_HOST_INTERRUPT_PRIORITY);
NVIC_EnableIRQ(usb_irq);
usb_echo("host init done\r\n");
usb_echo("This example requires that the CDC device uses Hardware flow\r\n");
usb_echo(
"if the device does't support it, please set USB_HOST_UART_SUPPORT_HW_FLOW to zero and rebuild this "
"project\r\n");
usb_echo("Type strings, then the string\r\n");
usb_echo("will be echoed back from the device\r\n");
}
/**
* @brief MPU region configuration function
*/
void MPU_Config(void)
{
MPU_Disable();
/* Configure FLASH region as REGION N0, 1MB of size and R/W region */
MPU_Region_Config(0,FLASH_ADDRESS_START,FLASH_SIZE,MPU_REGION_PRIVILEGED_READ_WRITE);
/* Configure RAM region as Region N1, 128kB of size and R/W region */
MPU_Region_Config(1,RAM1_ADDRESS_START,RAM1_SIZE,MPU_REGION_PRIVILEGED_READ_WRITE);
/* Configure small RAM region as REGION N2, 32Byte of size, no access region and Execute Never region */
MPU_Region_Config(2,RAM2_ADDRESS_START,RAM2_SIZE,MPU_NO_ACCESS);
/* Configure Peripheral region as REGION N3, 128KB of size, R/W region */
MPU_Region_Config(3,PERIPH_ADDRESS_START,PERIPH_SIZE,MPU_REGION_PRIVILEGED_READ_WRITE);
/* Enable the memory fault exception */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Enable MPU */
MPU_Enable();
}
/**************************************************************************//**
* @brief Main function.
*****************************************************************************/
int main( void )
{
int i;
MPU_RegionInit_TypeDef flashInit = MPU_INIT_FLASH_DEFAULT;
MPU_RegionInit_TypeDef sramInit = MPU_INIT_SRAM_DEFAULT;
MPU_RegionInit_TypeDef peripheralInit = MPU_INIT_PERIPHERAL_DEFAULT;
/* Chip alignment */
CHIP_Init();
/* If first word of user data page is non-zero, enable eA Profiler trace */
BSP_TraceProfilerSetup();
/* Enable LCD without voltage boost */
SegmentLCD_Init( false );
SegmentLCD_AllOff();
SegmentLCD_Symbol(LCD_SYMBOL_GECKO, 1);
SegmentLCD_Symbol(LCD_SYMBOL_EFM32, 1);
GpioInit();
RTCDRV_Setup( cmuSelect_LFXO, cmuClkDiv_32);
ScrollText( " MPU DEMO PRESS Pb0 OR Pb1 "
"TO GENERATE MPU EXCEPTIONS " );
MPU_Disable();
/* Flash memory */
MPU_ConfigureRegion( &flashInit );
/* SRAM */
MPU_ConfigureRegion( &sramInit );
/* SRAM, a 4k part with priviledged only access, this regions settings */
/* will override those of the previous region */
sramInit.regionNo = 2;
sramInit.baseAddress = RAM_MEM_BASE + 0x2000;
sramInit.size = mpuRegionSize4Kb;
sramInit.accessPermission = mpuRegionApPRw;
MPU_ConfigureRegion( &sramInit );
/* LCD, priviledged only access */
peripheralInit.regionNo = 3;
peripheralInit.baseAddress = LCD_BASE;
peripheralInit.size = mpuRegionSize128b;
peripheralInit.accessPermission = mpuRegionApPRw;
MPU_ConfigureRegion( &peripheralInit );
MPU_Enable( MPU_CTRL_PRIVDEFENA ); /* Full access to default memory map */
/* in priviledged state */
i = 0;
while ( 1 )
{
SegmentLCD_Number( i ); /* Count on numeric diplay */
i = ( i + 1 ) % 101;
RTCDRV_Delay( 150 , false);
if ( PB0_PUSHED() )
{
BullsEye( 1 );
/* Generate an access violation in internal SRAM */
__set_CONTROL( 1 ); /* Enter User (unpriviledged) state */
*(volatile uint32_t *)(RAM_MEM_BASE + 0x2000) = 1;
BullsEye( 0 );
}
if ( PB1_PUSHED() )
{
BullsEye( 1 );
/* Generate an access violation in LCD peripheral */
__set_CONTROL( 1 ); /* Enter User (unpriviledged) state */
BullsEye( 0 );
}
}
}
/**************************************************************************//**
* @brief Main function
*****************************************************************************/
int main(void)
{
int c;
MPU_RegionInit_TypeDef flashInit = MPU_INIT_FLASH_DEFAULT;
MPU_RegionInit_TypeDef sramInit = MPU_INIT_SRAM_DEFAULT;
MPU_RegionInit_TypeDef peripheralInit = MPU_INIT_PERIPHERAL_DEFAULT;
/* Chip revision alignment and errata fixes */
CHIP_Init();
/* Initialize DK board register access */
BSP_Init(BSP_INIT_DK_SPI);
/* If first word of user data page is non-zero, enable eA Profiler trace */
BSP_TraceProfilerSetup();
/* Enable printf on RS232 port - this example only supports LEUART */
RETARGET_SerialInit();
RETARGET_SerialCrLf(1);
printf("\nEFM32 MPU access violation example.\n"
"Hit lowercase 'x' to force access violations.\n");
MPU_Disable();
/* Flash memory */
MPU_ConfigureRegion( &flashInit );
/* SRAM */
MPU_ConfigureRegion( &sramInit );
/* SRAM, a 4k part with priviledged only access, this regions settings */
/* will override those of the previous region */
sramInit.regionNo = 2;
sramInit.baseAddress = RAM_MEM_BASE + 0x2000;
sramInit.size = mpuRegionSize4Kb;
sramInit.accessPermission = mpuRegionApPRw;
MPU_ConfigureRegion( &sramInit );
/* LEUART, priviledged only access */
peripheralInit.regionNo = 3;
peripheralInit.baseAddress = LEUART1_BASE;
peripheralInit.size = mpuRegionSize128b;
peripheralInit.accessPermission = mpuRegionApPRw;
MPU_ConfigureRegion( &peripheralInit );
MPU_Enable( MPU_CTRL_PRIVDEFENA ); /* Full access to default memory map */
/* in priviledged state */
while (1)
{
EMU_EnterEM2(true);
/* Retrieve new character */
c = getchar();
if (c > 0)
{
if ( c == 'x' )
{
/* Generate an access violation in LEUART1 peripheral */
__set_CONTROL( 1 ); /* Enter User (unpriviledged) state */
putchar( c );
/* MemManage_Handler() will set back to priviledged state */
/* Generate an access violation in internal SRAM */
__set_CONTROL( 1 ); /* Enter User (unpriviledged) state */
*(volatile uint32_t *)(RAM_MEM_BASE + 0x2000) = 1;
/* MemManage_Handler() will set back to priviledged state */
}
else
{
/* Echo character */
putchar(c);
}
}
/* Most terminals issue CR when pressing enter, add LF */
if (c == '\r')
{
putchar('\n');
}
}
}
/* Application initialization */
static void USB_DeviceApplicationInit(void)
{
uint8_t irqNumber;
#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)
uint8_t usbDeviceEhciIrq[] = USBHS_IRQS;
irqNumber = usbDeviceEhciIrq[CONTROLLER_ID - kUSB_ControllerEhci0];
CLOCK_EnableUsbhs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk));
USB_EhciPhyInit(CONTROLLER_ID, BOARD_XTAL0_CLK_HZ);
#endif
#if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0U)
uint8_t usbDeviceKhciIrq[] = USB_IRQS;
irqNumber = usbDeviceKhciIrq[CONTROLLER_ID - kUSB_ControllerKhci0];
SystemCoreClockUpdate();
#if ((defined FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && (FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED))
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U);
#else
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk));
#endif /* FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED */
#endif
#if (defined(FSL_FEATURE_SOC_MPU_COUNT) && (FSL_FEATURE_SOC_MPU_COUNT > 0U))
MPU_Enable(MPU, 0);
#endif /* FSL_FEATURE_SOC_MPU_COUNT */
/*
* If the SOC has USB KHCI dedicated RAM, the RAM memory needs to be clear after
* the KHCI clock is enabled. When the demo uses USB EHCI IP, the USB KHCI dedicated
* RAM can not be used and the memory can't be accessed.
*/
#if (defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U))
#if (defined(FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS) && (FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS > 0U))
for (int i = 0; i < FSL_FEATURE_USB_KHCI_USB_RAM; i++)
{
((uint8_t *)FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS)[i] = 0x00U;
}
#endif /* FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS */
#endif /* FSL_FEATURE_USB_KHCI_USB_RAM */
/* Set composite device default state */
g_UsbDeviceComposite.speed = USB_SPEED_FULL;
g_UsbDeviceComposite.attach = 0U;
g_UsbDeviceComposite.deviceHandle = NULL;
/* Initialize the usb stack and class drivers */
if (kStatus_USB_Success != USB_DeviceInit(CONTROLLER_ID, USB_DeviceCallback, &g_UsbDeviceComposite.deviceHandle))
{
usb_echo("USB device composite demo init failed\r\n");
return;
}
else
{
usb_echo("USB device composite demo\r\n");
}
USB_DeviceHidKeyboardInit(&g_UsbDeviceComposite);
USB_DeviceHidMouseInit(&g_UsbDeviceComposite);
/* Install isr, set priority, and enable IRQ. */
NVIC_SetPriority((IRQn_Type)irqNumber, USB_DEVICE_INTERRUPT_PRIORITY);
NVIC_EnableIRQ((IRQn_Type)irqNumber);
/* Start USB device composite */
USB_DeviceRun(g_UsbDeviceComposite.deviceHandle);
}
/**
* \brief Set up a memory region.
*/
void _SetupMemoryRegion( void )
{
uint32_t dwRegionBaseAddr;
uint32_t dwRegionAttr;
memory_barrier();
/***************************************************
ITCM memory region --- Normal
START_Addr:- 0x00000000UL
END_Addr:- 0x00400000UL
****************************************************/
dwRegionBaseAddr =
ITCM_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_ITCM_REGION; // 1
dwRegionAttr =
MPU_AP_PRIVILEGED_READ_WRITE |
MPU_CalMPURegionSize(ITCM_END_ADDRESS - ITCM_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
Internal flash memory region --- Normal read-only
(update to Strongly ordered in write accesses)
START_Addr:- 0x00400000UL
END_Addr:- 0x00600000UL
******************************************************/
dwRegionBaseAddr =
IFLASH_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_IFLASH_REGION; //2
dwRegionAttr =
MPU_AP_READONLY |
INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
MPU_CalMPURegionSize(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
DTCM memory region --- Normal
START_Addr:- 0x20000000L
END_Addr:- 0x20400000UL
******************************************************/
/* DTCM memory region */
dwRegionBaseAddr =
DTCM_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_DTCM_REGION; //3
dwRegionAttr =
MPU_AP_PRIVILEGED_READ_WRITE |
MPU_CalMPURegionSize(DTCM_END_ADDRESS - DTCM_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
SRAM Cacheable memory region --- Normal
START_Addr:- 0x20400000UL
END_Addr:- 0x2043FFFFUL
******************************************************/
/* SRAM memory region */
dwRegionBaseAddr =
SRAM_FIRST_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_SRAM_REGION_1; //4
dwRegionAttr =
MPU_AP_FULL_ACCESS |
INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
MPU_CalMPURegionSize(SRAM_FIRST_END_ADDRESS - SRAM_FIRST_START_ADDRESS)
| MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
Internal SRAM second partition memory region --- Normal
START_Addr:- 0x20440000UL
END_Addr:- 0x2045FFFFUL
******************************************************/
/* SRAM memory region */
dwRegionBaseAddr =
SRAM_SECOND_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_SRAM_REGION_2; //5
dwRegionAttr =
MPU_AP_FULL_ACCESS |
INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
MPU_CalMPURegionSize(SRAM_SECOND_END_ADDRESS - SRAM_SECOND_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
Peripheral memory region --- DEVICE Shareable
START_Addr:- 0x40000000UL
END_Addr:- 0x5FFFFFFFUL
******************************************************/
dwRegionBaseAddr =
PERIPHERALS_START_ADDRESS |
MPU_REGION_VALID |
MPU_PERIPHERALS_REGION; //6
dwRegionAttr = MPU_AP_FULL_ACCESS |
MPU_REGION_EXECUTE_NEVER |
SHAREABLE_DEVICE_TYPE |
MPU_CalMPURegionSize(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS)
|MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
External EBI memory memory region --- Strongly Ordered
START_Addr:- 0x60000000UL
END_Addr:- 0x6FFFFFFFUL
******************************************************/
dwRegionBaseAddr =
EXT_EBI_START_ADDRESS |
MPU_REGION_VALID |
MPU_EXT_EBI_REGION;
dwRegionAttr =
MPU_AP_FULL_ACCESS |
/* External memory Must be defined with 'Device' or 'Strongly Ordered'
attribute for write accesses (AXI) */
STRONGLY_ORDERED_SHAREABLE_TYPE |
MPU_CalMPURegionSize(EXT_EBI_END_ADDRESS - EXT_EBI_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
SDRAM Cacheable memory region --- Normal
START_Addr:- 0x70000000UL
END_Addr:- 0x7FFFFFFFUL
******************************************************/
dwRegionBaseAddr =
SDRAM_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_SDRAM_REGION; //7
dwRegionAttr =
MPU_AP_FULL_ACCESS |
INNER_NORMAL_WB_RWA_TYPE( SHAREABLE ) |
MPU_CalMPURegionSize(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
QSPI memory region --- Strongly ordered
START_Addr:- 0x80000000UL
END_Addr:- 0x9FFFFFFFUL
******************************************************/
dwRegionBaseAddr =
QSPI_START_ADDRESS |
MPU_REGION_VALID |
MPU_QSPIMEM_REGION; //8
dwRegionAttr =
MPU_AP_FULL_ACCESS |
STRONGLY_ORDERED_SHAREABLE_TYPE |
MPU_CalMPURegionSize(QSPI_END_ADDRESS - QSPI_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
USB RAM Memory region --- Device
START_Addr:- 0xA0100000UL
END_Addr:- 0xA01FFFFFUL
******************************************************/
dwRegionBaseAddr =
USBHSRAM_START_ADDRESS |
MPU_REGION_VALID |
MPU_USBHSRAM_REGION; //9
dwRegionAttr =
MPU_AP_FULL_ACCESS |
MPU_REGION_EXECUTE_NEVER |
SHAREABLE_DEVICE_TYPE |
MPU_CalMPURegionSize(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/* Enable the memory management fault , Bus Fault, Usage Fault exception */
SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk
| SCB_SHCSR_USGFAULTENA_Msk);
/* Enable the MPU region */
MPU_Enable( MPU_ENABLE | MPU_PRIVDEFENA);
memory_sync();
}
int test_sdhc(void) {
#if TEST_SDCARD
if(CLOCK_GetBusClkFreq() < SD_CLOCK_25MHZ) {
PRINT("skipping SDHC test, bus clock frequency %d is lower than required %d\r\n",CLOCK_GetBusClkFreq(), SD_CLOCK_25MHZ);
return;
}
init_sdhc_pins();
FRESULT error;
DIR directory; /* Directory object */
FILINFO fileInformation;
UINT bytesWritten;
UINT bytesRead;
const TCHAR driverNumberBuffer[3U] = {SDDISK + '0', ':', '/'};
MPU_Enable(MPU, false);
PRINTF("\r\nFATFS example to demonstrate how to use FATFS with SD card.\r\n");
PRINTF("\r\nPlease insert a card into board.\r\n");
/* Wait the card to be inserted. */
while (!(GPIO_ReadPinInput(GPIOE, 7U))) {
}
PRINTF("Detected SD card inserted.\r\n");
/* Delat some time to make card stable. */
delay(1000U);
if (f_mount(&g_fileSystem, driverNumberBuffer, 0U)) {
PRINTF("Mount volume failed.\r\n");
return -1;
}
#if (_FS_RPATH >= 2U)
error = f_chdrive(&driverNumberBuffer[0U]);
if (error) {
PRINTF("Change drive failed.\r\n");
return -1;
}
#endif
#if _USE_MKFS
PRINTF("\r\nMake file system......The time may be long if the card capacity is big.\r\n");
if (f_mkfs(driverNumberBuffer, 1U, 0U))
{
PRINTF("Make file system failed.\r\n");
return -1;
}
#endif /* _USE_MKFS */
FIL testFileObject;
PRINTF("\r\nRead from static test file\r\n");
error = f_open(&testFileObject, _T("/test.txt"), FA_READ);
if (error) {
PRINTF("Open file failed (%d).\r\n", error);
return -1;
}
memset(g_bufferRead, 0U, sizeof(g_bufferRead));
error = f_read(&testFileObject, g_bufferRead, sizeof(g_bufferRead), &bytesRead);
if (error) {
PRINTF("Read file failed. \r\n");
}
PRINTF("bytes read: %d\r\n", bytesRead);
PRINTF("----\r\n");
PRINTF("%s", g_bufferRead);
PRINTF("----\r\n");
if (f_close(&testFileObject)) {
PRINTF("\r\nClose file failed.\r\n");
return -1;
}
PRINTF("\r\nCreate directory......\r\n");
error = f_mkdir(_T("/dir_1"));
if (error) {
if (error == FR_EXIST) {
PRINTF("Directory exists.\r\n");
} else {
PRINTF("Make directory failed.\r\n");
return -1;
}
}
PRINTF("\r\nCreate a file in that directory......\r\n");
error = f_open(&g_fileObject, _T("/dir_1/f_1.dat"), (FA_WRITE | FA_READ | FA_CREATE_ALWAYS));
if (error) {
if (error == FR_EXIST) {
PRINTF("File exists.\r\n");
} else {
PRINTF("Open file failed.\r\n");
return -1;
}
}
PRINTF("\r\nCreate a directory in that directory......\r\n");
error = f_mkdir(_T("/dir_1/dir_2"));
if (error) {
if (error == FR_EXIST) {
PRINTF("Directory exists.\r\n");
} else {
PRINTF("Directory creation failed.\r\n");
return -1;
}
}
PRINTF("\r\nList the file in that directory......\r\n");
if (f_opendir(&directory, "/dir_1")) {
PRINTF("Open directory failed.\r\n");
return -1;
}
for (;;) {
error = f_readdir(&directory, &fileInformation);
/* To the end. */
if ((error != FR_OK) || (fileInformation.fname[0U] == 0U)) {
break;
}
if (fileInformation.fname[0] == '.') {
continue;
}
if (fileInformation.fattrib & AM_DIR) {
PRINTF("Directory file : %s.\r\n", fileInformation.fname);
} else {
PRINTF("General file : %s.\r\n", fileInformation.fname);
}
}
memset(g_bufferWrite, 'a', sizeof(g_bufferWrite));
g_bufferWrite[BUFFER_SIZE - 2U] = '\r';
g_bufferWrite[BUFFER_SIZE - 1U] = '\n';
PRINTF("\r\nWrite/read file ...\r\n");
PRINTF("\r\nWrite to above created file.\r\n");
error = f_write(&g_fileObject, g_bufferWrite, sizeof(g_bufferWrite), &bytesWritten);
if ((error) || (bytesWritten != sizeof(g_bufferWrite))) {
PRINTF("Write file failed. \r\n");
return -1;
}
/* Move the file pointer */
if (f_lseek(&g_fileObject, 0U)) {
PRINTF("Set file pointer position failed. \r\n");
return -1;
}
PRINTF("Read from above created file.\r\n");
memset(g_bufferRead, 0U, sizeof(g_bufferRead));
error = f_read(&g_fileObject, g_bufferRead, sizeof(g_bufferRead), &bytesRead);
if ((error) || (bytesRead != sizeof(g_bufferRead))) {
PRINTF("Read file failed. \r\n");
return -1;
}
PRINTF("Compare the read/write content......\r\n");
if (memcmp(g_bufferWrite, g_bufferRead, sizeof(g_bufferWrite))) {
PRINTF("Compare read/write content isn't consistent.\r\n");
return -1;
}
PRINTF("The read/write content is consistent.\r\n");
PRINTF("\r\nThe example will not read/write file again.\r\n");
if (f_close(&g_fileObject)) {
PRINTF("\r\nClose file failed.\r\n");
return -1;
}
#endif
return 0;
}
/**
* \brief Setup a memory region.
*/
static void _SetupMPU(void)
{
uint32_t dwRegionBaseAddr;
uint32_t dwRegionAttr;
/* Internal flash privilege memory region */
dwRegionBaseAddr = IFLASH_PRIVILEGE_START_ADDRESS |
MPU_REGION_VALID |
MPU_PRIVILEGED_FLASH_REGION;
dwRegionAttr = MPU_AP_FULL_ACCESS |
MPU_CalMPURegionSize(IFLASH_PRIVILEGE_END_ADDRESS -
IFLASH_PRIVILEGE_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
/* Internal flash unprivileged memory region */
dwRegionBaseAddr = IFLASH_START_ADDRESS |
MPU_REGION_VALID |
MPU_UNPRIVILEGED_FLASH_REGION;
dwRegionAttr = MPU_AP_READONLY |
MPU_CalMPURegionSize(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
/* SRAM memory unprivileged region */
dwRegionBaseAddr = MPU_SRAM_UNPRIVILEGE_START_ADDRESS |
MPU_REGION_VALID |
MPU_UNPRIVILEGED_RAM_REGION;
dwRegionAttr = MPU_AP_FULL_ACCESS |
INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE) |
MPU_CalMPURegionSize(MPU_SRAM_UNPRIVILEGE_END_ADDRESS -
MPU_SRAM_UNPRIVILEGE_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
/* SRAM memory privilege region */
dwRegionBaseAddr = MPU_SRAM_PRIVILEGE_START_ADDRESS |
MPU_REGION_VALID |
MPU_PRIVILEGE_RAM_REGION;
dwRegionAttr = MPU_AP_FULL_ACCESS |
INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE ) |
MPU_CalMPURegionSize(MPU_SRAM_PRIVILEGE_END_ADDRESS -
MPU_SRAM_PRIVILEGE_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
/* SRAM memory privilege region */
dwRegionBaseAddr = MPU_SRAM_PRIVILEGE2_START_ADDRESS |
MPU_REGION_VALID |
MPU_PRIVILEGE_RAM_REGION_2;
dwRegionAttr = MPU_AP_FULL_ACCESS |
INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE ) |
MPU_CalMPURegionSize(MPU_SRAM_PRIVILEGE2_END_ADDRESS -
MPU_SRAM_PRIVILEGE2_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
/* Peripheral memory region */
dwRegionBaseAddr = MPU_PERIPHERALS_START_ADDRESS_0 |
MPU_REGION_VALID |
MPU_PERIPHERALS_REGION_0;
dwRegionAttr = MPU_AP_FULL_ACCESS |
MPU_REGION_EXECUTE_NEVER |
MPU_CalMPURegionSize(MPU_PERIPHERALS_END_ADDRESS_0 -
MPU_PERIPHERALS_START_ADDRESS_0) |
MPU_REGION_ENABLE;
MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
/* Peripheral memory region */
dwRegionBaseAddr = MPU_PERIPHERALS_START_ADDRESS_1 |
MPU_REGION_VALID |
MPU_PERIPHERALS_REGION_1;
dwRegionAttr = MPU_AP_FULL_ACCESS |
MPU_REGION_EXECUTE_NEVER |
1 << MPU_RASR_SRD_Pos |
MPU_CalMPURegionSize(MPU_PERIPHERALS_END_ADDRESS_1 -
MPU_PERIPHERALS_START_ADDRESS_1) |
MPU_REGION_ENABLE;
MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
/* Sub Peripheral memory region */
dwRegionBaseAddr = MPU_PIOC_PERIPHERALS_REGION_START_ADDRESS |
MPU_REGION_VALID |
MPU_PIOC_REGION_REGION;
dwRegionAttr = MPU_AP_FULL_ACCESS |
MPU_REGION_EXECUTE_NEVER |
MPU_CalMPURegionSize(MPU_PIOC_PERIPHERALS_REGION_END_ADDRESS -
MPU_PIOC_PERIPHERALS_REGION_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
/* Enable the memory management fault exception */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Enable the MPU region */
MPU_Enable(MPU_ENABLE | MPU_PRIVDEFENA);
}
