void
ar9300GetSpectralParams(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss)
{
u_int32_t val;
struct ath_hal_9300 *ahp = AH9300(ah);
HAL_POWER_MODE pwrmode = ahp->ah_powerMode;
if (AR_SREV_WASP(ah) && (pwrmode == HAL_PM_FULL_SLEEP)) {
ar9300SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE);
}
val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
ss->ss_fft_period = MS(val, AR_PHY_SPECTRAL_SCAN_FFT_PERIOD);
ss->ss_period = MS(val, AR_PHY_SPECTRAL_SCAN_PERIOD);
ss->ss_count = MS(val, AR_PHY_SPECTRAL_SCAN_COUNT);
ss->ss_short_report = MS(val, AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
if (AR_SREV_WASP(ah) && (pwrmode == HAL_PM_FULL_SLEEP)) {
ar9300SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
}
}
/*
* Read 16 bits of data from offset into *data
*/
HAL_BOOL
ar5416EepromRead(struct ath_hal *ah, u_int off, u_int16_t *data)
{
(void)OS_REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
if (!ath_hal_wait(ah, AR_EEPROM_STATUS_DATA, AR_EEPROM_STATUS_DATA_BUSY
| AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, AH_WAIT_TIMEOUT))
{
return AH_FALSE;
}
*data = MS(OS_REG_READ(ah, AR_EEPROM_STATUS_DATA), AR_EEPROM_STATUS_DATA_VAL);
return AH_TRUE;
}
/*
* Once configured for I/O - get input lines
*/
u_int32_t
ar9300GpioGet(struct ath_hal *ah, u_int32_t gpio)
{
u_int32_t gpio_in;
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
if (gpio >= AH_PRIVATE(ah)->ah_caps.halNumGpioPins) {
return 0xffffffff;
}
gpio_in = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN));
return (MS(gpio_in, AR_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
}
/*
* Process an RX descriptor, and return the status to the caller.
* Copy some hardware specific items into the software portion
* of the descriptor.
*
* NB: the caller is responsible for validating the memory contents
* of the descriptor (e.g. flushing any cached copy).
*/
HAL_STATUS
ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
u_int32_t pa, struct ath_desc *nds)
{
struct ar5212_desc *ads = AR5212DESC(ds);
struct ar5212_desc *ands = AR5212DESC(nds);
if ((ads->ds_rxstatus1 & AR_Done) == 0)
return HAL_EINPROGRESS;
/*
* Given the use of a self-linked tail be very sure that the hw is
* done with this descriptor; the hw may have done this descriptor
* once and picked it up again...make sure the hw has moved on.
*/
if ((ands->ds_rxstatus1&AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
return HAL_EINPROGRESS;
ds->ds_rxstat.rs_datalen = ads->ds_rxstatus0 & AR_DataLen;
ds->ds_rxstat.rs_tstamp = MS(ads->ds_rxstatus1, AR_RcvTimestamp);
ds->ds_rxstat.rs_status = 0;
/* XXX what about KeyCacheMiss? */
ds->ds_rxstat.rs_rssi = MS(ads->ds_rxstatus0, AR_RcvSigStrength);
if (ads->ds_rxstatus1 & AR_KeyIdxValid)
ds->ds_rxstat.rs_keyix = MS(ads->ds_rxstatus1, AR_KeyIdx);
else
ds->ds_rxstat.rs_keyix = HAL_RXKEYIX_INVALID;
/* NB: caller expected to do rate table mapping */
ds->ds_rxstat.rs_rate = MS(ads->ds_rxstatus0, AR_RcvRate);
ds->ds_rxstat.rs_antenna = MS(ads->ds_rxstatus0, AR_RcvAntenna);
ds->ds_rxstat.rs_more = (ads->ds_rxstatus0 & AR_More) ? 1 : 0;
if ((ads->ds_rxstatus1 & AR_FrmRcvOK) == 0) {
/*
* These four bits should not be set together. The
* 5212 spec states a Michael error can only occur if
* DecryptCRCErr not set (and TKIP is used). Experience
* indicates however that you can also get Michael errors
* when a CRC error is detected, but these are specious.
* Consequently we filter them out here so we don't
* confuse and/or complicate drivers.
*/
if (ads->ds_rxstatus1 & AR_CRCErr)
ds->ds_rxstat.rs_status |= HAL_RXERR_CRC;
else if (ads->ds_rxstatus1 & AR_PHYErr) {
u_int phyerr;
ds->ds_rxstat.rs_status |= HAL_RXERR_PHY;
phyerr = MS(ads->ds_rxstatus1, AR_PHYErrCode);
ds->ds_rxstat.rs_phyerr = phyerr;
if ((!AH5212(ah)->ah_hasHwPhyCounters) &&
(phyerr != HAL_PHYERR_RADAR))
ar5212AniPhyErrReport(ah, &ds->ds_rxstat);
} else if (ads->ds_rxstatus1 & AR_DecryptCRCErr)
ds->ds_rxstat.rs_status |= HAL_RXERR_DECRYPT;
else if (ads->ds_rxstatus1 & AR_MichaelErr)
ds->ds_rxstat.rs_status |= HAL_RXERR_MIC;
}
return HAL_OK;
}
/* This function is executed by the second task that is set up
* in the function firsttask() by a call to nosTaskCreate()
*/
void secondtask(void *arg)
{
char *name = (char*) arg;
for(;;)
{
/* print string: "Task 2" */
nosPrintf1("%s\n", name);
/* sleep (=do nothing) for two seconds */
nosTaskSleep(MS(2000));
}
}
static void
ar5210_decode_txdesc(struct if_ath_alq_payload *a)
{
struct ar5210_desc txc;
/* XXX assumes txs is smaller than PAYLOAD_LEN! */
memcpy(&txc, &a->payload, sizeof(struct ar5210_desc));
printf("[%u.%06u] [%llu] TXD\n",
(unsigned int) be32toh(a->hdr.tstamp_sec),
(unsigned int) be32toh(a->hdr.tstamp_usec),
(unsigned long long) be64toh(a->hdr.threadid));
printf(" link=0x%08x, data=0x%08x\n",
txc.ds_link,
txc.ds_data);
/* ds_ctl0 */
printf(" Frame Len=%d\n", txc.ds_ctl0 & AR_FrameLen);
printf(" TX Rate=0x%02x, RtsEna=%d, ClrDstMask=%d AntModeXmit=0x%02x\n",
MS(txc.ds_ctl0, AR_XmitRate),
MF(txc.ds_ctl0, AR_RTSCTSEnable),
MF(txc.ds_ctl0, AR_ClearDestMask),
MF(txc.ds_ctl0, AR_AntModeXmit));
printf(" FrmType=0x%02x, TxIntrReq=%d\n",
MS(txc.ds_ctl0, AR_FrmType),
MF(txc.ds_ctl0, AR_TxInterReq));
printf(" LongPkt=%d\n", MF(txc.ds_ctl0, AR_LongPkt));
/* ds_ctl1 */
printf(" BufLen=%d, TxMore=%d, EncryptKeyIdx=%d, RtsDuration=%d\n",
txc.ds_ctl1 & AR_BufLen,
MF(txc.ds_ctl1, AR_More),
MS(txc.ds_ctl1, AR_EncryptKeyIdx),
MS(txc.ds_ctl1, AR_RTSDuration));
printf("\n ------ \n");
}
/*
* Set the GPIO Interrupt
*/
void
ar5416GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
{
uint32_t val;
HALASSERT(gpio < AR_NUM_GPIO);
/* XXX bounds check gpio */
val = MS(OS_REG_READ(ah, AR_GPIO_INTR_OUT), AR_GPIO_INTR_CTRL);
if (ilevel) /* 0 == interrupt on pin high */
val &= ~AR_GPIO_BIT(gpio);
else /* 1 == interrupt on pin low */
val |= AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_OUT, AR_GPIO_INTR_CTRL, val);
/* Change the interrupt mask. */
val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE), AR_INTR_GPIO);
val |= AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_GPIO, val);
val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK), AR_INTR_GPIO);
val |= AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK, AR_INTR_GPIO, val);
}
void tcpClientThread(void* arg)
{
int sock = (long)arg;
int i;
nosPrintf("in tcp client\n");
for (i = 0; i < 5; i++) {
write(sock, "Hello!\n", 7);
posTaskSleep(MS(1000));
}
close(sock);
}
/*
* Once configured for I/O - get input lines
*/
u_int32_t
ar7010GpioGet(struct ath_hal *ah, u_int32_t gpio)
{
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
if (gpio >= AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins) {
return 0xffffffff;
}
/* Read output value for all gpio's, shift it left, and verify whether a
* specific gpio bit is set.
*/
return (MS(OS_REG_READ(ah, AR7010_GPIO_IN), AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
}
void
ar9280_olpc_init(struct athn_softc *sc)
{
uint32_t reg;
int i;
/* Save original Tx gain values. */
for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
sc->tx_gain_tbl[i] = MS(reg, AR_PHY_TX_GAIN);
}
/* Initial Tx gain temperature compensation. */
sc->tcomp = 0;
}
/* This function is executed by the second task that is set up
* in the function firsttask() by a call to nosTaskCreate()
*/
void task2(void *arg)
{
/* avoid compiler warning */
(void) arg;
for(;;)
{
/* call function */
incrementCounter(2);
/* do something here and waste some time */
posTaskSleep(MS(300));
}
}
/* Applies for first msdu in chain, before altering it. */
static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb)
{
struct htt_rx_desc *rxd;
enum rx_msdu_decap_format fmt;
rxd = (void *)skb->data - sizeof(*rxd);
fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
RX_MSDU_START_INFO1_DECAP_FORMAT);
if (fmt == RX_MSDU_DECAP_RAW)
return (void *)skb->data;
else
return (void *)skb->data - RX_HTT_HDR_STATUS_LEN;
}
static void
ar2133GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
{
struct ath_hal_5416 *ahp = AH5416(ah);
int16_t nf;
switch (ahp->ah_rx_chainmask) {
case 0x7:
nf = MS(OS_REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1);
HALDEBUG(ah, HAL_DEBUG_NFCAL,
"NF calibrated [ctl] [chain 2] is %d\n", nf);
nfarray[4] = nf;
nf = MS(OS_REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1);
HALDEBUG(ah, HAL_DEBUG_NFCAL,
"NF calibrated [ext] [chain 2] is %d\n", nf);
nfarray[5] = nf;
/* fall thru... */
case 0x3:
case 0x5:
nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1);
HALDEBUG(ah, HAL_DEBUG_NFCAL,
"NF calibrated [ctl] [chain 1] is %d\n", nf);
nfarray[2] = nf;
nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1);
HALDEBUG(ah, HAL_DEBUG_NFCAL,
"NF calibrated [ext] [chain 1] is %d\n", nf);
nfarray[3] = nf;
/* fall thru... */
case 0x1:
nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1);
HALDEBUG(ah, HAL_DEBUG_NFCAL,
"NF calibrated [ctl] [chain 0] is %d\n", nf);
nfarray[0] = nf;
nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1);
HALDEBUG(ah, HAL_DEBUG_NFCAL,
"NF calibrated [ext] [chain 0] is %d\n", nf);
nfarray[1] = nf;
break;
}
}
/*
* Once configured for I/O - set output lines
*/
HAL_BOOL
ar5416GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
{
uint32_t reg;
HALASSERT(gpio < AR_NUM_GPIO);
reg = MS(OS_REG_READ(ah, AR_GPIO_INTR_OUT), AR_GPIO_OUT_VAL);
if (val & 1)
reg |= AR_GPIO_BIT(gpio);
else
reg &= ~AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_OUT, AR_GPIO_OUT_VAL, reg);
return AH_TRUE;
}
uint8_t
r12a_rx_radiotap_flags(const void *buf)
{
const struct r92c_rx_stat *stat = buf;
uint8_t flags, rate;
if (!(stat->rxdw4 & htole32(R12A_RXDW4_SPLCP)))
return (0);
rate = MS(le32toh(stat->rxdw3), R92C_RXDW3_RATE);
if (RTWN_RATE_IS_CCK(rate))
flags = IEEE80211_RADIOTAP_F_SHORTPRE;
else
flags = IEEE80211_RADIOTAP_F_SHORTGI;
return (flags);
}
void Status::tick()
{
// Si on a de la place sur le buffer de sortie, alors on accepte
if (Serial.availableForWrite() < sizeof(struct Payload)) {
// Il faut attendre pendant au moins ce temps
this->nextTick = UTime::now() + (sizeof(struct Payload) + 2) * CHAR_XMIT_DELAY;
return;
}
sendStatus();
if (motor.isMoving() || filterWheelMotor.isMoving()) {
this->nextTick += MS(250);
} else {
this->nextTick += LongDuration::seconds(10);
}
}
void rx_task(void * ignore)
{
int cnt = 0;
while (1) {
if (uart_gets(buf) <= 0)
continue;
PORTB ^= _BV(PB0);
if (!strncmp(buf, "+BTINQ: ", 8)) {
char * x = strchr(&buf[8], ',');
if (x == NULL) continue;
*(x+1) = 0;
//strcpy(ptr[cnt], &buf[8]);
uart_puts("AT+BTSDP=");
uart_puts(&buf[8]);
uart_puts("2\r");
posTaskSleep(MS(500));
PORTB ^= _BV(PB0);
posTaskSleep(MS(500));
PORTB ^= _BV(PB0);
posTaskSleep(MS(500));
PORTB ^= _BV(PB0);
}
}
}
/* This function is executed by the second task that is set up
* in the function firsttask() by a call to nosTaskCreate()
*/
void secondtask(void *arg)
{
char *name = (char*) arg;
for(;;)
{
/* print string: "Task 2" */
posTaskSchedLock();
printf("%s\n", name);
posTaskSchedUnlock();
/* sleep (=do nothing) for two seconds */
posTaskSleep(MS(2000));
}
}
int16_t ar9300GetExtChanNF(struct ath_hal *ah)
{
int16_t nf;
struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) {
/* Noise floor calibration value is ready */
nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
} else {
/* NF calibration is not done, return nominal value */
nf = ahpriv->nfp->nominal;
}
if (nf & 0x100)
nf = (0 - ((nf ^ 0x1ff) + 1));
return nf;
}
static void
ar5212_decode_rxstatus(struct if_ath_alq_payload *a)
{
struct ar5212_desc rxs;
/* XXX assumes rxs is smaller than PAYLOAD_LEN! */
memcpy(&rxs, &a->payload, sizeof(struct ar5212_desc));
printf("[%u] [%llu] RXSTATUS\n",
(unsigned int) be32toh(a->hdr.tstamp),
(unsigned long long) be64toh(a->hdr.threadid));
printf(" link=0x%08x, data=0x%08x, ctl0=0x%08x, ctl2=0x%08x\n",
rxs.ds_link,
rxs.ds_data,
rxs.ds_ctl0,
rxs.ds_ctl1);
/* ds_rxstatus0 */
printf(" DataLen=%d, ArMore=%d, DecompCrcError=%d, RcvRate=0x%02x\n",
rxs.ds_rxstatus0 & AR_DataLen,
MF(rxs.ds_rxstatus0, AR_More),
MF(rxs.ds_rxstatus0, AR_DecompCRCErr),
MS(rxs.ds_rxstatus0, AR_RcvRate));
printf(" RSSI=%d, RcvAntenna=0x%x\n",
MS(rxs.ds_rxstatus0, AR_RcvSigStrength),
MS(rxs.ds_rxstatus0, AR_RcvAntenna));
/* ds_rxstatus1 */
printf(" RxDone=%d, RxFrameOk=%d, CrcErr=%d, DecryptCrcErr=%d\n",
MF(rxs.ds_rxstatus1, AR_Done),
MF(rxs.ds_rxstatus1, AR_FrmRcvOK),
MF(rxs.ds_rxstatus1, AR_CRCErr),
MF(rxs.ds_rxstatus1, AR_DecryptCRCErr));
printf(" PhyErr=%d, MichaelErr=%d, KeyIdxValid=%d\n",
MF(rxs.ds_rxstatus1, AR_PHYErr),
MF(rxs.ds_rxstatus1, AR_MichaelErr),
MF(rxs.ds_rxstatus1, AR_KeyIdxValid));
/* If PHY error, print that out. Otherwise, the key index */
if (MF(rxs.ds_rxstatus1, AR_PHYErr))
printf(" PhyErrCode=0x%02x\n",
MS(rxs.ds_rxstatus1, AR_PHYErrCode));
else
printf(" KeyIdx=0x%02x\n",
MS(rxs.ds_rxstatus1, AR_KeyIdx));
printf(" KeyMiss=%d\n",
MF(rxs.ds_rxstatus1, AR_KeyCacheMiss));
printf(" Timetamp: 0x%05x\n",
MS(rxs.ds_rxstatus1, AR_RcvTimestamp));
printf("\n ------\n");
}
uint8_t
r12a_tx_radiotap_flags(const void *buf)
{
const struct r12a_tx_desc *txd = buf;
uint8_t flags, rate;
if (!(txd->txdw5 & htole32(R12A_TXDW5_DATA_SHORT)))
return (0);
rate = MS(le32toh(txd->txdw4), R12A_TXDW4_DATARATE);
if (RTWN_RATE_IS_CCK(rate))
flags = IEEE80211_RADIOTAP_F_SHORTPRE;
else
flags = IEEE80211_RADIOTAP_F_SHORTGI;
return (flags);
}
uint32_t
r12a_c_cut_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr)
{
uint32_t pi_mode, val;
val = rtwn_bb_read(sc, R12A_HSSI_PARAM1(chain));
pi_mode = (val & R12A_HSSI_PARAM1_PI) ? 1 : 0;
rtwn_bb_setbits(sc, R12A_HSSI_PARAM2,
R12A_HSSI_PARAM2_READ_ADDR_MASK, addr);
rtwn_delay(sc, 20);
val = rtwn_bb_read(sc, pi_mode ? R12A_HSPI_READBACK(chain) :
R12A_LSSI_READBACK(chain));
return (MS(val, R92C_LSSI_READBACK_DATA));
}
/* This function is executed by the first task.
*/
void task1(void *arg)
{
int i = 0;
/* avoid compiler warning */
(void) arg;
for(;;)
{
/* call function */
sharedResource(1);
/* do something here and waste some time */
posTaskSleep(MS(100 + i*20));
if (++i == 5) i = 0;
}
}
void
ar9280olcInit(struct ath_hal *ah)
{
uint32_t i;
/* Only do OLC if it's enabled for this chipset */
if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL))
return;
HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Setting up TX gain tables.\n", __func__);
for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
AH9280(ah)->originalGain[i] = MS(OS_REG_READ(ah,
AR_PHY_TX_GAIN_TBL1 + i * 4), AR_PHY_TX_GAIN);
AH9280(ah)->PDADCdelta = 0;
}
static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
{
(void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
if (!ath9k_hw_wait(ah,
AR_EEPROM_STATUS_DATA,
AR_EEPROM_STATUS_DATA_BUSY |
AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
AH_WAIT_TIMEOUT)) {
return false;
}
*data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
AR_EEPROM_STATUS_DATA_VAL);
return true;
}
static void
radar_fft_search_report_parse(struct ath_dfs *dfs, const char *buf, size_t len,
struct rx_search_fft_report *rsfr)
{
uint32_t rs[2];
/* Drop out if we have < 2 DWORDs available */
if (len < sizeof(rs)) {
DFS_DPRINTK(dfs, ATH_DEBUG_DFS_PHYERR |
ATH_DEBUG_DFS_PHYERR_SUM,
"%s: len (%d) < expected (%d)!\n",
__func__,
len,
sizeof(rs));
}
/*
* Since the TLVs may be unaligned for some reason
* we take a private copy into aligned memory.
* This enables us to use the HAL-like accessor macros
* into the DWORDs to access sub-DWORD fields.
*/
OS_MEMCPY(rs, buf, sizeof(rs));
rsfr->total_gain_db = MS(rs[SEARCH_FFT_REPORT_REG_1], SEARCH_FFT_REPORT_TOTAL_GAIN_DB);
rsfr->base_pwr_db = MS(rs[SEARCH_FFT_REPORT_REG_1], SEARCH_FFT_REPORT_BASE_PWR_DB);
rsfr->fft_chn_idx = MS(rs[SEARCH_FFT_REPORT_REG_1], SEARCH_FFT_REPORT_FFT_CHN_IDX);
rsfr->peak_sidx = sign_extend_32(MS(rs[SEARCH_FFT_REPORT_REG_1], SEARCH_FFT_REPORT_PEAK_SIDX), 12);
rsfr->relpwr_db = MS(rs[SEARCH_FFT_REPORT_REG_2], SEARCH_FFT_REPORT_RELPWR_DB);
rsfr->avgpwr_db = MS(rs[SEARCH_FFT_REPORT_REG_2], SEARCH_FFT_REPORT_AVGPWR_DB);
rsfr->peak_mag = MS(rs[SEARCH_FFT_REPORT_REG_2], SEARCH_FFT_REPORT_PEAK_MAG);
rsfr->num_str_bins_ib = MS(rs[SEARCH_FFT_REPORT_REG_2], SEARCH_FFT_REPORT_NUM_STR_BINS_IB);
DFS_DPRINTK(dfs, ATH_DEBUG_DFS_PHYERR,"%s: two 32 bit values are: %08x %08x\n", __func__, rs[0], rs[1]);
DFS_DPRINTK(dfs, ATH_DEBUG_DFS_PHYERR,"%s: rsfr->total_gain_db = %d\n", __func__, rsfr->total_gain_db);
DFS_DPRINTK(dfs, ATH_DEBUG_DFS_PHYERR,"%s: rsfr->base_pwr_db = %d\n", __func__, rsfr->base_pwr_db);
DFS_DPRINTK(dfs, ATH_DEBUG_DFS_PHYERR,"%s: rsfr->fft_chn_idx = %d\n", __func__, rsfr->fft_chn_idx);
DFS_DPRINTK(dfs, ATH_DEBUG_DFS_PHYERR,"%s: rsfr->peak_sidx = %d\n", __func__, rsfr->peak_sidx);
DFS_DPRINTK(dfs, ATH_DEBUG_DFS_PHYERR,"%s: rsfr->relpwr_db = %d\n", __func__, rsfr->relpwr_db);
DFS_DPRINTK(dfs, ATH_DEBUG_DFS_PHYERR,"%s: rsfr->avgpwr_db = %d\n", __func__, rsfr->avgpwr_db);
DFS_DPRINTK(dfs, ATH_DEBUG_DFS_PHYERR,"%s: rsfr->peak_mag = %d\n", __func__, rsfr->peak_mag);
DFS_DPRINTK(dfs, ATH_DEBUG_DFS_PHYERR,"%s: rsfr->num_str_bins_ib = %d\n", __func__, rsfr->num_str_bins_ib);
}
void ar9003_mci_check_gpm_offset(struct ath_hw *ah)
{
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
u32 offset;
/*
* This should only be called before "MAC Warm Reset" or "MCI Reset Rx".
*/
offset = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
if (mci->gpm_idx == offset)
return;
ath_dbg(common, MCI, "GPM cached write pointer mismatch %d %d\n",
mci->gpm_idx, offset);
mci->query_bt = true;
mci->need_flush_btinfo = true;
mci->gpm_idx = 0;
}
int net_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen)
{
UosFile* file = uosSlot2File(s);
if (optname == SO_RCVTIMEO) {
const struct timeval* tv = optval;
if (tv->tv_sec == 0 && tv->tv_usec == 0)
netSockTimeout(file, INFINITE);
else
netSockTimeout(file, MS(tv->tv_sec * 1000 + tv->tv_usec / 1000));
return 0;
}
return -1;
}
static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
{
struct ath_hw *ah = (struct ath_hw *) common->ah;
common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
if (!ath9k_hw_wait(ah,
AR_EEPROM_STATUS_DATA,
AR_EEPROM_STATUS_DATA_BUSY |
AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
AH_WAIT_TIMEOUT)) {
return false;
}
*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
AR_EEPROM_STATUS_DATA_VAL);
return true;
}
bool
ar9300_is_spectral_enabled(struct ath_hal *ah)
{
u_int32_t val;
struct ath_hal_9300 *ahp = AH9300(ah);
bool asleep = ahp->ah_chip_full_sleep;
if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
ar9300_set_power_mode(ah, HAL_PM_AWAKE, true);
}
val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, true);
}
return MS(val, AR_PHY_SPECTRAL_SCAN_ENABLE);
}