static int setup_i2s_protdesc(struct msp_protdesc *prot_desc) { prot_desc->rx_phase_mode = MSP_DUAL_PHASE; prot_desc->tx_phase_mode = MSP_DUAL_PHASE; prot_desc->rx_phase2_start_mode = MSP_PHASE2_START_MODE_FSYNC; prot_desc->tx_phase2_start_mode = MSP_PHASE2_START_MODE_FSYNC; prot_desc->rx_byte_order = MSP_BTF_MS_BIT_FIRST; prot_desc->tx_byte_order = MSP_BTF_MS_BIT_FIRST; prot_desc->tx_fsync_pol = MSP_FSYNC_POL(MSP_FSYNC_POL_ACT_LO); prot_desc->rx_fsync_pol = MSP_FSYNC_POL_ACT_LO << RFSPOL_SHIFT; prot_desc->rx_frame_len_1 = MSP_FRAME_LEN_1; prot_desc->rx_frame_len_2 = MSP_FRAME_LEN_1; prot_desc->tx_frame_len_1 = MSP_FRAME_LEN_1; prot_desc->tx_frame_len_2 = MSP_FRAME_LEN_1; prot_desc->rx_elem_len_1 = MSP_ELEM_LEN_16; prot_desc->rx_elem_len_2 = MSP_ELEM_LEN_16; prot_desc->tx_elem_len_1 = MSP_ELEM_LEN_16; prot_desc->tx_elem_len_2 = MSP_ELEM_LEN_16; prot_desc->rx_clk_pol = MSP_RISING_EDGE; prot_desc->tx_clk_pol = MSP_FALLING_EDGE; prot_desc->rx_data_delay = MSP_DELAY_0; prot_desc->tx_data_delay = MSP_DELAY_0; prot_desc->tx_half_word_swap = MSP_SWAP_NONE; prot_desc->rx_half_word_swap = MSP_SWAP_NONE; prot_desc->compression_mode = MSP_COMPRESS_MODE_LINEAR; prot_desc->expansion_mode = MSP_EXPAND_MODE_LINEAR; prot_desc->frame_sync_ignore = MSP_FSYNC_IGNORE; return 0; }
static void set_prot_desc_rx(struct ux500_msp *msp, struct msp_protdesc *protdesc, enum msp_data_size data_size) { u32 temp_reg = 0; temp_reg |= MSP_P2_ENABLE_BIT(protdesc->rx_phase_mode); temp_reg |= MSP_P2_START_MODE_BIT(protdesc->rx_phase2_start_mode); temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->rx_frame_len_1); temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->rx_frame_len_2); if (msp->def_elem_len) { temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->rx_elem_len_1); temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->rx_elem_len_2); } else { temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size); temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size); } temp_reg |= MSP_DATA_DELAY_BITS(protdesc->rx_data_delay); temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->rx_byte_order); temp_reg |= MSP_FSYNC_POL(protdesc->rx_fsync_pol); temp_reg |= MSP_DATA_WORD_SWAP(protdesc->rx_half_word_swap); temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->expansion_mode); temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore); writel(temp_reg, msp->registers + MSP_RCF); }
static int setup_pcm_protdesc(struct snd_soc_dai *dai, unsigned int fmt, struct msp_protdesc *prot_desc) { prot_desc->rx_phase_mode = MSP_SINGLE_PHASE; prot_desc->tx_phase_mode = MSP_SINGLE_PHASE; prot_desc->rx_phase2_start_mode = MSP_PHASE2_START_MODE_IMEDIATE; prot_desc->tx_phase2_start_mode = MSP_PHASE2_START_MODE_IMEDIATE; prot_desc->rx_byte_order = MSP_BTF_MS_BIT_FIRST; prot_desc->tx_byte_order = MSP_BTF_MS_BIT_FIRST; prot_desc->tx_fsync_pol = MSP_FSYNC_POL(MSP_FSYNC_POL_ACT_HI); prot_desc->rx_fsync_pol = MSP_FSYNC_POL_ACT_HI << RFSPOL_SHIFT; if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_A) { dev_dbg(dai->dev, "%s: DSP_A.\n", __func__); prot_desc->rx_clk_pol = MSP_RISING_EDGE; prot_desc->tx_clk_pol = MSP_FALLING_EDGE; prot_desc->rx_data_delay = MSP_DELAY_1; prot_desc->tx_data_delay = MSP_DELAY_1; } else { dev_dbg(dai->dev, "%s: DSP_B.\n", __func__); prot_desc->rx_clk_pol = MSP_FALLING_EDGE; prot_desc->tx_clk_pol = MSP_RISING_EDGE; prot_desc->rx_data_delay = MSP_DELAY_0; prot_desc->tx_data_delay = MSP_DELAY_0; } prot_desc->rx_half_word_swap = MSP_SWAP_NONE; prot_desc->tx_half_word_swap = MSP_SWAP_NONE; prot_desc->compression_mode = MSP_COMPRESS_MODE_LINEAR; prot_desc->expansion_mode = MSP_EXPAND_MODE_LINEAR; prot_desc->frame_sync_ignore = MSP_FSYNC_IGNORE; return 0; }