static void __init hdpu_fixup_eth_pdata(struct platform_device *pd) { struct mv643xx_eth_platform_data *eth_pd; eth_pd = pd->dev.platform_data; eth_pd->port_serial_control = mv64x60_read(&bh, MV643XX_ETH_PORT_SERIAL_CONTROL_REG(pd->id) & ~1); eth_pd->force_phy_addr = 1; eth_pd->phy_addr = pd->id; eth_pd->tx_queue_size = 400; eth_pd->rx_queue_size = 800; }
void __init plat_mem_setup(void) { unsigned int tmpword; board_time_init = momenco_time_init; _machine_restart = momenco_ocelot_restart; _machine_halt = momenco_ocelot_halt; pm_power_off = momenco_ocelot_power_off; /* Wired TLB entries */ setup_wired_tlb_entries(); /* shut down ethernet ports, just to be sure our memory doesn't get * corrupted by random ethernet traffic. */ MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); do {} while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); do {} while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); do {} while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); do {} while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0), MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1), MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); /* Turn off the Bit-Error LED */ OCELOT_FPGA_WRITE(0x80, CLR); tmpword = OCELOT_FPGA_READ(BOARDREV); if (tmpword < 26) printk("Momenco Ocelot-3: Board Assembly Rev. %c\n", 'A'+tmpword); else printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n", tmpword); tmpword = OCELOT_FPGA_READ(FPGA_REV); printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); tmpword = OCELOT_FPGA_READ(RESET_STATUS); printk("Reset reason: 0x%x\n", tmpword); switch (tmpword) { case 0x1: printk(" - Power-up reset\n"); break; case 0x2: printk(" - Push-button reset\n"); break; case 0x4: printk(" - cPCI bus reset\n"); break; case 0x8: printk(" - Watchdog reset\n"); break; case 0x10: printk(" - Software reset\n"); break; default: printk(" - Unknown reset cause\n"); } reset_reason = tmpword; OCELOT_FPGA_WRITE(0xff, RESET_STATUS); tmpword = OCELOT_FPGA_READ(CPCI_ID); printk("cPCI ID register: 0x%02x\n", tmpword); printk(" - Slot number: %d\n", tmpword & 0x1f); printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no"); printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no"); tmpword = OCELOT_FPGA_READ(BOARD_STATUS); printk("Board Status register: 0x%02x\n", tmpword); printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); printk(" - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1); /* Support for 128 MB memory */ add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM); }
void __init plat_mem_setup(void) { unsigned int tmpword; board_time_init = momenco_time_init; _machine_restart = momenco_jaguar_restart; _machine_halt = momenco_jaguar_halt; pm_power_off = momenco_jaguar_power_off; /* * initrd_start = (unsigned long)jaguar_initrd_start; * initrd_end = (unsigned long)jaguar_initrd_start + (ulong)jaguar_initrd_size; * initrd_below_start_ok = 1; */ wire_stupidity_into_tlb(); /* * shut down ethernet ports, just to be sure our memory doesn't get * corrupted by random ethernet traffic. */ MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8); MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8); while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff); while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff); MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0), MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1), MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2), MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1); /* Turn off the Bit-Error LED */ JAGUAR_FPGA_WRITE(0x80, CLR); tmpword = JAGUAR_FPGA_READ(BOARDREV); if (tmpword < 26) printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n", 'A'+tmpword); else printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n", tmpword); tmpword = JAGUAR_FPGA_READ(FPGA_REV); printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); tmpword = JAGUAR_FPGA_READ(RESET_STATUS); printk("Reset reason: 0x%x\n", tmpword); switch (tmpword) { case 0x1: printk(" - Power-up reset\n"); break; case 0x2: printk(" - Push-button reset\n"); break; case 0x8: printk(" - Watchdog reset\n"); break; case 0x10: printk(" - JTAG reset\n"); break; default: printk(" - Unknown reset cause\n"); } reset_reason = tmpword; JAGUAR_FPGA_WRITE(0xff, RESET_STATUS); tmpword = JAGUAR_FPGA_READ(BOARD_STATUS); printk("Board Status register: 0x%02x\n", tmpword); printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); /* 256MiB of RM9000x2 DDR */ // add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM); /* 128MiB of MV-64340 DDR */ // add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM); /* XXX Memory configuration should be picked up from PMON2k */ #ifdef CONFIG_JAGUAR_DMALOW printk("Jaguar ATX DMA-low mode set\n"); add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM); add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM); #else /* 128MiB of MV-64340 DDR RAM */ printk("Jaguar ATX DMA-low mode is not set\n"); add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM); #endif #ifdef GEMDEBUG_TRACEBUFFER { unsigned int tbControl; tbControl = 0 << 26 | /* post trigger delay 0 */ 0x2 << 16 | /* sequential trace mode */ // 0x0 << 16 | /* non-sequential trace mode */ // 0xf << 4 | /* watchpoints disabled */ 2 << 2 | /* armed */ 2 ; /* interrupt disabled */ printk ("setting tbControl = %08lx\n", tbControl); write_32bit_cp0_set1_register($22, tbControl); __asm__ __volatile__(".set noreorder\n\t" \ "nop; nop; nop; nop; nop; nop;\n\t" \ "nop; nop; nop; nop; nop; nop;\n\t" \ ".set reorder\n\t"); } #endif }