int mv_enable_fc_events(void *fc_event_handler, unsigned long period_ns)
{
unsigned long flags;
uint64_t clock_ticks = period_ns;
if (fc_event_handler == 0)
return -1;
local_irq_save(flags);
mv_fc_event_handler = fc_event_handler;
clock_ticks *= kw_clkevt.mult;
clock_ticks >>= kw_clkevt.shift;
/* Setup timer value */
MV_REG_WRITE(CNTMR_RELOAD_REG(FCTRLEVENT), (unsigned long)clock_ticks);
MV_REG_WRITE(CNTMR_VAL_REG(FCTRLEVENT), (unsigned long)clock_ticks);
/* Enable periodic timer and timer interrupt */
MV_REG_BIT_SET(BRIDGE_INT_MASK_REG, BRIDGE_INT_TIMER(FCTRLEVENT));
MV_REG_BIT_SET(CNTMR_CTRL_REG, TIMER_RELOAD_EN(FCTRLEVENT) | TIMER_EN(FCTRLEVENT));
fc_disabled = 0;
local_irq_restore(flags);
return 0;
}
/*******************************************************************************
* mvPexIfEnable
*
* DESCRIPTION:
* This function Enables PCI Express interface.
*
* INPUT:
* pexIf - PEX interface number.
* pexType - MV_PEX_ROOT_COMPLEX - root complex device
* MV_PEX_END_POINT - end point device
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvPexIfEnable(MV_U32 pexIf, MV_PEX_TYPE pexType)
{
MV_U32 regVal;
/* NOTE: this was asked by CV, bit is reserved in the spec, but causing problems, disabling for now. */
/* MV_REG_BIT_SET(PEX_CTRL_REG(pexIf), PXCR_AUTO_SPEED_CTRL_MASK); */
/* Set pex mode incase S@R not exist */
if (pexType == MV_PEX_END_POINT) {
MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf), PXCR_DEV_TYPE_CTRL_MASK);
/* Change pex mode in capability reg */
MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_CAPABILITY_REG), BIT22);
MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_CAPABILITY_REG), BIT20);
regVal = MV_REG_READ(PEX_CAPABILITIES_REG(pexIf));
regVal |= 0x00F00000;
regVal &= ~(BIT23 | BIT22 | BIT21);
MV_REG_WRITE(PEX_CAPABILITIES_REG(pexIf), regVal);
} else {
regVal = MV_REG_READ(PEX_CAPABILITIES_REG(pexIf));
regVal |= 0x00F00000;
regVal &= ~(BIT23 | BIT21 | BIT20);
MV_REG_WRITE(PEX_CAPABILITIES_REG(pexIf), regVal);
MV_REG_BIT_SET(PEX_CTRL_REG(pexIf), PXCR_DEV_TYPE_CTRL_MASK);
}
return;
}
/******************************************************************************
* mvEthCompMac0ToSgmiiConfig
*
* DESCRIPTION:
* Configure ethernet complex for MAC0 to SGMII output.
*
* INPUT:
* ethCompCfg - Ethernet complex configuration bitmap.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK on success,
* MV_ERROR otherwise.
*******************************************************************************/
MV_STATUS mvEthCompMac0ToSgmiiConfig(MV_U32 ethCompCfg)
{
if (!(ethCompCfg & (ESC_OPT_SGMII | ESC_OPT_SGMII_2_5)))
return MV_OK;
MV_REG_BIT_SET(MV_MAC_SERIAL_CTRL0_REG, BIT23 | BIT22 | BIT21 | BIT13 | BIT4 | BIT3 | BIT2);
MV_REG_WRITE(MV_MAC_SERIAL_CTRL1_REG,
(MV_REG_READ(MV_MAC_SERIAL_CTRL1_REG) & ~(BIT6 | BIT3)) | (BIT12 | BIT7 | BIT2));
MV_REG_BIT_SET(MV_MAC_SERIAL_CTRL0_REG, BIT1 | BIT10);
/* MV_REG_BIT_SET(MV_MAC_SERIAL_CTRL1_REG, BIT12 | BIT7 | BIT2); */
/* 3.8.3. LP_SERDES_PHY initialization:
* 3.8.3.1. Set LP_SERDES to reset: set Regunit Software Reset Control
* register to Reset (0x1).
*/
MV_REG_BIT_SET(SOFT_RESET_CTRL_REG, SRC_LPSRDSSWRSTN_MASK);
/* 3.8.3.2. De-assert LP_SERDES reset: set Regunit Software Reset
* Control register to 0x0.
*/
MV_REG_BIT_RESET(SOFT_RESET_CTRL_REG, SRC_LPSRDSSWRSTN_MASK);
/* 3.9. GbE-MAC-0 to LP_SERDES_PHY, using SSGMII
* 3.9.1. Ethernet-Complex configuration:
*/
/* Initialize Serdes. */
mvEthCompSerdesConfig(ethCompCfg);
return MV_OK;
}
/*******************************************************************************
* mvMbusArbCtrlSet - Set MBus Arbiter control register
*
* DESCRIPTION:
*
* INPUT:
* ctrl - pointer to MV_MBUS_ARB_CTRL register
*
* OUTPUT:
* N/A
*
* RETURN:
* MV_ERROR if paramers to function invalid.
*
*******************************************************************************/
MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl)
{
if (ctrl->highPrio == MV_FALSE)
{
MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP);
}
else
{
MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP);
}
if (ctrl->fixedRoundRobin == MV_FALSE)
{
MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED);
}
else
{
MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED);
}
if (ctrl->starvEn == MV_FALSE)
{
MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN);
}
else
{
MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN);
}
return MV_OK;
}
/*******************************************************************************
* mvAc97Reset
*
* DESCRIPTION:
* Cold reset the AC'97 unit.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK - On successfull init,
* MV_FAIL - If initialization fails.
*******************************************************************************/
MV_STATUS mvAc97Reset(MV_VOID)
{
//MV_U32 timeout = 1000;
/* Hold CLKBPB for 100us */
MV_REG_BIT_RESET(MV_AC97_GLOBAL_CTRL_REG,AC97_GLB_CTRL_COLD_RESET_MASK);
MV_REG_BIT_SET(MV_AC97_GLOBAL_CTRL_REG,AC97_GLB_CTRL_INT_CLK_EN_MASK);
mvOsUDelay(100);
MV_REG_BIT_RESET(MV_AC97_GLOBAL_CTRL_REG,AC97_GLB_CTRL_INT_CLK_EN_MASK);
MV_REG_BIT_SET(MV_AC97_GLOBAL_CTRL_REG,AC97_GLB_CTRL_COLD_RESET_MASK);
#if 0 /* Not sure if this is needed. */
MV_REG_BIT_SET(MV_AC97_GLOBAL_CTRL_REG,
AC97_GLB_CTRL_COLD_RESET_MASK | AC97_GLB_CTRL_WARM_RESET_MASK);
while(timeout > 0) {
val = MV_REG_READ(MV_AC97_GLOBAL_STATUS_REG);
if(val & (AC97_GLB_PCODEC_READY_MASK | AC97_GLB_SCODEC_READY_MASK))
break;
timeout--;
mvOsDelay(10);
}
if(timeout == 0)
return MV_TIMEOUT;
#endif /* 0 */
return MV_OK;
}
static void
kw_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
{
unsigned long flags;
local_irq_save(flags);
if (mode == CLOCK_EVT_MODE_PERIODIC) {
/*
* Setup latch cycles in timer and enable reload interrupt.
*/
MV_REG_WRITE(CNTMR_RELOAD_REG(CLOCKEVENT), ((mvBoardTclkGet() + HZ/2) / HZ));
MV_REG_WRITE(CNTMR_VAL_REG(CLOCKEVENT), ((mvBoardTclkGet() + HZ/2) / HZ));
MV_REG_BIT_SET(BRIDGE_INT_MASK_REG, BRIDGE_INT_TIMER(CLOCKEVENT));
MV_REG_BIT_SET(CNTMR_CTRL_REG, TIMER_RELOAD_EN(CLOCKEVENT) |
TIMER_EN(CLOCKEVENT));
} else {
/*
* Disable timer and interrupt
*/
MV_REG_BIT_RESET(BRIDGE_INT_MASK_REG, BRIDGE_INT_TIMER(CLOCKEVENT));
MV_REG_WRITE(BRIDGE_INT_CAUSE_REG, ~BRIDGE_INT_TIMER(CLOCKEVENT));
MV_REG_BIT_RESET(CNTMR_CTRL_REG, TIMER_RELOAD_EN(CLOCKEVENT) |
TIMER_EN(CLOCKEVENT));
}
local_irq_restore(flags);
}
static int
kw_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
{
unsigned long flags;
if (delta == 0)
return -ETIME;
local_irq_save(flags);
/*
* Clear and enable timer interrupt bit
*/
MV_REG_WRITE(BRIDGE_INT_CAUSE_REG, ~BRIDGE_INT_TIMER(CLOCKEVENT));
MV_REG_BIT_SET(BRIDGE_INT_MASK_REG, BRIDGE_INT_TIMER(CLOCKEVENT));
/*
* Setup new timer value
*/
MV_REG_WRITE(CNTMR_VAL_REG(CLOCKEVENT), delta);
/*
* Disable auto reload and kickoff the timer
*/
MV_REG_BIT_RESET(CNTMR_CTRL_REG, TIMER_RELOAD_EN(CLOCKEVENT));
MV_REG_BIT_SET(CNTMR_CTRL_REG, TIMER_EN(CLOCKEVENT));
local_irq_restore(flags);
return 0;
}
/******************************************************************************
* mvEthCompSwitchReset
*
* DESCRIPTION:
* Reset switch device after being configured by ethernet complex functions.
*
* INPUT:
* ethCompCfg - Ethernet complex configuration bitmap.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK on success,
* MV_ERROR otherwise.
*******************************************************************************/
MV_STATUS mvEthCompSwitchReset(MV_U32 ethCompCfg)
{
MV_U32 reg;
MV_U32 i;
if (!(ethCompCfg & (ESC_OPT_MAC0_2_SW_P4 | ESC_OPT_MAC1_2_SW_P5))) {
/* If no switch is connected, then we need to enable the 25MHz
** clock, and get the switch out of reset
*/
/* Set switch phy address so it does not collide with other
** addresses.
*/
reg = MV_REG_READ(MV_ETHCOMP_CTRL_REG(1));
reg &= ~ETHCC_SWTCH_ADDR_MASK;
reg |= (0xF << ETHCC_SWTCH_ADDR_OFFSET);
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(1), reg);
MV_REG_BIT_SET(MV_ETHCOMP_CTRL_REG(0), (1 << ETHCC_SW_FI_125_CLK_OFFSET));
MV_REG_BIT_SET(MV_ETHCOMP_CTRL_REG(1), ETHCC_SWTCH_RESET_MASK);
return MV_OK;
}
/* Disable polling on MAC ports. */
if (ethCompCfg & ESC_OPT_MAC0_2_SW_P4)
MV_REG_BIT_RESET(ETH_UNIT_CONTROL_REG(0), BIT1);
if (ethCompCfg & ESC_OPT_MAC1_2_SW_P5)
MV_REG_BIT_RESET(ETH_UNIT_CONTROL_REG(1), BIT1);
/*
* 3.1.4. Reset de-assertion:
* 3.1.4.1. De-assert Switch reset: set Regunit
* Ethernet_Complex_Control_1 register, field SwitchReset to 0x1.
*/
MV_REG_BIT_SET(MV_ETHCOMP_CTRL_REG(1), ETHCC_SWTCH_RESET_MASK);
#warning "Fix this to poll the Switch EEInt after reset"
mvOsDelay(100);
/* 10Mbps support */
for (i = 1; i < 4; i++) {
reg = MV_REG_READ(MV_ETHCOMP_CTRL_REG(3));
reg |= ETHCC_SW_PX_FRC_MII_SPD_MASK(i);
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(3), reg);
mvOsDelay(1);
reg |= ETHCC_SW_PX_FRC_SPD_MASK(i);
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(3), reg);
mvOsDelay(1);
reg &= ~ETHCC_SW_PX_FRC_MII_SPD_MASK(i);
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(3), reg);
mvOsDelay(1);
reg &= ~ETHCC_SW_PX_FRC_SPD_MASK(i);
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(3), reg);
mvOsDelay(1);
}
return MV_OK;
}
static void mv_unmask_irq(unsigned int irq)
{
if(irq < 32)
MV_REG_BIT_SET(MV_IRQ_MASK_REG, (1 << irq) );
else /* irq > 32 */
{
MV_REG_BIT_SET(MV_GPP_IRQ_MASK_REG, (1 << (irq - 32)) );
}
return;
}
/******************************************************************************
* mvEthernetComplexPostInit
*
* DESCRIPTION:
* Perform basic setup that is needed after configuring the eth-complex
* registers.
*
* INPUT:
* ethCompCfg - Ethernet complex configuration.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK on success,
* MV_ERROR otherwise.
*******************************************************************************/
static MV_STATUS mvEthernetComplexPostInit(MV_U32 ethCompCfg)
{
/* Re-enable polling mode if port is not connected to switch. */
if (!(ethCompCfg & ESC_OPT_MAC0_2_SW_P4))
MV_REG_BIT_SET(ETH_UNIT_CONTROL_REG(0), BIT1);
if (!(ethCompCfg & ESC_OPT_MAC1_2_SW_P5))
MV_REG_BIT_SET(ETH_UNIT_CONTROL_REG(1), BIT1);
return MV_OK;
}
void
BuffaloGpio_CpuReset(void)
{
#ifdef CONFIG_ARCH_FEROCEON_MV78XX0
return;
#else
MV_REG_BIT_SET(CPU_RSTOUTN_MASK_REG, BIT(2));
MV_REG_BIT_SET(CPU_SYS_SOFT_RST_REG, BIT(0));
#endif
}
static void mv_unmask_irq(unsigned int irq)
{
if (irq < 32)
MV_REG_BIT_SET(CPU_INT_MASK_LOW_REG(coreId), (1 << irq));
else if (irq < 64) /* irq > 32 && irq < 64 */
MV_REG_BIT_SET(CPU_INT_MASK_HIGH_REG(coreId), (1 << (irq - 32)));
else
MV_REG_BIT_SET(GPP_INT_LVL_REG(0), (1 << (irq - 64)) );
}
/*******************************************************************************
* mvAc97CodecRegRead
*
* DESCRIPTION:
* Read an attached AC'97 codec register.
*
* INPUT:
* codecId - The Codec ID to read the register for.
* regAddr - The Codec register address to read.
*
* OUTPUT:
* data - The Codec register value as returned by the Codec.
*
* RETURN:
* MV_OK - On successfull init,
* MV_TIMEOUT - On read timeout.
* MV_FAIL - Otherwise.
*******************************************************************************/
MV_STATUS mvAc97CodecRegRead(MV_AC97_CODEC_ID codecId, MV_U16 regAddr,MV_U16 *data)
{
MV_U32 val;
MV_U32 status = MV_OK;
MV_U32 accAddr;
MV_U32 retries = AC97_READ_WRITE_MAX_RETRY;
if(data == NULL)
return MV_BAD_PARAM;
/* Get the access register. */
mvAc97CodecAccessRegGet(codecId,regAddr,&accAddr);
if(regAddr == AC97_CODEC_GPIO_STATUS_REG) {
/* Read from the AC'97 controller cache.*/
goto done;
}
/* Clear the command / status done bits. */
MV_REG_BIT_SET(MV_AC97_GLOBAL_STATUS_REG,
(AC97_GLB_STATUS_DONE_MASK | AC97_GLB_CMND_DONE_MASK));
/* Issue a dummy read. */
val = MV_REG_READ(accAddr);
/* Wait till the status done bit is valid. */
while(retries > 0)
{
retries--;
val = MV_REG_READ(MV_AC97_GLOBAL_STATUS_REG);
if(val & AC97_GLB_STATUS_DONE_MASK)
break;
}
/* Check for a timeout. */
if(retries == 0)
{
status = MV_TIMEOUT;
goto done;
}
/* Clear the command / status done bits. */
MV_REG_BIT_SET(MV_AC97_GLOBAL_STATUS_REG,
(AC97_GLB_STATUS_DONE_MASK | AC97_GLB_CMND_DONE_MASK));
done:
if(status == MV_OK)
{
/* Now read the "real" data. */
val = MV_REG_READ(accAddr);
*data = (MV_U16)(val & 0xFFFF);
}
return status;
}
/******************************************************************************
* mvEthernetComplexShutdownIf
*
* DESCRIPTION:
* Shutdown ethernet complex interfaces.
*
* INPUT:
* integSwitch - MV_TRUE to shutdown the integrated switch.
* gePhy - MV_TRUE to shutdown the GE-PHY
* fePhy - MV_TRUE to shutdown the 3xFE PHY.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK on success,
* MV_ERROR otherwise.
*******************************************************************************/
MV_STATUS mvEthernetComplexShutdownIf(MV_BOOL integSwitch, MV_BOOL gePhy, MV_BOOL fePhy)
{
if (gePhy == MV_TRUE) {
MV_REG_BIT_RESET(MV_ETHCOMP_GE_PHY_CTRL_REG, PHYCTRL_PHY_PWR_DOWN_MASK);
MV_REG_BIT_SET(MV_ETHCOMP_GE_PHY_CTRL_REG, PHYCTRL_EXT_PWR_DOWN_SRC_MASK);
MV_REG_BIT_SET(MV_ETHCOMP_GE_PHY_CTRL_REG, PHYCTRL_PHY_PWR_DOWN_MASK);
}
if (fePhy == MV_TRUE) {
MV_REG_BIT_RESET(MV_ETHCOMP_FE_PHY_CTRL_REG, ETHCC_FE_PHY_RESET_MASK);
MV_REG_BIT_RESET(MV_ETHCOMP_FE_PHY_CTRL_REG, ETHCC_FE_PHY_EXT_PWR_DOWM_MASK);
}
return MV_OK;
}
/*******************************************************************************
* mvDmaMemInit - Initialize a memory buffer with a given 64bit value pattern
*
* DESCRIPTION:
* This function initiates IDMA channel, according to function parameters,
* in order to perform DMA transaction for the purpose of initializing a
* memory buffer with a user supplied pattern.
* This routine supports both chain and none chained DMA modes.
* To use the function in chain mode just set phyNextDesc parameter with
* chain second descriptor address (the first one is given in other
* function paarameters). Otherwise (none chain mode) set it to NULL.
* To gain maximum performance the user is asked to keep the following
* restrictions:
* 1) Selected engine is available (not busy).
* 1) This module does not take into consideration CPU MMU issues.
* In order for the IDMA engine to access the appropreate source
* and destination, address parameters must be given in system
* physical mode.
* 2) This API does not take care of cache coherency issues. The source,
* destination and in case of chain the descriptor list are assumed
* to be cache coherent.
* 3) No chain mode support.
* 4) Parameters validity. For example, does size parameter exceeds
* maximum byte count of descriptor mode (16M or 64K).
*
* INPUT:
* chan - DMA channel number. See MV_DMA_CHANNEL enumerator.
* ptrnPtr - Physical source address of the 64bit pattern
* startPtr - Physical destinaation address to start with
* size - The total number of bytes to transfer.
*
* OUTPUT:
* None.
*
* RETURS:
* MV_OK.
*
*******************************************************************************/
MV_STATUS mvDmaMemInit(MV_U32 chan, MV_U32 ptrnPtr, MV_U32 startPtr, MV_U32 size)
{
/* Set byte count register */
MV_REG_WRITE(IDMA_BYTE_COUNT_REG(chan), size);
/* Set source address register */
MV_REG_WRITE(IDMA_SRC_ADDR_REG(chan), ptrnPtr);
/* Set destination address register */
MV_REG_WRITE(IDMA_DST_ADDR_REG(chan), startPtr);
/* Lock the Source address in dma operation */
MV_REG_BIT_SET(IDMA_CTRL_LOW_REG(chan), ICCLR_SRC_HOLD);
/* Start DMA */
MV_REG_BIT_SET(IDMA_CTRL_LOW_REG(chan), ICCLR_CHAN_ENABLE);
return MV_OK;
}
/*******************************************************************************
* mvAc97CodecRegWrite
*
* DESCRIPTION:
* Write to an attached AC'97 codec register.
*
* INPUT:
* codecId - The Codec ID to write the register for.
* regAddr - The Codec register address to write to.
* data - Data to be written.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK - On successfull init,
* MV_FAIL - Otherwise.
*******************************************************************************/
MV_STATUS mvAc97CodecRegWrite(MV_AC97_CODEC_ID codecId, MV_U16 regAddr,MV_U16 data)
{
MV_U32 val;
MV_U32 status = MV_OK;
MV_U32 accAddr;
MV_U32 retries = AC97_READ_WRITE_MAX_RETRY;
/* Get the access register. */
mvAc97CodecAccessRegGet(codecId,regAddr,&accAddr);
/* Clear the command / status done bits. */
MV_REG_BIT_SET(MV_AC97_GLOBAL_STATUS_REG,
(AC97_GLB_STATUS_DONE_MASK | AC97_GLB_CMND_DONE_MASK));
/* Issue the write operation. */
val = (MV_U32)data;
MV_REG_WRITE(accAddr,val);
/* Wait till the status done bit is valid. */
while(retries > 0)
{
retries--;
val = MV_REG_READ(MV_AC97_GLOBAL_STATUS_REG);
if(val & AC97_GLB_CMND_DONE_MASK)
break;
}
/* Check for a timeout. */
if(retries == 0)
status = MV_TIMEOUT;
return status;
}
/*******************************************************************************
* mvXorTargetWinEnable - Enable/disable a Xor address decode window
*
* DESCRIPTION:
* This function enable/disable a XOR address decode window.
* if parameter 'enable' == MV_TRUE the routine will enable the
* window, thus enabling XOR accesses (before enabling the window it is
* tested for overlapping). Otherwise, the window will be disabled.
*
* INPUT:
* winNum - Decode window number.
* enable - Enable/disable parameter.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
*
*******************************************************************************/
MV_STATUS mvXorTargetWinEnable(MV_U32 unit, MV_U32 winNum, MV_BOOL enable)
{
MV_UNIT_WIN_INFO addrDecWin;
MV_U32 chan;
/* Parameter checking */
if (winNum >= XOR_MAX_ADDR_DEC_WIN) {
DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __func__, winNum));
return MV_ERROR;
}
if (enable == MV_TRUE) {
/* Get current window */
if (MV_OK != mvXorTargetWinRead(unit, winNum, &addrDecWin)) {
DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __func__));
return MV_ERROR;
}
/* Check for overlapping */
if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &(addrDecWin.addrWin))) {
/* Overlap detected */
DB(mvOsPrintf("%s: ERR. Overlap detected\n", __func__));
return MV_ERROR;
}
/* No Overlap. Enable address decode target window */
for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++)
MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit, chan), XEXWCR_WIN_EN_MASK(winNum));
} else {
/* Disable address decode target window */
for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++)
MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit, chan), XEXWCR_WIN_EN_MASK(winNum));
}
return MV_OK;
}
/*******************************************************************************
* mvTsuWinEnable - Enable/disable a TS address decode window
*
* DESCRIPTION:
* This function enable/disable a TS address decode window.
*
* INPUT:
* winNum - Decode window number.
* enable - Enable/disable parameter.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
*
*******************************************************************************/
MV_STATUS mvTsuWinEnable(MV_U32 winNum, MV_BOOL enable)
{
MV_UNIT_WIN_INFO addrDecWin;
/* Parameter checking */
if (winNum >= TSU_MAX_DECODE_WIN) {
DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum));
return MV_ERROR;
}
if (enable == MV_TRUE) {
/* Get current window */
if (MV_OK != mvTsuWinRead(0, winNum, &addrDecWin)) {
DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__));
return MV_ERROR;
}
/* Check for overlapping */
if (MV_TRUE == tsuWinOverlapDetect(winNum, &(addrDecWin.addrWin))) {
/* Overlap detected */
DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__));
return MV_ERROR;
}
/* No Overlap. Enable address decode target window */
MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum), TSU_WIN_CTRL_EN_MASK);
} else {
/* Disable address decode target window */
MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum), TSU_WIN_CTRL_EN_MASK);
}
return MV_OK;
}
MV_STATUS mvXorOverrideSet(MV_U32 chan, MV_XOR_OVERRIDE_TARGET target, MV_U32 winNum, MV_BOOL enable)
{
MV_U32 temp;
/* Parameter checking */
if (chan >= MV_XOR_MAX_CHAN) {
DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __func__, chan));
return MV_BAD_PARAM;
}
if (winNum >= XOR_MAX_OVERRIDE_WIN) {
DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __func__, winNum));
return MV_BAD_PARAM;
}
/* set the enable bit */
if (enable)
MV_REG_BIT_SET(XOR_OVERRIDE_CTRL_REG(chan), XEXAOCR_OVR_EN_MASK(target));
else
MV_REG_BIT_RESET(XOR_OVERRIDE_CTRL_REG(chan), XEXAOCR_OVR_EN_MASK(target));
/* read the override control register */
temp = MV_REG_READ(XOR_OVERRIDE_CTRL_REG(chan));
temp &= ~XEXAOCR_OVR_PTR_MASK(target);
temp |= (winNum << XEXAOCR_OVR_PTR_OFFS(target));
MV_REG_WRITE(XOR_OVERRIDE_CTRL_REG(chan), temp);
return MV_OK;
}
MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum,
MV_BOOL enable)
{
PEX_WIN_REG_INFO winRegInfo;
/* Parameter checking */
if (pexIf >= mvCtrlPexMaxIfGet())
{
mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n",
pexIf);
return MV_BAD_PARAM;
}
if (MV_PEX_WIN_DEFAULT == winNum)
{
mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n",
winNum);
return MV_BAD_PARAM;
}
pexWinRegInfoGet(pexIf, winNum, &winRegInfo);
if (enable == MV_TRUE)
{
MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN);
}
else
{
MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN);
}
return MV_OK;
}
/*******************************************************************************
* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window
*
* DESCRIPTION:
* This function enable/disable a CPU address decode window.
* if parameter 'enable' == MV_TRUE the routine will enable the
* window, thus enabling CPU accesses (before enabling the window it is
* tested for overlapping). Otherwise, the window will be disabled.
*
* INPUT:
* winNum - Peripheral winNum enumerator.
* enable - Enable/disable parameter.
*
* OUTPUT:
* N/A
*
* RETURN:
* MV_ERROR if protection window number was wrong, or the window
* overlapps other winNum window.
*
*******************************************************************************/
MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable)
{
/* Parameter checking */
if (winNum >= MAX_AHB_TO_MBUS_WINS)
{
mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum);
return MV_NOT_SUPPORTED;
}
/* Internal registers bar can't be disable or enabled */
if (winNum == MV_AHB_TO_MBUS_INTREG_WIN)
{
return (enable ? MV_OK : MV_ERROR);
}
if (enable == MV_TRUE)
{
/* enable the window */
MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE);
}
else
{ /* Disable address decode winNum window */
MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE);
}
return MV_OK;
}
/*******************************************************************************
* mvCpuIfEnablePex - Enable PCI Express.
*
* DESCRIPTION:
* This function enables PCI Express access to the device address
* space.
*
* INPUT:
* pexIf - The PCI-E interface to enable.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvCpuIfEnablePex(MV_U32 pexIf)
{
MV_U32 reg;
if (mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf) == MV_TRUE) {
if (pexIf == 0) {
reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PEX_LINK_CAPABILITY_REG));
reg &= ~PXLC_MAX_LNK_SPEED_MASK;
reg |= (0x1 << PXLC_MAX_LNK_SPEED_OFFS);
MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(0, PEX_LINK_CAPABILITY_REG), reg);
}
MV_REG_BIT_SET(0x18480 , BIT6);
/* CPU config register Pex enable */
MV_REG_BIT_SET(CPU_CTRL_STAT_REG, CCSR_PCI_ACCESS_MASK(pexIf));
}
}
static void mv_enter_standby(void)
{
u32 reg;
static MV_U32 pwrUpDelay = 0;
pr_debug("kw2_standby: Entering STANDBY mode.\n");
if (pwrUpDelay == 0)
pwrUpDelay = mvBoardPwrUpDelayGet();
count_standby++;
save_kw2_cpu_win_state();
/* Prepare resume PC */
MV_REG_WRITE(PMU_CPU_BOOT_ADDR, virt_to_phys(kw2_cpu_resume));
MV_REG_WRITE(PMU_PWR_UP_DELAY, pwrUpDelay);
MV_REG_WRITE(PMU_CPU_STATUS_MASK, 0x00310000);
/* L2 Power down enable */
if (mvCpuL2Exists())
MV_REG_BIT_SET(PMU_L2C_CTRL_AND_CONF, BIT20);
/* CPU Power down enable */
MV_REG_BIT_SET(PMU_CPU_CTRL_AND_CONF, BIT20);
/* CPU Power down request */
MV_REG_BIT_SET(PMU_CPU_CTRL_AND_CONF, BIT16);
/* Suspend the CPU only */
if (kw2_cpu_suspend() == 0)
cpu_init();
restore_kw2_cpu_win_state();
reg = MV_REG_READ(PMU_CPU_STATUS_MASK);
reg &= ~0x3310000;
MV_REG_WRITE(PMU_CPU_STATUS_MASK, reg);
pr_debug("kw2_standby: Exiting STANDBY mode.\n");
}
/*******************************************************************************
* mvXorTargetWinWrite - Set XOR target address window
*
* DESCRIPTION:
* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
* address window. After setting this target window, the XOR will be
* able to access the target within the address window.
*
* INPUT:
* winNum - One of the possible XOR memory decode windows.
* target - Peripheral target enumerator.
* base - Window base address.
* size - Window size.
* enable - Window enable/disable.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
*
*******************************************************************************/
MV_STATUS mvXorTargetWinWrite(MV_U32 unit, MV_U32 winNum,
MV_UNIT_WIN_INFO *pAddrDecWin)
{
MV_U32 sizeReg, baseReg;
MV_U32 chan;
/* Parameter checking */
if (winNum >= XOR_MAX_ADDR_DEC_WIN) {
DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __func__, winNum));
return MV_BAD_PARAM;
}
if (pAddrDecWin == NULL) {
DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __func__));
return MV_BAD_PTR;
}
/* Check if the requested window overlaps with current windows */
if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) {
DB(mvOsPrintf("%s: ERR. Window %d overlap\n", __func__, winNum));
return MV_ERROR;
}
if (!MV_IS_POWER_OF_2(pAddrDecWin->addrWin.size)) {
mvOsPrintf("%s: ERR. Illegal window size.\n", __func__);
return MV_BAD_PARAM;
}
baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit, winNum));
sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit, winNum));
baseReg = pAddrDecWin->addrWin.baseLow & XEBARX_BASE_MASK;
sizeReg = (pAddrDecWin->addrWin.size / XOR_WIN_SIZE_ALIGN) - 1;
sizeReg = (sizeReg << XESMRX_SIZE_MASK_OFFS) & XESMRX_SIZE_MASK_MASK;
/* set attributes */
baseReg &= ~XEBARX_ATTR_MASK;
baseReg |= pAddrDecWin->attrib << XEBARX_ATTR_OFFS;
/* set target ID */
baseReg &= ~XEBARX_TARGET_MASK;
baseReg |= pAddrDecWin->targetId << XEBARX_TARGET_OFFS;
/* Write to address decode Base Address Register */
MV_REG_WRITE(XOR_BASE_ADDR_REG(unit, winNum), baseReg);
/* Write to Size Register */
MV_REG_WRITE(XOR_SIZE_MASK_REG(unit, winNum), sizeReg);
for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) {
if (pAddrDecWin->enable)
MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit, chan), XEXWCR_WIN_EN_MASK(winNum));
else
MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit, chan), XEXWCR_WIN_EN_MASK(winNum));
}
return MV_OK;
}
/*******************************************************************************
* mvPexTargetWinRemap - Set PEX to target address window remap.
*
* DESCRIPTION:
* The PEX interface supports remap of the BAR original address window.
* For each BAR it is possible to define a remap address. For example
* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified
* according to remap register but will also be targeted to the
* SDRAM CS[0].
*
* INPUT:
* pexIf - PEX interface number.
* bar - Peripheral target enumerator accessed by slave.
* pAddrWin - Address window to be checked.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
*
*******************************************************************************/
MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum,
MV_PEX_REMAP_WIN *pAddrWin)
{
PEX_WIN_REG_INFO winRegInfo;
/* Parameter checking */
if (pexIf >= mvCtrlPexMaxIfGet())
{
mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n",
pexIf);
return MV_BAD_PARAM;
}
if (MV_PEX_WIN_DEFAULT == winNum)
{
mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n",
winNum);
return MV_BAD_PARAM;
}
if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT))
{
mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\
"\nAddress 0x%08x is unaligned to size 0x%x.\n",
pexIf,
winNum,
pAddrWin->addrWin.baseLow,
pAddrWin->addrWin.size);
return MV_ERROR;
}
pexWinRegInfoGet(pexIf, winNum, &winRegInfo);
/* Set remap low register value */
MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow);
/* Skip base high settings if the BAR has only base low (32-bit) */
if (0 != winRegInfo.remapHighRegOffs)
{
MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh);
}
if (pAddrWin->enable == MV_TRUE)
{
MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN);
}
else
{
MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN);
}
return MV_OK;
}
/*******************************************************************************
* mvXorCommandSet - Set command of XOR channel
*
* DESCRIPTION:
* XOR channel can be started, idle, paused and restarted.
* Paused can be set only if channel is active.
* Start can be set only if channel is idle or paused.
* Restart can be set only if channel is paused.
* Stop can be set only if channel is active.
*
* INPUT:
* chan - The channel number
* command - The command type (start, stop, restart, pause)
*
* OUTPUT:
* None.
*
* RETURN:
* GT_OK on success , GT_BAD_PARAM on erroneous parameter, MV_ERROR on
* undefind XOR engine mode
*
*******************************************************************************/
GT_STATUS mvXorCommandSet(GT_U32 chan, MV_COMMAND command)
{
MV_STATE state;
/* Parameter checking */
if (chan >= MV_XOR_MAX_CHAN) {
DB(mvPrintf("%s: ERR. Invalid chan num %d\n", __func__, chan));
return GT_BAD_PARAM;
}
/* get the current state */
state = mvXorStateGet(chan);
/* command is start and current state is idle */
if ((command == MV_START) && (state == MV_IDLE)) {
MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), XEXACTR_XESTART_MASK);
return GT_OK;
}
/* command is stop and current state is active */
else if ((command == MV_STOP) && (state == MV_ACTIVE)) {
MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), XEXACTR_XESTOP_MASK);
return GT_OK;
}
/* command is paused and current state is active */
else if (((MV_STATE)command == MV_PAUSED) && (state == MV_ACTIVE)) {
MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), XEXACTR_XEPAUSE_MASK);
return GT_OK;
}
/* command is restart and current state is paused */
else if ((command == MV_RESTART) && (state == MV_PAUSED)) {
MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), XEXACTR_XERESTART_MASK);
return GT_OK;
}
/* command is stop and current state is active */
else if ((command == MV_STOP) && (state == MV_IDLE))
return GT_OK;
/* illegal command */
DB(mvPrintf("%s: ERR. Illegal command\n", __func__));
return GT_BAD_PARAM;
}
MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType)
{
/* Set pex mode incase S@R not exist */
if( pexType == MV_PEX_END_POINT)
{
MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK);
/* Change pex mode in capability reg */
MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22);
MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20);
}
else
{
MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK);
}
/* CPU config register Pex enable */
MV_REG_BIT_SET(CPU_CTRL_STAT_REG,(CCSR_PCI_ACCESS_MASK(pexIf)));
}
/*******************************************************************************
* mvAudioHalInit - Initialize the Audio subsystem
*
* DESCRIPTION:
*
* INPUT:
* None
* OUTPUT:
* None
* RETURN:
* None
*
*******************************************************************************/
MV_VOID mvAudioHalInit(void)
{
int timeout;
MV_REG_BIT_RESET(AUDIO_REG_BASE + 0x1200,0x333FF8);
MV_REG_BIT_SET(AUDIO_REG_BASE + 0x1200,0x111D18);
/*MV_REG_BIT_RESET(0x10074,0xC018000);
MV_REG_BIT_SET(0x10074,0x4008000);*/
timeout = 10000000;
while(timeout--);
MV_REG_BIT_RESET(AUDIO_REG_BASE + 0x1200,0x333FF8);
MV_REG_BIT_SET(AUDIO_REG_BASE + 0x1200,0x111D18);
/*MV_REG_BIT_RESET(0x10074,0xC018000);
MV_REG_BIT_SET(0x10074,0x4008000);*/
}
/*******************************************************************************
* mvAudioHalInit - Initialize the Audio subsystem
*
* DESCRIPTION:
*
* INPUT:
* None
* OUTPUT:
* None
* RETURN:
* None
*
*******************************************************************************/
MV_VOID mvAudioHalInit(MV_U8 unit)
{
int timeout;
MV_REG_BIT_RESET(MV_AUDIO_PLL_CTRL1_REG(unit),0x333FF8);
MV_REG_BIT_SET(MV_AUDIO_PLL_CTRL1_REG(unit),0x111D18);
/*MV_REG_BIT_RESET(0x10074,0xC018000);
MV_REG_BIT_SET(0x10074,0x4008000);*/
timeout = 10000000;
while(timeout--);
MV_REG_BIT_RESET(MV_AUDIO_PLL_CTRL1_REG(unit),0x333FF8);
MV_REG_BIT_SET(MV_AUDIO_PLL_CTRL1_REG(unit),0x111D18);
/*MV_REG_BIT_RESET(0x10074,0xC018000);
MV_REG_BIT_SET(0x10074,0x4008000);*/
}
/******************************************************************************
* mvEthCompSwP1ToSgmiiConfig
*
* DESCRIPTION:
* Configure ethernet complex for Switch port1 to SGMII output.
*
* INPUT:
* ethCompCfg - Ethernet complex configuration bitmap.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK on success,
* MV_ERROR otherwise.
*******************************************************************************/
MV_STATUS mvEthCompSwP1ToSgmiiConfig(MV_U32 ethCompCfg)
{
MV_U32 reg;
if (!(ethCompCfg & (ESC_OPT_SGMII | ESC_OPT_SGMII_2_5)))
return MV_OK;
/* 3.10. Switch P1 to LP_SERDES_PHY, using TBI
* 3.10.2. Ethernet-Complex configuration:
* 3.10.2.1. Configure Switch 125Mhz clock source: set Regunit
* Ethernet_Complex_Control_0 register, field SwFi125ClkSrc to LpSERDES (0x2).
*/
reg = MV_REG_READ(MV_ETHCOMP_CTRL_REG(0));
reg &= ~ETHCC_SW_FI_125_CLK_MASK;
/* 3.10.2.2. Connect Switch ports 1 to PCS-0: set Regunit
* Ethernet_Complex_Control_0 register, field SwitchPort123Source to PCS (0x0)
*/
reg &= ~ETHCC_SW_PORT_123_SRC_MASK;
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(0), reg);
/* Initialize Serdes. */
mvEthCompSerdesConfig(ethCompCfg);
/* 3.10.4. Reset de-assertion:
* 3.10.4.1. De-assert all PCSs reset: set registers PCS_0_Control,
* PCS_1_Control PCS_2_Control and PCS_3_Control, fields PCS<i>_Port_Reset to 0x0.
*/
MV_REG_BIT_RESET(MV_ETHCOMP_PCS_CTRL_REG(0), PCSCTRL_PORT_RESET_MASK);
/* 3.10.5. PCS-0 configurations:
* OPEN: This section was never tried on our test-plan. We should ramp
* up this test!!! The following sections are written based on section. (QSGMII)
* 3.10.5.1. Enable PCS ports: set Regunit PCS0Control register, fields
* Pcs0PortActive and Pcs0En to active (0x1)
*/
MV_REG_BIT_SET(MV_ETHCOMP_PCS_CTRL_REG(0), PCSCTRL_PORT_ACTIVE_MASK);
MV_REG_BIT_SET(MV_ETHCOMP_PCS_CTRL_REG(0), PCSCTRL_PORT_EN_MASK);
return MV_OK;
}
