/**
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
value, followed a bitwise inclusive OR with another 8-bit value.
Reads the 8-bit PCI configuration register specified by Address, performs a
bitwise AND between the read result and the value specified by AndData,
performs a bitwise inclusive OR between the result of the AND operation and
the value specified by OrData, and writes the result to the 8-bit PCI
configuration register specified by Address. The value written to the PCI
configuration register is returned. This function must guarantee that all PCI
read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the result of the AND operation.
@return The value written back to the PCI configuration register.
**/
UINT8
EFIAPI
PciExpressAndThenOr8 (
IN UINTN Address,
IN UINT8 AndData,
IN UINT8 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
return MmioAndThenOr8 (
(UINTN) GetPciExpressBaseAddress () + Address,
AndData,
OrData
);
}
/**
Perform flash write operation with progress indicator. The start and end
completion percentage values are passed into this function. If the requested
flash write operation is broken up, then completion percentage between the
start and end values may be passed to the provided Progress function. The
caller of this function is required to call the Progress function for the
start and end completion percentage values. This allows the Progress,
StartPercentage, and EndPercentage parameters to be ignored if the requested
flash write operation can not be broken up
@param[in] FirmwareType The type of firmware.
@param[in] FlashAddress The address of flash device to be accessed.
@param[in] FlashAddressType The type of flash device address.
@param[in] Buffer The pointer to the data buffer.
@param[in] Length The length of data buffer in bytes.
@param[in] Progress A function used report the progress of the
firmware update. This is an optional parameter
that may be NULL.
@param[in] StartPercentage The start completion percentage value that may
be used to report progress during the flash
write operation.
@param[in] EndPercentage The end completion percentage value that may
be used to report progress during the flash
write operation.
@retval EFI_SUCCESS The operation returns successfully.
@retval EFI_WRITE_PROTECTED The flash device is read only.
@retval EFI_UNSUPPORTED The flash device access is unsupported.
@retval EFI_INVALID_PARAMETER The input parameter is not valid.
**/
EFI_STATUS
EFIAPI
PerformFlashWriteWithProgress (
IN PLATFORM_FIRMWARE_TYPE FirmwareType,
IN EFI_PHYSICAL_ADDRESS FlashAddress,
IN FLASH_ADDRESS_TYPE FlashAddressType,
IN VOID *Buffer,
IN UINTN Length,
IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS Progress, OPTIONAL
IN UINTN StartPercentage,
IN UINTN EndPercentage
)
{
EFI_STATUS Status = EFI_SUCCESS;
UINTN Index;
EFI_PHYSICAL_ADDRESS Address;
UINTN CountOfBlocks;
EFI_TPL OldTpl;
BOOLEAN FlashError;
UINT8 *Buf;
UINTN LpcBaseAddress;
UINT8 Data8Or;
UINT8 Data8And;
UINT8 BiosCntl;
Index = 0;
Address = 0;
CountOfBlocks = 0;
FlashError = FALSE;
Buf = Buffer;
DEBUG((DEBUG_INFO | DEBUG_ERROR, "PerformFlashWrite - 0x%x(%x) - 0x%x\n", (UINTN)FlashAddress, (UINTN)FlashAddressType, Length));
if (FlashAddressType == FlashAddressTypeRelativeAddress) {
FlashAddress = FlashAddress + mInternalFdAddress;
}
CountOfBlocks = (UINTN) (Length / BLOCK_SIZE);
Address = FlashAddress;
LpcBaseAddress = MmPciAddress (0,
DEFAULT_PCI_BUS_NUMBER_PCH,
PCI_DEVICE_NUMBER_PCH_LPC,
PCI_FUNCTION_NUMBER_PCH_LPC,
0
);
BiosCntl = MmioRead8 (LpcBaseAddress + R_PCH_LPC_BIOS_CNTL);
if ((BiosCntl & B_PCH_LPC_BIOS_CNTL_SMM_BWP) == B_PCH_LPC_BIOS_CNTL_SMM_BWP) {
///
/// Clear SMM_BWP bit (D31:F0:RegDCh[5])
///
Data8And = (UINT8) ~B_PCH_LPC_BIOS_CNTL_SMM_BWP;
Data8Or = 0x00;
MmioAndThenOr8 (
LpcBaseAddress + R_PCH_LPC_BIOS_CNTL,
Data8And,
Data8Or
);
DEBUG((DEBUG_INFO, "PerformFlashWrite Clear SMM_BWP bit\n"));
}
//
// Raise TPL to TPL_NOTIFY to block any event handler,
// while still allowing RaiseTPL(TPL_NOTIFY) within
// output driver during Print()
//
OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
for (Index = 0; Index < CountOfBlocks; Index++) {
if (Progress != NULL) {
Progress (StartPercentage + ((Index * (EndPercentage - StartPercentage)) / CountOfBlocks));
}
//
// Handle block based on address and contents.
//
if (!EFI_ERROR (InternalCompareBlock (Address, Buf))) {
DEBUG((DEBUG_INFO, "Skipping block at 0x%lx (already programmed)\n", Address));
} else {
//
// Make updating process uninterruptable,
// so that the flash memory area is not accessed by other entities
// which may interfere with the updating process
//
Status = InternalEraseBlock (Address);
if (EFI_ERROR(Status)) {
gBS->RestoreTPL (OldTpl);
FlashError = TRUE;
goto Done;
}
Status = InternalWriteBlock (
Address,
Buf,
(UINT32)(Length > BLOCK_SIZE ? BLOCK_SIZE : Length)
);
if (EFI_ERROR(Status)) {
gBS->RestoreTPL (OldTpl);
FlashError = TRUE;
goto Done;
}
}
//
// Move to next block to update.
//
Address += BLOCK_SIZE;
Buf += BLOCK_SIZE;
if (Length > BLOCK_SIZE) {
Length -= BLOCK_SIZE;
} else {
Length = 0;
}
}
gBS->RestoreTPL (OldTpl);
Done:
if ((BiosCntl & B_PCH_LPC_BIOS_CNTL_SMM_BWP) == B_PCH_LPC_BIOS_CNTL_SMM_BWP) {
//
// Restore original control setting
//
MmioWrite8 (LpcBaseAddress + R_PCH_LPC_BIOS_CNTL, BiosCntl);
}
if (Progress != NULL) {
Progress (EndPercentage);
}
return EFI_SUCCESS;
}
