static int macscsi_pwrite (struct Scsi_Host *instance,
unsigned char *src, int len)
{
unsigned char *s;
volatile unsigned char *d;
NCR5380_local_declare();
NCR5380_setup(instance);
s = src;
d = mac_scsi_drq;
/* These conditions are derived from MacOS */
while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)
&& (!(NCR5380_read(STATUS_REG) & SR_REQ)
|| (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)))
;
if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)) {
printk(KERN_ERR "Error in macscsi_pwrite\n");
return -1;
}
CP_MEM_TO_IO(s, d, len);
if (len != 0) {
printk(KERN_NOTICE "Bus error in macscsi_pwrite\n");
return -1;
}
return 0;
}
static void mac_scsi_reset_boot(struct Scsi_Host *instance)
{
unsigned long end;
NCR5380_local_declare();
NCR5380_setup(instance);
/*
* Do a SCSI reset to clean up the bus during initialization. No messing
* with the queues, interrupts, or locks necessary here.
*/
printk(KERN_INFO "Macintosh SCSI: resetting the SCSI bus..." );
/* get in phase */
NCR5380_write( TARGET_COMMAND_REG,
PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
/* assert RST */
NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST );
/* The min. reset hold time is 25us, so 40us should be enough */
udelay( 50 );
/* reset RST and interrupt */
NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE );
NCR5380_read( RESET_PARITY_INTERRUPT_REG );
for( end = jiffies + AFTER_RESET_DELAY; time_before(jiffies, end); )
barrier();
printk(KERN_INFO " done\n" );
}
static int macscsi_pread (struct Scsi_Host *instance,
unsigned char *dst, int len)
{
unsigned char *d;
volatile unsigned char *s;
NCR5380_local_declare();
NCR5380_setup(instance);
s = mac_scsi_drq+0x60;
d = dst;
while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)
&& !(NCR5380_read(STATUS_REG) & SR_REQ))
;
if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)
&& (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)) {
printk(KERN_ERR "Error in macscsi_pread\n");
return -1;
}
CP_IO_TO_MEM(s, d, len);
if (len != 0) {
printk(KERN_NOTICE "Bus error in macscsi_pread\n");
return -1;
}
return 0;
}
static void mac_scsi_reset_boot(struct Scsi_Host *instance)
{
unsigned long end;
NCR5380_local_declare();
NCR5380_setup(instance);
printk(KERN_INFO "Macintosh SCSI: resetting the SCSI bus..." );
disable_irq(IRQ_MAC_SCSI);
NCR5380_write( TARGET_COMMAND_REG,
PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST );
udelay( 50 );
NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE );
NCR5380_read( RESET_PARITY_INTERRUPT_REG );
for( end = jiffies + AFTER_RESET_DELAY; time_before(jiffies, end); )
barrier();
enable_irq(IRQ_MAC_SCSI);
printk(KERN_INFO " done\n" );
}
static int macscsi_pwrite(struct Scsi_Host *instance,
unsigned char *src, int len)
{
struct NCR5380_hostdata *hostdata = shost_priv(instance);
unsigned char *s;
unsigned char *d;
NCR5380_local_declare();
NCR5380_setup(instance);
s = src;
d = hostdata->pdma_base + (OUTPUT_DATA_REG << 4);
/* These conditions are derived from MacOS */
while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) &&
(!(NCR5380_read(STATUS_REG) & SR_REQ) ||
(NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)))
;
if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)) {
pr_err("Error in macscsi_pwrite\n");
return -1;
}
CP_MEM_TO_IO(s, d, len);
if (len != 0) {
pr_notice("Bus error in macscsi_pwrite\n");
return -1;
}
return 0;
}
static void sun3_scsi_reset_boot(struct Scsi_Host *instance)
{
unsigned long end;
NCR5380_local_declare();
NCR5380_setup(instance);
/*
* Do a SCSI reset to clean up the bus during initialization. No
* messing with the queues, interrupts, or locks necessary here.
*/
printk( "Sun3 SCSI: resetting the SCSI bus..." );
/* switch off SCSI IRQ - catch an interrupt without IRQ bit set else */
// sun3_disable_irq( IRQ_SUN3_SCSI );
/* get in phase */
NCR5380_write( TARGET_COMMAND_REG,
PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
/* assert RST */
NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST );
/* The min. reset hold time is 25us, so 40us should be enough */
udelay( 50 );
/* reset RST and interrupt */
NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE );
NCR5380_read( RESET_PARITY_INTERRUPT_REG );
for( end = jiffies + AFTER_RESET_DELAY; time_before(jiffies, end); )
barrier();
/* switch on SCSI IRQ again */
// sun3_enable_irq( IRQ_SUN3_SCSI );
printk( " done\n" );
}
static __inline__ int macscsi_pread(struct Scsi_Host *instance, unsigned char *addr,
int len)
{
volatile unsigned char *dma_io = mac_scsi_drq + 0x60;
NCR5380_local_declare();
NCR5380_setup(instance);
len = pdma_read_count;
dprintk(NDEBUG_PSEUDO_DMA, ("scsi%d : about to pread %d bytes...", instance->host_no, len));
if(!len) return 0;
counter = 0;
while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)
&& !(NCR5380_read(STATUS_REG) & SR_REQ)) {
counter++;
}
if (counter)
printk("_%d_", (unsigned int)counter);
counter = 0;
if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)
&& (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)) {
printk(KERN_ERR "Error in macscsi_pread\n");
pdma_read_count = 0;
return -1;
}
// m2_poll_start();
// pmu_suspend();
pdma_read_residue = len;
dprintk(NDEBUG_PSEUDO_DMA, ("preading: "));
cycle_counter = 0;
while(pdma_read_residue >= 1)
{
int status;
#ifdef DRQ_INTERRUPT
spin_lock_irq(&io_request_lock);
#endif
if(pdma_read_residue == 0) {
#ifdef DRQ_INTERRUPT
spin_unlock_irq(&io_request_lock);
#endif
break;
}
cycle_counter++;
counter = 0;
while (!((status = NCR5380_read(BUS_AND_STATUS_REG)) & BASR_DRQ)) {
// pmu_poll();
counter++;
if (!(status & BASR_PHASE_MATCH)) {
(void) NCR5380_read(RESET_PARITY_INTERRUPT_REG);
len = pdma_read_residue;
pdma_read_residue = 0;
#ifdef DRQ_INTERRUPT
spin_unlock_irq(&io_request_lock);
#endif
// m2_poll_stop();
// pmu_resume();
return len;
}
if (!(NCR5380_read(MODE_REG) & MR_DMA_MODE)) {
len = pdma_read_residue;
pdma_read_residue = 0;
#ifdef DRQ_INTERRUPT
spin_unlock_irq(&io_request_lock);
#endif
// m2_poll_stop();
// pmu_resume();
return len;
}
// udelay(1);
}
*pdma_dst++ = in_8((void *)dma_io);
pdma_read_residue -= 1;
average += counter;
#ifdef DRQ_INTERRUPT
spin_unlock_irq(&io_request_lock);
#endif
// while (NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ);
}
average /= cycle_counter;
// printk(".%d.\n", average);
average = 0;
len = pdma_read_residue;
pdma_read_residue = 0;
// m2_poll_stop();
// pmu_resume();
return len;
}