DEFINEFN
vinfo_t* psyco_call_psyco(PsycoObject* po, CodeBufferObject* codebuf,
Source argsources[], int argcount,
struct stack_frame_info_s* finfo)
{
word_t* arg;
int i, initial_depth;
Source* p;
BEGIN_CODE
NEED_CC(); /* 'flag' and 'retval' are a single shared register */
ABOUT_TO_CALL_SUBFUNCTION(finfo);
/* no stack push between the INSN_pyenter above and the INSN_vmcall
below, apart from function arguments! See iprocessor.c:impl_vmcall */
initial_depth = po->stack_depth;
p = argsources;
for (i=argcount; i--; p++) {
INSN_rt_push(*p); INSNPUSHED(1);
}
INSN_vmcall(&arg);
*arg = (word_t) codebuf->codestart;
po->stack_depth = initial_depth; /* callee removes arguments */
RETURNED_FROM_SUBFUNCTION();
INSN_pushretval(); INSNPUSHED(1);
END_CODE
META_assertdepth(po->stack_depth);
return generic_call_check(po, CfReturnRef|CfPyErrIfNull,
bfunction_result(po, true));
}
/*
* users should call the longSubtractAnalyser or longSubtractAnalyserWithExplicitOperands APIs instead of calling this one directly
*/
TR::Register* TR_X86SubtractAnalyser::longSubtractAnalyserImpl(TR::Node *root, TR::Node *&firstChild, TR::Node *&secondChild)
{
TR::Register *firstRegister = firstChild->getRegister();
TR::Register *secondRegister = secondChild->getRegister();
TR::Register *targetRegister = NULL;
bool firstHighZero = false;
bool secondHighZero = false; bool useSecondHighOrder = false;
TR_X86OpCodes regRegOpCode = SUB4RegReg;
TR_X86OpCodes regMemOpCode = SUB4RegMem;
bool needsEflags = NEED_CC(root) || (root->getOpCodeValue() == TR::lusubb);
// Can generate better code for long adds when one or more children have a high order zero word
// can avoid the evaluation when we don't need the result of such nodes for another parent.
//
if (firstChild->isHighWordZero() && !needsEflags)
{
firstHighZero = true;
}
if (secondChild->isHighWordZero() && !needsEflags)
{
secondHighZero = true;
TR::ILOpCodes secondOp = secondChild->getOpCodeValue();
if (secondChild->getReferenceCount() == 1 && secondRegister == 0)
{
if (secondOp == TR::iu2l || secondOp == TR::su2l ||
secondOp == TR::bu2l ||
(secondOp == TR::lushr &&
secondChild->getSecondChild()->getOpCodeValue() == TR::iconst &&
(secondChild->getSecondChild()->getInt() & TR::TreeEvaluator::shiftMask(true)) == 32))
{
secondChild = secondChild->getFirstChild();
secondRegister = secondChild->getRegister();
if (secondOp == TR::lushr)
{
useSecondHighOrder = true;
}
}
}
}
setInputs(firstChild, firstRegister, secondChild, secondRegister);
if (isVolatileMemoryOperand(firstChild))
resetMem1();
if (isVolatileMemoryOperand(secondChild))
resetMem2();
if (getEvalChild1())
{
firstRegister = _cg->evaluate(firstChild);
}
if (getEvalChild2())
{
secondRegister = _cg->evaluate(secondChild);
}
if (secondHighZero && secondRegister && secondRegister->getRegisterPair())
{
if (!useSecondHighOrder)
{
secondRegister = secondRegister->getLowOrder();
}
else
{
secondRegister = secondRegister->getHighOrder();
}
}
if (root->getOpCodeValue() == TR::lusubb &&
TR_X86ComputeCC::setCarryBorrow(root->getChild(2), true, _cg))
{
// use SBB rather than SUB
//
regRegOpCode = SBB4RegReg;
regMemOpCode = SBB4RegMem;
}
if (getCopyReg1())
{
TR::Register *lowThird = _cg->allocateRegister();
TR::Register *highThird = _cg->allocateRegister();
TR::RegisterPair *thirdReg = _cg->allocateRegisterPair(lowThird, highThird);
targetRegister = thirdReg;
generateRegRegInstruction(MOV4RegReg, root, lowThird, firstRegister->getLowOrder(), _cg);
if (firstHighZero)
{
generateRegRegInstruction(XOR4RegReg, root, highThird, highThird, _cg);
}
else
{
generateRegRegInstruction(MOV4RegReg, root, highThird, firstRegister->getHighOrder(), _cg);
}
if (getSubReg3Reg2())
{
if (secondHighZero)
{
generateRegRegInstruction(regRegOpCode, root, lowThird, secondRegister, _cg);
generateRegImmInstruction(SBB4RegImms, root, highThird, 0, _cg);
}
else
{
generateRegRegInstruction(regRegOpCode, root, lowThird, secondRegister->getLowOrder(), _cg);
generateRegRegInstruction(SBB4RegReg, root, highThird, secondRegister->getHighOrder(), _cg);
}
}
else // assert getSubReg3Mem2() == true
{
TR::MemoryReference *lowMR = generateX86MemoryReference(secondChild, _cg);
/**
* The below code is needed to ensure correct behaviour when the subtract analyser encounters a lushr bytecode that shifts
* by 32 bits. This is the only case where the useSecondHighOrder bit is set.
* When the first child of the lushr is in a register, code above handles the shift. When the first child of the lushr is in
* memory, the below ensures that the upper part of the first child of the lushr is used as lowMR.
*/
if (useSecondHighOrder)
{
TR_ASSERT(secondHighZero, "useSecondHighOrder should be consistent with secondHighZero. useSecondHighOrder subsumes secondHighZero");
lowMR = generateX86MemoryReference(*lowMR, 4, _cg);
}
generateRegMemInstruction(regMemOpCode, root, lowThird, lowMR, _cg);
if (secondHighZero)
{
generateRegImmInstruction(SBB4RegImms, root, highThird, 0, _cg);
}
else
{
TR::MemoryReference *highMR = generateX86MemoryReference(*lowMR, 4, _cg);
generateRegMemInstruction(SBB4RegMem, root, highThird, highMR, _cg);
}
lowMR->decNodeReferenceCounts(_cg);
}
}
else if (getSubReg1Reg2())
{
if (secondHighZero)
{
generateRegRegInstruction(regRegOpCode, root, firstRegister->getLowOrder(), secondRegister, _cg);
generateRegImmInstruction(SBB4RegImms, root, firstRegister->getHighOrder(), 0, _cg);
}
else
{
generateRegRegInstruction(regRegOpCode, root, firstRegister->getLowOrder(), secondRegister->getLowOrder(), _cg);
generateRegRegInstruction(SBB4RegReg, root, firstRegister->getHighOrder(), secondRegister->getHighOrder(), _cg);
}
targetRegister = firstRegister;
}
else // assert getSubReg1Mem2() == true
{
TR::MemoryReference *lowMR = generateX86MemoryReference(secondChild, _cg);
/**
* The below code is needed to ensure correct behaviour when the subtract analyser encounters a lushr bytecode that shifts
* by 32 bits. This is the only case where the useSecondHighOrder bit is set.
* When the first child of the lushr is in a register, code above handles the shift. When the first child of the lushr is in
* memory, the below ensures that the upper part of the first child of the lushr is used as lowMR.
*/
if (useSecondHighOrder)
lowMR = generateX86MemoryReference(*lowMR, 4, _cg);
generateRegMemInstruction(regMemOpCode, root, firstRegister->getLowOrder(), lowMR, _cg);
if (secondHighZero)
{
generateRegImmInstruction(SBB4RegImms, root, firstRegister->getHighOrder(), 0, _cg);
}
else
{
TR::MemoryReference *highMR = generateX86MemoryReference(*lowMR, 4, _cg);
generateRegMemInstruction(SBB4RegMem, root, firstRegister->getHighOrder(), highMR, _cg);
}
targetRegister = firstRegister;
lowMR->decNodeReferenceCounts(_cg);
}
return targetRegister;
}
/*
* users should call the integerSubtractAnalyser or integerSubtractAnalyserWithExplicitOperands APIs instead of calling this one directly
*/
TR::Register* TR_X86SubtractAnalyser::integerSubtractAnalyserImpl(TR::Node *root,
TR::Node *firstChild,
TR::Node *secondChild,
TR_X86OpCodes regRegOpCode,
TR_X86OpCodes regMemOpCode,
TR_X86OpCodes copyOpCode,
bool needsEflags,
TR::Node *borrow)
{
TR::Register *targetRegister = NULL;
TR::Register *firstRegister = firstChild->getRegister();
TR::Register *secondRegister = secondChild->getRegister();
setInputs(firstChild, firstRegister, secondChild, secondRegister);
bool loadedConst = false;
needsEflags = needsEflags || NEED_CC(root);
if (getEvalChild1())
{
// if firstChild and secondChild are the same node, then we should
// evaluate (take the else path) so that the evaluate for the secondChild
// below will get the correct/already-allocated register.
if (firstRegister == 0 && firstChild->getOpCodeValue() == TR::iconst && (firstChild != secondChild))
{
// An iconst may have to be generated. The iconst will be generated after the
// secondChild is evaluated. Set the loadedConst flag to true.
loadedConst = true;
}
else
{
firstRegister = _cg->evaluate(firstChild);
}
}
if (getEvalChild2())
{
secondRegister = _cg->evaluate(secondChild);
if (firstChild->getRegister())
{
firstRegister = firstChild->getRegister();
}
else if (!loadedConst)
{
firstRegister = _cg->evaluate(firstChild);
}
}
if (loadedConst)
{
if (firstRegister == 0)
{
// firstchild is an inconst and it has not been evaluated.
// Generate the code for an iconst.
firstRegister = _cg->allocateRegister();
TR::TreeEvaluator::insertLoadConstant(firstChild, firstRegister, firstChild->getInt(), TR_RematerializableInt, _cg);
}
else
{
// firstchild was evaluated. The code for an iconst does not need to be generated.
// Set the loadConst flag to false.
loadedConst = false;
}
}
if (borrow != 0)
TR_X86ComputeCC::setCarryBorrow(borrow, true, _cg);
if (getCopyReg1())
{
if (firstChild->getReferenceCount() > 1)
{
TR::Register *thirdReg;
if (firstChild->getOpCodeValue() == TR::iconst && loadedConst)
{
thirdReg = firstRegister;
}
else
{
if (secondChild->getReferenceCount() == 1 && secondRegister != 0 && !needsEflags && (borrow == 0))
{
// use one fewer registers if we negate the clobberable secondRegister and add
// Don't do this though if condition codes are needed. The sequence
// depends on the carry flag being valid as if a sub was done.
//
bool nodeIs64Bit = TR_X86OpCode(regRegOpCode).hasLongSource();
generateRegInstruction(NEGReg(nodeIs64Bit), secondChild, secondRegister, _cg);
thirdReg = secondRegister;
secondRegister = firstRegister;
regRegOpCode = ADDRegReg(nodeIs64Bit);
}
else
{
thirdReg = _cg->allocateRegister();
generateRegRegInstruction(copyOpCode, root, thirdReg, firstRegister, _cg);
}
}
targetRegister = thirdReg;
if (getSubReg3Reg2())
{
generateRegRegInstruction(regRegOpCode, root, thirdReg, secondRegister, _cg);
}
else // assert getSubReg3Mem2() == true
{
TR::MemoryReference *tempMR = generateX86MemoryReference(secondChild, _cg);
generateRegMemInstruction(regMemOpCode, root, thirdReg, tempMR, _cg);
tempMR->decNodeReferenceCounts(_cg);
}
}
else
{
if (getSubReg3Reg2())
{
generateRegRegInstruction(regRegOpCode, root, firstRegister, secondRegister, _cg);
}
else // assert getSubReg3Mem2() == true
{
TR::MemoryReference *tempMR = generateX86MemoryReference(secondChild, _cg);
generateRegMemInstruction(regMemOpCode, root, firstRegister, tempMR, _cg);
tempMR->decNodeReferenceCounts(_cg);
}
targetRegister = firstRegister;
}
}
else if (getSubReg1Reg2())
{
generateRegRegInstruction(regRegOpCode, root, firstRegister, secondRegister, _cg);
targetRegister = firstRegister;
}
else // assert getSubReg1Mem2() == true
{
TR::MemoryReference *tempMR = generateX86MemoryReference(secondChild, _cg);
generateRegMemInstruction(regMemOpCode, root, firstRegister, tempMR, _cg);
targetRegister = firstRegister;
tempMR->decNodeReferenceCounts(_cg);
}
return targetRegister;
}
void
TR_S390BinaryAnalyser::longSubtractAnalyser(TR::Node * root)
{
TR::Node * firstChild;
TR::Node * secondChild;
TR::Instruction * cursor = NULL;
TR::RegisterDependencyConditions * dependencies = NULL;
bool setsOrReadsCC = NEED_CC(root) || (root->getOpCodeValue() == TR::lusubb);
TR::InstOpCode::Mnemonic regToRegOpCode;
TR::InstOpCode::Mnemonic memToRegOpCode;
TR::Compilation *comp = TR::comp();
if (TR::Compiler->target.is64Bit() || cg()->use64BitRegsOn32Bit())
{
if (!setsOrReadsCC)
{
regToRegOpCode = TR::InstOpCode::SGR;
memToRegOpCode = TR::InstOpCode::SG;
}
else
{
regToRegOpCode = TR::InstOpCode::SLGR;
memToRegOpCode = TR::InstOpCode::SLG;
}
}
else
{
regToRegOpCode = TR::InstOpCode::SLR;
memToRegOpCode = TR::InstOpCode::SL;
}
firstChild = root->getFirstChild();
secondChild = root->getSecondChild();
TR::Register * firstRegister = firstChild->getRegister();
TR::Register * secondRegister = secondChild->getRegister();
setInputs(firstChild, firstRegister, secondChild, secondRegister,
false, false, comp);
/** Attempt to use SGH to subtract halfword (64 <- 16).
* The second child is a halfword from memory */
bool is16BitMemory2Operand = false;
if (TR::Compiler->target.cpu.getS390SupportsZ14() &&
secondChild->getOpCodeValue() == TR::s2l &&
secondChild->getFirstChild()->getOpCodeValue() == TR::sloadi &&
secondChild->isSingleRefUnevaluated() &&
secondChild->getFirstChild()->isSingleRefUnevaluated())
{
setMem2();
memToRegOpCode = TR::InstOpCode::SGH;
is16BitMemory2Operand = true;
}
if (getEvalChild1())
{
firstRegister = cg()->evaluate(firstChild);
}
if (getEvalChild2())
{
secondRegister = cg()->evaluate(secondChild);
}
remapInputs(firstChild, firstRegister, secondChild, secondRegister);
if ((root->getOpCodeValue() == TR::lusubb) &&
TR_S390ComputeCC::setCarryBorrow(root->getChild(2), false, cg()))
{
// use SLBGR rather than SLGR/SGR
// SLBG rather than SLG/SG
// or
// use SLBR rather than SLR
// SLB rather than SL
bool uses64bit = TR::Compiler->target.is64Bit() || cg()->use64BitRegsOn32Bit();
regToRegOpCode = uses64bit ? TR::InstOpCode::SLBGR : TR::InstOpCode::SLBR;
memToRegOpCode = uses64bit ? TR::InstOpCode::SLBG : TR::InstOpCode::SLB;
}
if (TR::Compiler->target.is64Bit() || cg()->use64BitRegsOn32Bit())
{
if (getCopyReg1())
{
TR::Register * thirdReg = cg()->allocate64bitRegister();
root->setRegister(thirdReg);
generateRRInstruction(cg(), TR::InstOpCode::LGR, root, thirdReg, firstRegister);
if (getBinaryReg3Reg2())
{
generateRRInstruction(cg(), regToRegOpCode, root, thirdReg, secondRegister);
}
else // assert getBinaryReg3Mem2() == true
{
TR::MemoryReference * longMR = generateS390MemoryReference(secondChild, cg());
generateRXInstruction(cg(), memToRegOpCode, root, thirdReg, longMR);
longMR->stopUsingMemRefRegister(cg());
}
}
else if (getBinaryReg1Reg2())
{
generateRRInstruction(cg(), regToRegOpCode, root, firstRegister, secondRegister);
root->setRegister(firstRegister);
}
else // assert getBinaryReg1Mem2() == true
{
TR_ASSERT( !getInvalid(), "TR_S390BinaryAnalyser::invalid case\n");
TR::Node* baseAddrNode = is16BitMemory2Operand ? secondChild->getFirstChild() : secondChild;
TR::MemoryReference * longMR = generateS390MemoryReference(baseAddrNode, cg());
generateRXInstruction(cg(), memToRegOpCode, root, firstRegister, longMR);
longMR->stopUsingMemRefRegister(cg());
root->setRegister(firstRegister);
if(is16BitMemory2Operand)
{
cg()->decReferenceCount(secondChild->getFirstChild());
}
}
}
else // if 32bit codegen...
{
bool zArchTrexsupported = performTransformation(comp, "O^O Use SL/SLB for long sub.");
TR::Register * highDiff = NULL;
TR::LabelSymbol * doneLSub = TR::LabelSymbol::create(cg()->trHeapMemory(),cg());
if (getCopyReg1())
{
TR::Register * lowThird = cg()->allocateRegister();
TR::Register * highThird = cg()->allocateRegister();
TR::RegisterPair * thirdReg = cg()->allocateConsecutiveRegisterPair(lowThird, highThird);
highDiff = highThird;
dependencies = new (cg()->trHeapMemory()) TR::RegisterDependencyConditions(0, 9, cg());
dependencies->addPostCondition(firstRegister, TR::RealRegister::EvenOddPair);
dependencies->addPostCondition(firstRegister->getHighOrder(), TR::RealRegister::LegalEvenOfPair);
dependencies->addPostCondition(firstRegister->getLowOrder(), TR::RealRegister::LegalOddOfPair);
// If 2nd operand has ref count of 1 and can be accessed by a memory reference,
// then second register will not be used.
if(secondRegister == firstRegister && !setsOrReadsCC)
{
TR_ASSERT( false, "lsub with identical children - fix Simplifier");
}
if (secondRegister != NULL && firstRegister != secondRegister)
{
dependencies->addPostCondition(secondRegister, TR::RealRegister::EvenOddPair);
dependencies->addPostCondition(secondRegister->getHighOrder(), TR::RealRegister::LegalEvenOfPair);
dependencies->addPostCondition(secondRegister->getLowOrder(), TR::RealRegister::LegalOddOfPair);
}
dependencies->addPostCondition(highThird, TR::RealRegister::AssignAny);
root->setRegister(thirdReg);
generateRRInstruction(cg(), TR::InstOpCode::LR, root, highThird, firstRegister->getHighOrder());
generateRRInstruction(cg(), TR::InstOpCode::LR, root, lowThird, firstRegister->getLowOrder());
if (getBinaryReg3Reg2())
{
if ((ENABLE_ZARCH_FOR_32 && zArchTrexsupported) || setsOrReadsCC)
{
generateRRInstruction(cg(), regToRegOpCode, root, lowThird, secondRegister->getLowOrder());
generateRRInstruction(cg(), TR::InstOpCode::SLBR, root, highThird, secondRegister->getHighOrder());
}
else
{
generateRRInstruction(cg(), TR::InstOpCode::SR, root, highThird, secondRegister->getHighOrder());
generateRRInstruction(cg(), TR::InstOpCode::SLR, root, lowThird, secondRegister->getLowOrder());
}
}
else // assert getBinaryReg3Mem2() == true
{
TR::MemoryReference * highMR = generateS390MemoryReference(secondChild, cg());
TR::MemoryReference * lowMR = generateS390MemoryReference(*highMR, 4, cg());
dependencies->addAssignAnyPostCondOnMemRef(highMR);
if ((ENABLE_ZARCH_FOR_32 && zArchTrexsupported) || setsOrReadsCC)
{
generateRXInstruction(cg(), memToRegOpCode, root, lowThird, lowMR);
generateRXInstruction(cg(), TR::InstOpCode::SLB, root, highThird, highMR);
}
else
{
generateRXInstruction(cg(), TR::InstOpCode::S, root, highThird, highMR);
generateRXInstruction(cg(), TR::InstOpCode::SL, root, lowThird, lowMR);
}
highMR->stopUsingMemRefRegister(cg());
lowMR->stopUsingMemRefRegister(cg());
}
}
else if (getBinaryReg1Reg2())
{
dependencies = new (cg()->trHeapMemory()) TR::RegisterDependencyConditions(0, 6, cg());
dependencies->addPostCondition(firstRegister, TR::RealRegister::EvenOddPair);
dependencies->addPostCondition(firstRegister->getHighOrder(), TR::RealRegister::LegalEvenOfPair);
dependencies->addPostCondition(firstRegister->getLowOrder(), TR::RealRegister::LegalOddOfPair);
if(secondRegister == firstRegister)
{
TR_ASSERT( false, "lsub with identical children - fix Simplifier");
}
if (secondRegister != firstRegister)
{
dependencies->addPostCondition(secondRegister, TR::RealRegister::EvenOddPair);
dependencies->addPostCondition(secondRegister->getHighOrder(), TR::RealRegister::LegalEvenOfPair);
dependencies->addPostCondition(secondRegister->getLowOrder(), TR::RealRegister::LegalOddOfPair);
}
if ((ENABLE_ZARCH_FOR_32 && zArchTrexsupported) || setsOrReadsCC)
{
generateRRInstruction(cg(), regToRegOpCode, root, firstRegister->getLowOrder(), secondRegister->getLowOrder());
generateRRInstruction(cg(), TR::InstOpCode::SLBR, root, firstRegister->getHighOrder(), secondRegister->getHighOrder());
}
else
{
generateRRInstruction(cg(), TR::InstOpCode::SR, root, firstRegister->getHighOrder(), secondRegister->getHighOrder());
generateRRInstruction(cg(), TR::InstOpCode::SLR, root, firstRegister->getLowOrder(), secondRegister->getLowOrder());
}
highDiff = firstRegister->getHighOrder();
root->setRegister(firstRegister);
}
else // assert getBinaryReg1Mem2() == true
{
TR_ASSERT( !getInvalid(),"TR_S390BinaryAnalyser::invalid case\n");
dependencies = new (cg()->trHeapMemory()) TR::RegisterDependencyConditions(0, 5, cg());
dependencies->addPostCondition(firstRegister, TR::RealRegister::EvenOddPair);
dependencies->addPostCondition(firstRegister->getHighOrder(), TR::RealRegister::LegalEvenOfPair);
dependencies->addPostCondition(firstRegister->getLowOrder(), TR::RealRegister::LegalOddOfPair);
TR::MemoryReference * highMR = generateS390MemoryReference(secondChild, cg());
TR::MemoryReference * lowMR = generateS390MemoryReference(*highMR, 4, cg());
dependencies->addAssignAnyPostCondOnMemRef(highMR);
if ((ENABLE_ZARCH_FOR_32 && zArchTrexsupported) || setsOrReadsCC)
{
generateRXInstruction(cg(), memToRegOpCode, root, firstRegister->getLowOrder(), lowMR);
generateRXInstruction(cg(), TR::InstOpCode::SLB, root, firstRegister->getHighOrder(), highMR);
}
else
{
generateRXInstruction(cg(), TR::InstOpCode::S, root, firstRegister->getHighOrder(), highMR);
generateRXInstruction(cg(), TR::InstOpCode::SL, root, firstRegister->getLowOrder(), lowMR);
}
highDiff = firstRegister->getHighOrder();
root->setRegister(firstRegister);
highMR->stopUsingMemRefRegister(cg());
lowMR->stopUsingMemRefRegister(cg());
}
if (!((ENABLE_ZARCH_FOR_32 && zArchTrexsupported) || setsOrReadsCC))
{
// Check for overflow in LS int. If overflow, we are done.
generateS390BranchInstruction(cg(), TR::InstOpCode::BRC,TR::InstOpCode::COND_MASK3, root, doneLSub);
// Increment MS int due to overflow in LS int
generateRIInstruction(cg(), TR::InstOpCode::AHI, root, highDiff, -1);
generateS390LabelInstruction(cg(), TR::InstOpCode::LABEL, root, doneLSub, dependencies);
}
}
cg()->decReferenceCount(firstChild);
cg()->decReferenceCount(secondChild);
return;
}
