static void ni_tio_configure_dma(struct ni_gpct *counter, bool enable, bool read) { struct ni_gpct_device *counter_dev = counter->counter_dev; unsigned int cidx = counter->counter_index; unsigned int mask; unsigned int bits; mask = GI_READ_ACKS_IRQ | GI_WRITE_ACKS_IRQ; bits = 0; if (enable) { if (read) bits |= GI_READ_ACKS_IRQ; else bits |= GI_WRITE_ACKS_IRQ; } ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), mask, bits); switch (counter_dev->variant) { case ni_gpct_variant_e_series: break; case ni_gpct_variant_m_series: case ni_gpct_variant_660x: mask = GI_DMA_ENABLE | GI_DMA_INT_ENA | GI_DMA_WRITE; bits = 0; if (enable) bits |= GI_DMA_ENABLE | GI_DMA_INT_ENA; if (!read) bits |= GI_DMA_WRITE; ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), mask, bits); break; } }
static void ni_tio_configure_dma(struct ni_gpct *counter, short enable, short read_not_write) { struct ni_gpct_device *counter_dev = counter->counter_dev; unsigned cidx = counter->counter_index; unsigned input_select_bits = 0; if (enable) { if (read_not_write) input_select_bits |= Gi_Read_Acknowledges_Irq; else input_select_bits |= Gi_Write_Acknowledges_Irq; } ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), Gi_Read_Acknowledges_Irq | Gi_Write_Acknowledges_Irq, input_select_bits); switch (counter_dev->variant) { case ni_gpct_variant_e_series: break; case ni_gpct_variant_m_series: case ni_gpct_variant_660x: { unsigned gi_dma_config_bits = 0; if (enable) { gi_dma_config_bits |= Gi_DMA_Enable_Bit; gi_dma_config_bits |= Gi_DMA_Int_Bit; } if (read_not_write == 0) gi_dma_config_bits |= Gi_DMA_Write_Bit; ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), Gi_DMA_Enable_Bit | Gi_DMA_Int_Bit | Gi_DMA_Write_Bit, gi_dma_config_bits); } break; } }