static int ni_tio_cmd_setup(struct ni_gpct *counter, comedi_async * async) { comedi_cmd *cmd = &async->cmd; int set_gate_source = 0; unsigned gate_source; int retval = 0; if (cmd->scan_begin_src == TRIG_EXT) { set_gate_source = 1; gate_source = cmd->scan_begin_arg; } else if (cmd->convert_src == TRIG_EXT) { set_gate_source = 1; gate_source = cmd->convert_arg; } if (set_gate_source) { retval = ni_tio_set_gate_src(counter, 0, gate_source); } if (cmd->flags & TRIG_WAKE_EOS) { ni_tio_set_bits(counter, NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index), Gi_Gate_Interrupt_Enable_Bit(counter->counter_index), Gi_Gate_Interrupt_Enable_Bit(counter->counter_index)); } return retval; }
void ni_tio_init_counter(struct ni_gpct *counter) { struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_reset_count_and_disarm(counter); /* initialize counter registers */ counter_dev->regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)] = 0x0; write_register(counter, counter_dev-> regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)], NITIO_Gi_Autoincrement_Reg(counter->counter_index)); ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index), ~0, Gi_Synchronize_Gate_Bit); ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index), ~0, 0); counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] = 0x0; write_register(counter, counter_dev-> regs[NITIO_Gi_LoadA_Reg(counter->counter_index)], NITIO_Gi_LoadA_Reg(counter->counter_index)); counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] = 0x0; write_register(counter, counter_dev-> regs[NITIO_Gi_LoadB_Reg(counter->counter_index)], NITIO_Gi_LoadB_Reg(counter->counter_index)); ni_tio_set_bits(counter, NITIO_Gi_Input_Select_Reg(counter->counter_index), ~0, 0); if (ni_tio_counting_mode_registers_present(counter_dev)) { ni_tio_set_bits(counter, NITIO_Gi_Counting_Mode_Reg(counter-> counter_index), ~0, 0); } if (ni_tio_second_gate_registers_present(counter_dev)) { counter_dev-> regs[NITIO_Gi_Second_Gate_Reg(counter->counter_index)] = 0x0; write_register(counter, counter_dev-> regs[NITIO_Gi_Second_Gate_Reg (counter->counter_index)], NITIO_Gi_Second_Gate_Reg(counter-> counter_index)); } ni_tio_set_bits(counter, NITIO_Gi_DMA_Config_Reg(counter->counter_index), ~0, 0x0); ni_tio_set_bits(counter, NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index), ~0, 0x0); }
int ni_tio_cancel(struct ni_gpct *counter) { unsigned long flags; ni_tio_arm(counter, 0, 0); comedi_spin_lock_irqsave(&counter->lock, flags); if (counter->mite_chan) { mite_dma_disarm(counter->mite_chan); } comedi_spin_unlock_irqrestore(&counter->lock, flags); ni_tio_configure_dma(counter, 0, 0); ni_tio_set_bits(counter, NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index), Gi_Gate_Interrupt_Enable_Bit(counter->counter_index), 0x0); return 0; }