static void
chx_set_intr_prio (uint8_t n)
{
unsigned int sh = (n & 3) << 3;
NVIC_IPR (n) = (NVIC_IPR(n) & ~(0xFF << sh))
| (CPU_EXCEPTION_PRIORITY_INTERRUPT << sh);
}
void nvic_set_priority_interrupt(unsigned int num, unsigned char priority)
{
if (num < 0)
writel(SCB_SHPR(num), priority);
else
writel(NVIC_IPR(num), priority);
}
/*
* Enable interrupt
* Enables the interrupt specified in intvec.
*/
EXPORT void EnableInt( INTVEC intvec, INT intpri )
{
UINT imask, shift;
UW pri;
DI(imask);
/* Set interrupt priority level. */
shift = (intvec % 4) * 8;
pri = *(_UW*)(NVIC_IPR(intvec));
pri &= ~(0xff << shift);
pri |= (intpri & 0xff) << shift;
*(_UW*)(NVIC_IPR(intvec)) = pri;
/* Enables the specified interrupt. */
*(_UW*)(NVIC_ISER(intvec)) = (0x01U << (intvec % 32));
EI(imask);
}
void nvic_set_priority(uint8_t irqn, uint8_t priority)
{
/* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the
* negative interrupt numbers assigned to the system interrupts. better
* handling would mean signed integers. */
if (irqn >= NVIC_IRQ_COUNT) {
/* Cortex-M system interrupts */
SCS_SHPR((irqn & 0xF) - 4) = priority;
} else {
/* Device specific interrupts */
NVIC_IPR(irqn) = priority;
}
}
