void NvOdmQueryClockLimits( NvOdmIoModule IoModule, const NvU32 **pClockSpeedLimits, NvU32 *pCount) { switch (IoModule) { case NvOdmIoModule_Hsmmc: *pCount = 0; break; case NvOdmIoModule_Sdio: *pClockSpeedLimits = s_NvOdmClockLimit_Sdio; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmClockLimit_Sdio); break; default: *pClockSpeedLimits = NULL; *pCount = 0; break; } }
void NvOdmQueryPinMux( NvOdmIoModule IoModule, const NvU32 **pPinMuxConfigTable, NvU32 *pCount) { switch (IoModule) { case NvOdmIoModule_Display: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Display; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Display); break; case NvOdmIoModule_Dap: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Dap; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Dap); break; case NvOdmIoModule_Hdcp: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Hdcp; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Hdcp); break; case NvOdmIoModule_Hdmi: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Hdmi; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Hdmi); break; case NvOdmIoModule_I2c: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_I2c; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_I2c); break; case NvOdmIoModule_I2c_Pmu: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_I2cPmu; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_I2cPmu); break; case NvOdmIoModule_Nand: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Nand; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Nand); break; case NvOdmIoModule_Sdio: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Sdio; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Sdio); break; case NvOdmIoModule_Spi: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Spi; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Spi); break; case NvOdmIoModule_Uart: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Uart; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Uart); break; case NvOdmIoModule_ExternalClock: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_ExternalClock; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_ExternalClock); break; case NvOdmIoModule_Crt: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Crt; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Crt); break; case NvOdmIoModule_PciExpress: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_PciExpress; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_PciExpress); break; case NvOdmIoModule_Tvo: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Tvo; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Tvo); break; case NvOdmIoModule_BacklightPwm: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_BacklightPwm; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_BacklightPwm); break; case NvOdmIoModule_Pwm: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Pwm; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Pwm); break; case NvOdmIoModule_Ulpi: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Ulpi; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Ulpi); break; case NvOdmIoModule_Spdif: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Spdif; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Spdif); break; case NvOdmIoModule_Kbd: *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Kbd; *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Kbd); break; case NvOdmIoModule_Twc: case NvOdmIoModule_Hsi: case NvOdmIoModule_Ata: case NvOdmIoModule_SyncNor: case NvOdmIoModule_Mio: case NvOdmIoModule_VideoInput: case NvOdmIoModule_OneWire: *pPinMuxConfigTable = NULL; *pCount = 0; break; default: *pCount = 0; break; } }