int
nv_save_libsvm_fp(FILE *fp,
const nv_matrix_t *data,
const nv_matrix_t *labels)
{
int j;
NV_ASSERT(labels->m >= data->m);
for (j = 0; j < data->m; ++j) {
int i;
int loop16 = (data->n & 0xfffffff0);
fprintf(fp, "%d ", NV_MAT_VI(labels, j, 0) + 1);
for (i = 0; i < loop16; i += 16) {
if (i != 0) {
fprintf(fp, " ");
}
fprintf(fp,
"%d:%E %d:%E %d:%E %d:%E %d:%E %d:%E %d:%E %d:%E %d:%E %d:%E %d:%E %d:%E %d:%E %d:%E %d:%E %d:%E",
i + 1,
NV_MAT_V(data, j, i + 0),
i + 2,
NV_MAT_V(data, j, i + 1),
i + 3,
NV_MAT_V(data, j, i + 2),
i + 4,
NV_MAT_V(data, j, i + 3),
i + 5,
NV_MAT_V(data, j, i + 4),
i + 6,
NV_MAT_V(data, j, i + 5),
i + 7,
NV_MAT_V(data, j, i + 6),
i + 8,
NV_MAT_V(data, j, i + 7),
i + 9,
NV_MAT_V(data, j, i + 8),
i + 10,
NV_MAT_V(data, j, i + 9),
i + 11,
NV_MAT_V(data, j, i + 10),
i + 12,
NV_MAT_V(data, j, i + 11),
i + 13,
NV_MAT_V(data, j, i + 12),
i + 14,
NV_MAT_V(data, j, i + 13),
i + 15,
NV_MAT_V(data, j, i + 14),
i + 16,
NV_MAT_V(data, j, i + 15));
}
for (i = loop16; i < data->n; ++i) {
if (i != 0) {
fprintf(fp, " ");
}
fprintf(fp, "%d:%E", i + 1, NV_MAT_V(data, j, i));
}
fprintf(fp, "\n");
}
return 0;
}
/**
* @brief Allocates a handle to the device. Configures the PWM
* control to the Vibro motor with default values. To change
* the amplitude and frequency use NvOdmVibrateSetParameter API.
* @param hOdmVibrate [IN] Opaque handle to the device.
* @return NV_TRUE on success and NV_FALSE on error
*/
NvBool
NvOdmVibOpen(NvOdmVibDeviceHandle *hOdmVibrate)
{
#if 1 /* yuyang(20100615):Create I2C handle */
const NvOdmPeripheralConnectivity *pConnectivity = NULL;
NvU32 Index = 0;
NvU32 I2cInstance = 0;
NV_ASSERT(hOdmVibrate);
/* Allocate the handle */
(*hOdmVibrate) = (NvOdmVibDeviceHandle)NvOdmOsAlloc(sizeof(NvOdmVibDevice));
if (*hOdmVibrate == NULL)
{
NV_ODM_TRACE(("Error Allocating NvOdmPmuDevice. \n"));
return NV_FALSE;
}
NvOsMemset((*hOdmVibrate), 0, sizeof(NvOdmVibDevice));
/* Get the PMU handle */
(*hOdmVibrate)->hOdmServicePmuDevice = NvOdmServicesPmuOpen();
if (!(*hOdmVibrate)->hOdmServicePmuDevice)
{
NV_ODM_TRACE(("Error Opening Pmu device. \n"));
NvOdmOsFree(*hOdmVibrate);
*hOdmVibrate = NULL;
return NV_FALSE;
}
// Get the peripheral connectivity information
pConnectivity = NvOdmPeripheralGetGuid(VIBRATE_DEVICE_GUID);
if (pConnectivity == NULL)
{
NV_ODM_TRACE(("Error pConnectivity NULL. \n"));
return NV_FALSE;
}
for (Index = 0; Index < pConnectivity->NumAddress; ++Index)
{
switch (pConnectivity->AddressList[Index].Interface)
{
case NvOdmIoModule_I2c:
(*hOdmVibrate)->DeviceAddr = (pConnectivity->AddressList[Index].Address);
I2cInstance = pConnectivity->AddressList[Index].Instance;
NV_ODM_TRACE("%s: hTouch->DeviceAddr = 0x%x, I2cInstance = %x\n", __func__, (*hOdmVibrate)->DeviceAddr, I2cInstance);
break;
case NvOdmIoModule_Vdd:
(*hOdmVibrate)->VddId = pConnectivity->AddressList[Index].Address;
NvOdmServicesPmuGetCapabilities((*hOdmVibrate)->hOdmServicePmuDevice, (*hOdmVibrate)->VddId, &((*hOdmVibrate)->RailCaps));
break;
default:
break;
}
}
(*hOdmVibrate)->hOdmI2c = NvOdmI2cOpen(NvOdmIoModule_I2c_Pmu, I2cInstance);
if (!(*hOdmVibrate)->hOdmI2c)
{
NV_ODM_TRACE(("NvOdm Touch : NvOdmI2cOpen Error \n"));
return NV_FALSE;
}
#else
const NvOdmPeripheralConnectivity *pConnectivity = NULL;
NvU32 Index = 0;
NV_ASSERT(hOdmVibrate);
/* Allocate the handle */
(*hOdmVibrate) = (NvOdmVibDeviceHandle)NvOdmOsAlloc(sizeof(NvOdmVibDevice));
if (*hOdmVibrate == NULL)
{
NV_ODM_TRACE(("Error Allocating NvOdmPmuDevice. \n"));
return NV_FALSE;
}
NvOsMemset((*hOdmVibrate), 0, sizeof(NvOdmVibDevice));
/* Get the PMU handle */
(*hOdmVibrate)->hOdmServicePmuDevice = NvOdmServicesPmuOpen();
if (!(*hOdmVibrate)->hOdmServicePmuDevice)
{
NV_ODM_TRACE(("Error Opening Pmu device. \n"));
NvOdmOsFree(*hOdmVibrate);
*hOdmVibrate = NULL;
return NV_FALSE;
}
// Get the peripheral connectivity information
pConnectivity = NvOdmPeripheralGetGuid(VIBRATE_DEVICE_GUID);
if (pConnectivity == NULL)
return NV_FALSE;
// Search for the Vdd rail and set the proper volage to the rail.
for (Index = 0; Index < pConnectivity->NumAddress; ++Index)
{
if (pConnectivity->AddressList[Index].Interface == NvOdmIoModule_Vdd)
{
(*hOdmVibrate)->VddId = pConnectivity->AddressList[Index].Address;
NvOdmServicesPmuGetCapabilities((*hOdmVibrate)->hOdmServicePmuDevice, (*hOdmVibrate)->VddId, &((*hOdmVibrate)->RailCaps));
break;
}
}
#endif /* __yuyang(20100615) */
return NV_TRUE;
}
const NvRmModuleClockLimits*
NvRmPrivClockLimitsInit(NvRmDeviceHandle hRmDevice)
{
NvU32 i;
NvRmFreqKHz CpuMaxKHz, AvpMaxKHz, VdeMaxKHz, TDMaxKHz, DispMaxKHz;
const NvRmSKUedLimits* pSKUedLimits;
const NvRmScaledClkLimits* pHwLimits;
const NvRmSocShmoo* pShmoo;
NV_ASSERT(hRmDevice);
NvRmPrivChipFlavorInit(hRmDevice);
pShmoo = s_ChipFlavor.pSocShmoo;
pHwLimits = &pShmoo->ScaledLimitsList[0];
pSKUedLimits = pShmoo->pSKUedLimits;
NvOsDebugPrintf("NVRM corner (%d, %d)\n",
s_ChipFlavor.corner, s_ChipFlavor.CpuCorner);
NvOsMemset((void*)s_pClockScales, 0, sizeof(s_pClockScales));
NvOsMemset(s_ClockRangeLimits, 0, sizeof(s_ClockRangeLimits));
NvOsMemset(s_VoltageStepRefCounts, 0, sizeof(s_VoltageStepRefCounts));
s_VoltageStepRefCounts[0] = NvRmPrivModuleID_Num; // all at minimum step
// Combine AVP/System clock absolute limit with scaling V/F ladder upper
// boundary, and set default clock range for all present modules the same
// as for AVP/System clock
AvpMaxKHz = pSKUedLimits->AvpMaxKHz;
for (i = 0; i < pShmoo->ScaledLimitsListSize; i++)
{
if (pHwLimits[i].HwDeviceId == NV_DEVID_AVP)
{
AvpMaxKHz = NV_MIN(
AvpMaxKHz, pHwLimits[i].MaxKHzList[pShmoo->ShmooVmaxIndex]);
break;
}
}
for (i = 0; i < NvRmPrivModuleID_Num; i++)
{
NvRmModuleInstance *inst;
if (NvRmPrivGetModuleInstance(hRmDevice, i, &inst) == NvSuccess)
{
s_ClockRangeLimits[i].MaxKHz = AvpMaxKHz;
s_ClockRangeLimits[i].MinKHz = NVRM_BUS_MIN_KHZ;
}
}
// Fill in limits for modules with slectable clock sources and/or dividers
// as specified by the h/w table according to the h/w device ID
// (CPU and AVP are not in relocation table - need translate id explicitly)
// TODO: need separate subclock limits? (current implementation applies
// main clock limits to all subclocks)
for (i = 0; i < pShmoo->ScaledLimitsListSize; i++)
{
NvRmModuleID id;
if (pHwLimits[i].HwDeviceId == NV_DEVID_CPU)
id = NvRmModuleID_Cpu;
else if (pHwLimits[i].HwDeviceId == NV_DEVID_AVP)
id = NvRmModuleID_Avp;
else if (pHwLimits[i].HwDeviceId == NVRM_DEVID_CLK_SRC)
id = NvRmClkLimitsExtID_ClkSrc;
else
id = NvRmPrivDevToModuleID(pHwLimits[i].HwDeviceId);
if ((id != NVRM_DEVICE_UNKNOWN) &&
(pHwLimits[i].SubClockId == 0))
{
s_ClockRangeLimits[id].MinKHz = pHwLimits[i].MinKHz;
s_ClockRangeLimits[id].MaxKHz =
pHwLimits[i].MaxKHzList[pShmoo->ShmooVmaxIndex];
s_pClockScales[id] = pHwLimits[i].MaxKHzList;
}
}
// Fill in CPU scaling data if SoC has dedicated CPU rail, and CPU clock
// characterization data is separated from other modules on common core rail
if (s_ChipFlavor.pCpuShmoo)
{
const NvRmScaledClkLimits* pCpuLimits =
s_ChipFlavor.pCpuShmoo->pScaledCpuLimits;
NV_ASSERT(pCpuLimits && (pCpuLimits->HwDeviceId == NV_DEVID_CPU));
s_ClockRangeLimits[NvRmModuleID_Cpu].MinKHz = pCpuLimits->MinKHz;
s_ClockRangeLimits[NvRmModuleID_Cpu].MaxKHz =
pCpuLimits->MaxKHzList[s_ChipFlavor.pCpuShmoo->ShmooVmaxIndex];
s_pClockScales[NvRmModuleID_Cpu] = pCpuLimits->MaxKHzList;
}
// Set AVP upper clock boundary with combined Absolute/Scaled limit;
// Sync System clock with AVP (System is not in relocation table)
s_ClockRangeLimits[NvRmModuleID_Avp].MaxKHz = AvpMaxKHz;
s_ClockRangeLimits[NvRmPrivModuleID_System].MaxKHz =
s_ClockRangeLimits[NvRmModuleID_Avp].MaxKHz;
s_ClockRangeLimits[NvRmPrivModuleID_System].MinKHz =
s_ClockRangeLimits[NvRmModuleID_Avp].MinKHz;
s_pClockScales[NvRmPrivModuleID_System] = s_pClockScales[NvRmModuleID_Avp];
// Set VDE upper clock boundary with combined Absolute/Scaled limit (on
// AP15/Ap16 VDE clock derived from the system bus, and VDE maximum limit
// must be the same as AVP/System).
VdeMaxKHz = pSKUedLimits->VdeMaxKHz;
VdeMaxKHz = NV_MIN(
VdeMaxKHz, s_ClockRangeLimits[NvRmModuleID_Vde].MaxKHz);
if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
{
NV_ASSERT(VdeMaxKHz == AvpMaxKHz);
}
s_ClockRangeLimits[NvRmModuleID_Vde].MaxKHz = VdeMaxKHz;
// Set upper clock boundaries for devices on CPU bus (CPU, Mselect,
// CMC) with combined Absolute/Scaled limits
CpuMaxKHz = pSKUedLimits->CpuMaxKHz;
CpuMaxKHz = NV_MIN(
CpuMaxKHz, s_ClockRangeLimits[NvRmModuleID_Cpu].MaxKHz);
s_ClockRangeLimits[NvRmModuleID_Cpu].MaxKHz = CpuMaxKHz;
if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
{
s_ClockRangeLimits[NvRmModuleID_CacheMemCtrl].MaxKHz = CpuMaxKHz;
s_ClockRangeLimits[NvRmPrivModuleID_Mselect].MaxKHz = CpuMaxKHz;
NV_ASSERT(s_ClockRangeLimits[NvRmClkLimitsExtID_ClkSrc].MaxKHz >=
CpuMaxKHz);
}
else if (hRmDevice->ChipId.Id == 0x20)
{
// No CMC; TODO: Mselect/CPU <= 1/4?
s_ClockRangeLimits[NvRmPrivModuleID_Mselect].MaxKHz = CpuMaxKHz >> 2;
}
float
nv_mlp_train_lex(nv_mlp_t *mlp,
const nv_matrix_t *data,
const nv_matrix_t *label,
const nv_matrix_t *t,
float ir, float hr,
int start_epoch, int end_epoch, int max_epoch)
{
int i;
int epoch = 1;
float p;
nv_matrix_t *input_y = nv_matrix_alloc(mlp->input_w->m, NV_MLP_BATCH_SIZE);
nv_matrix_t *hidden_y = nv_matrix_alloc(mlp->hidden_w->m, NV_MLP_BATCH_SIZE);
nv_matrix_t *output_y = nv_matrix_alloc(mlp->output, NV_MLP_BATCH_SIZE);
nv_matrix_t *corrupted_data = nv_matrix_alloc(mlp->input, NV_MLP_BATCH_SIZE);
nv_matrix_t *input_w_momentum = nv_matrix_alloc(mlp->input_w->n, mlp->input_w->m);
nv_matrix_t *input_bias_momentum = nv_matrix_alloc(mlp->input_bias->n,
mlp->input_bias->m);
nv_matrix_t *hidden_w_momentum = nv_matrix_alloc(mlp->hidden_w->n, mlp->hidden_w->m);
nv_matrix_t *hidden_bias_momentum = nv_matrix_alloc(mlp->hidden_bias->n,
mlp->hidden_bias->m);
int *djs = nv_alloc_type(int, NV_MLP_BATCH_SIZE);
int *rand_idx = nv_alloc_type(int, data->m);
NV_ASSERT(data->m > NV_MLP_BATCH_SIZE);
nv_matrix_zero(input_w_momentum);
nv_matrix_zero(hidden_w_momentum);
nv_matrix_zero(input_bias_momentum);
nv_matrix_zero(hidden_bias_momentum);
epoch = start_epoch + 1;
do {
long tm;
int correct = 0;
float e = 0.0f;
int count = 0;
tm = nv_clock();
nv_shuffle_index(rand_idx, 0, data->m);
for (i = 0; i < data->m / NV_MLP_BATCH_SIZE; ++i) {
int j;
#ifdef _OPENMP
#pragma omp parallel for schedule(dynamic, 1) reduction(+:correct, count, e)
#endif
for (j = 0; j < NV_MLP_BATCH_SIZE; ++j) {
int label_correct;
int dj = rand_idx[i * NV_MLP_BATCH_SIZE + j];
djs[j] = dj;
nv_mlp_corrupt(mlp, corrupted_data, j, data, dj);
nv_mlp_forward(mlp, input_y, j, hidden_y, j,
corrupted_data, j);
nv_mlp_softmax(output_y, j, hidden_y, j);
e += nv_mlp_error(output_y, j, t, dj);
label_correct = (int)NV_MAT_V(label, dj, 0);
if (nv_vector_max_n(output_y, j) == label_correct) {
++correct;
}
count += 1;
}
nv_mlp_backward(
mlp,
input_w_momentum, input_bias_momentum,
hidden_w_momentum, hidden_bias_momentum,
output_y, input_y, corrupted_data,
t, djs,
ir, hr);
}
p = (float)correct / count;
if (nv_mlp_progress_flag) {
printf("%d: E:%E, %f (%d/%d), %ldms\n",
epoch, e / count / mlp->output,
p, correct,
count,
nv_clock() - tm);
if (nv_mlp_progress_flag >= 2) {
nv_mlp_train_accuracy(mlp, data, label);
}
fflush(stdout);
}
} while (epoch++ < end_epoch);
nv_free(rand_idx);
nv_free(djs);
nv_matrix_free(&input_y);
nv_matrix_free(&hidden_y);
nv_matrix_free(&output_y);
nv_matrix_free(&corrupted_data);
nv_matrix_free(&input_w_momentum);
nv_matrix_free(&input_bias_momentum);
nv_matrix_free(&hidden_w_momentum);
nv_matrix_free(&hidden_bias_momentum);
return p;
}
long nvrm_unlocked_ioctl(struct file *file,
unsigned int cmd, unsigned long arg)
{
NvError err;
NvOsIoctlParams p;
NvU32 size;
NvU32 small_buf[8];
void *ptr = 0;
long e;
NvBool bAlloc = NV_FALSE;
struct nvrm_file_priv *priv = file->private_data;
switch( cmd ) {
case NvRmIoctls_Generic:
{
NvDispatchCtx dctx;
dctx.Rt = s_RtHandle;
dctx.Client = priv->rt_client;
dctx.PackageIdx = 0;
err = NvOsCopyIn( &p, (void *)arg, sizeof(p) );
if( err != NvSuccess )
{
printk( "NvRmIoctls_Generic: copy in failed\n" );
goto fail;
}
//printk( "NvRmIoctls_Generic: %d %d %d\n", p.InBufferSize,
// p.InOutBufferSize, p.OutBufferSize );
size = p.InBufferSize + p.InOutBufferSize + p.OutBufferSize;
if( size <= sizeof(small_buf) )
{
ptr = small_buf;
}
else
{
ptr = NvOsAlloc( size );
if( !ptr )
{
printk( "NvRmIoctls_Generic: alloc failure (%d bytes)\n",
size );
goto fail;
}
bAlloc = NV_TRUE;
}
err = NvOsCopyIn( ptr, p.pBuffer, p.InBufferSize +
p.InOutBufferSize );
if( err != NvSuccess )
{
printk( "NvRmIoctls_Generic: copy in failure\n" );
goto fail;
}
if (priv->su) {
err = NvRm_Dispatch( ptr, p.InBufferSize + p.InOutBufferSize,
((NvU8 *)ptr) + p.InBufferSize, p.InOutBufferSize +
p.OutBufferSize, &dctx );
} else {
err = NvRm_Dispatch_Others( ptr, p.InBufferSize + p.InOutBufferSize,
((NvU8 *)ptr) + p.InBufferSize, p.InOutBufferSize +
p.OutBufferSize, &dctx );
}
if( err != NvSuccess )
{
printk( "NvRmIoctls_Generic: dispatch failure\n" );
goto fail;
}
if( p.InOutBufferSize || p.OutBufferSize )
{
err = NvOsCopyOut( ((NvU8 *)((NvOsIoctlParams *)arg)->pBuffer)
+ p.InBufferSize,
((NvU8 *)ptr) + p.InBufferSize,
p.InOutBufferSize + p.OutBufferSize );
if( err != NvSuccess )
{
printk( "NvRmIoctls_Generic: copy out failure\n" );
goto fail;
}
}
break;
}
case NvRmIoctls_NvRmGraphics:
printk( "NvRmIoctls_NvRmGraphics: not supported\n" );
goto fail;
case NvRmIoctls_NvRmFbControl:
printk( "NvRmIoctls_NvRmFbControl: deprecated \n" );
break;
case NvRmIoctls_NvRmMemRead:
case NvRmIoctls_NvRmMemWrite:
case NvRmIoctls_NvRmMemReadStrided:
case NvRmIoctls_NvRmGetCarveoutInfo:
case NvRmIoctls_NvRmMemWriteStrided:
goto fail;
case NvRmIoctls_NvRmMemMapIntoCallerPtr:
// FIXME: implement?
printk( "NvRmIoctls_NvRmMemMapIntoCallerPtr: not supported\n" );
goto fail;
case NvRmIoctls_NvRmBootDone:
return tegra_start_dvfsd();
case NvRmIoctls_NvRmGetClientId:
err = NvOsCopyIn(&p, (void*)arg, sizeof(p));
if (err != NvSuccess)
{
NvOsDebugPrintf("NvRmIoctls_NvRmGetClientId: copy in failed\n");
goto fail;
}
NV_ASSERT(p.InBufferSize == 0);
NV_ASSERT(p.OutBufferSize == sizeof(NvRtClientHandle));
NV_ASSERT(p.InOutBufferSize == 0);
if (NvOsCopyOut(p.pBuffer,
&priv->rt_client,
sizeof(NvRtClientHandle)) != NvSuccess)
{
NvOsDebugPrintf("Failed to copy client id\n");
goto fail;
}
break;
case NvRmIoctls_NvRmClientAttach:
{
NvRtClientHandle Client;
err = NvOsCopyIn(&p, (void*)arg, sizeof(p));
if (err != NvSuccess)
{
NvOsDebugPrintf("NvRmIoctls_NvRmClientAttach: copy in failed\n");
goto fail;
}
NV_ASSERT(p.InBufferSize == sizeof(NvRtClientHandle));
NV_ASSERT(p.OutBufferSize == 0);
NV_ASSERT(p.InOutBufferSize == 0);
if (NvOsCopyIn((void*)&Client,
p.pBuffer,
sizeof(NvRtClientHandle)) != NvSuccess)
{
NvOsDebugPrintf("Failed to copy client id\n");
goto fail;
}
NV_ASSERT(Client || !"Bad client");
if (Client == priv->rt_client)
{
// The daemon is attaching to itself, no need to add refcount
break;
}
if (NvRtAddClientRef(s_RtHandle, Client) != NvSuccess)
{
NvOsDebugPrintf("Client ref add unsuccessful\n");
goto fail;
}
break;
}
case NvRmIoctls_NvRmClientDetach:
{
NvRtClientHandle Client;
err = NvOsCopyIn(&p, (void*)arg, sizeof(p));
if (err != NvSuccess)
{
NvOsDebugPrintf("NvRmIoctls_NvRmClientAttach: copy in failed\n");
goto fail;
}
NV_ASSERT(p.InBufferSize == sizeof(NvRtClientHandle));
NV_ASSERT(p.OutBufferSize == 0);
NV_ASSERT(p.InOutBufferSize == 0);
if (NvOsCopyIn((void*)&Client,
p.pBuffer,
sizeof(NvRtClientHandle)) != NvSuccess)
{
NvOsDebugPrintf("Failed to copy client id\n");
goto fail;
}
NV_ASSERT(Client || !"Bad client");
if (Client == priv->rt_client)
{
// The daemon is detaching from itself, no need to dec refcount
break;
}
client_detach(Client);
break;
}
// FIXME: power ioctls?
default:
printk( "unknown ioctl code\n" );
goto fail;
}
e = 0;
goto clean;
fail:
e = -EINVAL;
clean:
if( bAlloc )
{
NvOsFree( ptr );
}
return e;
}
NvError
NvDdkUsbPhyPowerDown(
NvDdkUsbPhyHandle hUsbPhy,
NvBool IsHostMode,
NvBool IsDpd)
{
NvError e = NvSuccess;
NvDdkUsbPhyIoctl_VBusStatusOutputArgs VBusStatus;
NvU32 TimeOut = USB_PHY_HW_TIMEOUT_US;
NV_ASSERT(hUsbPhy);
NvOsMutexLock(hUsbPhy->ThreadSafetyMutex);
if (!hUsbPhy->IsPhyPoweredUp)
{
NvOsMutexUnlock(hUsbPhy->ThreadSafetyMutex);
return e;
}
/* Allow saving register context for the USB host if it is a ULPI
interface or if the lowest power state is LP1 */
if (hUsbPhy->pProperty->UsbMode == NvOdmUsbModeType_Host)
{
hUsbPhy->SaveContext(hUsbPhy);
}
/* Turn on/off the vbus for host mode */
hUsbPhy->IsHostMode = IsHostMode;
if (IsHostMode)
{
UsbPrivEnableVbus(hUsbPhy, NV_FALSE);
/* Wait till Vbus is turned off */
do
{
NvOsWaitUS(1000);
TimeOut -= 1000;
e = hUsbPhy->Ioctl(hUsbPhy,
NvDdkUsbPhyIoctlType_VBusStatus,
NULL,
&VBusStatus);
} while (VBusStatus.VBusDetected && TimeOut);
}
// Power down the USB Phy
NV_CHECK_ERROR_CLEANUP(hUsbPhy->PowerDown(hUsbPhy));
// On AP20 H-CLK should not be turned off
// This is required to detect the sensor interrupts.
// However, phy can be programmed to put in the low power mode
if (!hUsbPhy->Caps.PhyRegInController)
{
// Disable the clock
NV_CHECK_ERROR_CLEANUP(
NvRmPowerModuleClockControl(hUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, hUsbPhy->Instance),
hUsbPhy->RmPowerClientId, NV_FALSE));
}
// Disable power
NV_CHECK_ERROR_CLEANUP(
NvRmPowerVoltageControl(hUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, hUsbPhy->Instance),
hUsbPhy->RmPowerClientId, NvRmVoltsOff, NvRmVoltsOff,
NULL, 0, NULL));
/* Turn off the USB busy hints */
UsbPhyDfsBusyHint(hUsbPhy, NV_FALSE, NV_WAIT_INFINITE);
if (hUsbPhy->TurnOffPowerRail)
{
NvOdmEnableUsbPhyPowerRail(NV_FALSE);
NvOdmEnableOtgCircuitry(NV_FALSE);
}
hUsbPhy->IsPhyPoweredUp = NV_FALSE;
fail:
NvOsMutexUnlock(hUsbPhy->ThreadSafetyMutex);
return e;
}
NvBool Pcf50626Setup(NvOdmPmuDeviceHandle hDevice)
{
NvOdmIoModule I2cModule = NvOdmIoModule_I2c;
NvU32 I2cInstance = 0;
NvU32 I2cAddress = 0;
NvU32 i = 0;
NvBool status = NV_FALSE;
const NvOdmPeripheralConnectivity *pConnectivity =
NvOdmPeripheralGetGuid(PMUGUID);
NV_ASSERT(hDevice);
pPrivData = (Pcf50626PrivData*) NvOdmOsAlloc(sizeof(Pcf50626PrivData));
if (pPrivData == NULL)
{
NVODMPMU_PRINTF(("Error Allocating Pcf50626PrivData. \n"));
return NV_FALSE;
}
NvOdmOsMemset(pPrivData, 0, sizeof(Pcf50626PrivData));
hDevice->pPrivate = pPrivData;
((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable = NvOdmOsAlloc(sizeof(NvU32) * PCF50626PmuSupply_Num);
if (((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable == NULL)
{
NVODMPMU_PRINTF(("Error Allocating RefCntTable. \n"));
goto fail;
}
// memset
for (i = 0; i < PCF50626PmuSupply_Num; i++)
{
((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable[i] = 0;
}
if (pConnectivity != NULL) // PMU is in database
{
for (i = 0; i < pConnectivity->NumAddress; i ++)
{
if (pConnectivity->AddressList[i].Interface == NvOdmIoModule_I2c_Pmu)
{
I2cModule = NvOdmIoModule_I2c_Pmu;
I2cInstance = pConnectivity->AddressList[i].Instance;
I2cAddress = pConnectivity->AddressList[i].Address;
break;
}
}
NV_ASSERT(I2cModule == NvOdmIoModule_I2c_Pmu);
NV_ASSERT(I2cAddress != 0);
((Pcf50626PrivData*)hDevice->pPrivate)->hOdmI2C = NvOdmI2cOpen(I2cModule, I2cInstance);
if (!((Pcf50626PrivData*)hDevice->pPrivate)->hOdmI2C)
{
NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: Error Open I2C device. \n"));
NVODMPMU_PRINTF(("[NVODM PMU]Please check PMU device I2C settings. \n"));
goto fail;
}
((Pcf50626PrivData*)hDevice->pPrivate)->DeviceAddr = I2cAddress;
((Pcf50626PrivData*)hDevice->pPrivate)->hOdmPmuSevice = NvOdmServicesPmuOpen();
if (!((Pcf50626PrivData*)hDevice->pPrivate)->hOdmPmuSevice)
{
NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: Error Open PMU Odm service. \n"));
goto fail;
}
}
else
{
// if PMU is not presented in the database, then the platform is PMU-less.
NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: The system did not doscover PMU fromthe data base. \n"));
NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: If this is not intended, please check the peripheral database for PMU settings. \n"));
goto fail;
}
if (!Pcf50626BatteryChargerSetup(hDevice))
{
NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: Pcf50626BatteryChargerSetup() failed. \n"));
goto fail;
}
//Check battery presence
if (!Pcf50626BatteryChargerCBCMainBatt(hDevice,&((Pcf50626PrivData*)hDevice->pPrivate)->battPresence))
{
NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: Pcf50626BatteryChargerCBCMainBatt() failed. \n"));
goto fail;
}
// The interrupt assumes not supported until pcf50626InterruptHandler() is called.
((Pcf50626PrivData*)hDevice->pPrivate)->pmuInterruptSupported = NV_FALSE;
// setup the interrupt any way.
if (!Pcf50626SetupInterrupt(hDevice, &((Pcf50626PrivData*)hDevice->pPrivate)->pmuStatus))
{
NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: Pcf50626SetupInterrupt() failed. \n"));
goto fail;
}
// Check battery Fullness
if (((Pcf50626PrivData*)hDevice->pPrivate)->battPresence == NV_TRUE)
{
if (!Pcf50626BatteryChargerCBCBattFul(hDevice,&status))
{
NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: Pcf50626BatteryChargerCBCBattFul() failed. \n"));
goto fail;
}
((Pcf50626PrivData*)hDevice->pPrivate)->pmuStatus.batFull = status;
}
else
{
((Pcf50626PrivData*)hDevice->pPrivate)->pmuStatus.batFull = NV_FALSE;
}
return NV_TRUE;
fail:
Pcf50626Release(hDevice);
return NV_FALSE;
}
NvError
NvRmPrivAp20GetModuleInterfaceCaps(
NvOdmIoModule Module,
NvU32 Instance,
NvU32 PinMap,
void *pCaps)
{
switch (Module)
{
case NvOdmIoModule_Sdio:
if (Instance == 1)
{
if (PinMap == NvOdmSdioPinMap_Config2 || PinMap == NvOdmSdioPinMap_Config4)
((NvRmModuleSdmmcInterfaceCaps *)pCaps)->MmcInterfaceWidth = 8;
else if (PinMap == NvOdmSdioPinMap_Config1 ||
PinMap == NvOdmSdioPinMap_Config3 || PinMap == NvOdmSdioPinMap_Config5)
((NvRmModuleSdmmcInterfaceCaps *)pCaps)->MmcInterfaceWidth = 4;
else
{
NV_ASSERT(NV_FALSE);
return NvError_NotSupported;
}
}
else if (Instance==2 && PinMap==NvOdmSdioPinMap_Config1)
((NvRmModuleSdmmcInterfaceCaps *)pCaps)->MmcInterfaceWidth = 8;
else if (Instance==3 && (PinMap==NvOdmSdioPinMap_Config1 || PinMap==NvOdmSdioPinMap_Config2))
((NvRmModuleSdmmcInterfaceCaps *)pCaps)->MmcInterfaceWidth = 8;
else
((NvRmModuleSdmmcInterfaceCaps *)pCaps)->MmcInterfaceWidth = 4;
return NvError_Success;
case NvOdmIoModule_Pwm:
if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config1))
((NvRmModulePwmInterfaceCaps *)pCaps)->PwmOutputIdSupported = 15;
else if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config2))
((NvRmModulePwmInterfaceCaps *)pCaps)->PwmOutputIdSupported = 13;
else if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config3))
((NvRmModulePwmInterfaceCaps *)pCaps)->PwmOutputIdSupported = 1;
else if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config4))
((NvRmModulePwmInterfaceCaps *)pCaps)->PwmOutputIdSupported = 12;
else if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config5))
((NvRmModulePwmInterfaceCaps *)pCaps)->PwmOutputIdSupported = 15;
else if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config6))
((NvRmModulePwmInterfaceCaps *)pCaps)->PwmOutputIdSupported = 3;
else
{
((NvRmModulePwmInterfaceCaps *)pCaps)->PwmOutputIdSupported = 0;
return NvError_NotSupported;
}
return NvError_Success;
case NvOdmIoModule_Nand:
if (Instance == 0 && (PinMap == NvOdmNandPinMap_Config1 || PinMap ==
NvOdmNandPinMap_Config3))
{
((NvRmModuleNandInterfaceCaps*)pCaps)->IsCombRbsyMode = NV_TRUE;
((NvRmModuleNandInterfaceCaps*)pCaps)->NandInterfaceWidth = 16;
}
else if (Instance == 0 && (PinMap == NvOdmNandPinMap_Config2 ||
PinMap == NvOdmNandPinMap_Config4))
{
((NvRmModuleNandInterfaceCaps*)pCaps)->IsCombRbsyMode = NV_TRUE;
((NvRmModuleNandInterfaceCaps*)pCaps)->NandInterfaceWidth = 8;
}
else
{
NV_ASSERT(NV_FALSE);
return NvError_NotSupported;
}
return NvSuccess;
case NvOdmIoModule_Uart:
if (Instance == 0)
{
if (PinMap == NvOdmUartPinMap_Config1)
((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 8;
else if (PinMap == NvOdmUartPinMap_Config2)
((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 7;
else if ((PinMap == NvOdmUartPinMap_Config3) || (PinMap == NvOdmUartPinMap_Config6))
((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 4;
else if ((PinMap == NvOdmUartPinMap_Config4) || (PinMap == NvOdmUartPinMap_Config5))
((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 2;
else if (PinMap == NvOdmUartPinMap_Config7)
((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 6;
else
((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 0;
}
else if ((Instance == 1) || (Instance == 2))
{
if (PinMap == NvOdmUartPinMap_Config1)
((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 4;
else if (PinMap == NvOdmUartPinMap_Config2)
((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 2;
else
((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 0;
}
else if ((Instance == 3) || (Instance == 4))
{
if ((PinMap == NvOdmUartPinMap_Config1) || (PinMap == NvOdmUartPinMap_Config2))
((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 4;
else
((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 0;
}
else
{
NV_ASSERT(NV_FALSE);
return NvError_NotSupported;
}
return NvSuccess;
default:
break;
}
return NvError_NotSupported;
}
NvError
NvRmPrivReadCfgVars( NvRmCfgMap *map, void *cfg )
{
NvU32 tmp;
NvU32 i;
char val[ NVRM_CFG_MAXLEN ];
NvError err;
/* the last cfg var entry is all zeroes */
for( i = 0; i < (NvU32)map[i].name; i++ )
{
err = NvOsGetConfigString( map[i].name, val, NVRM_CFG_MAXLEN );
if( err != NvSuccess )
{
/* no config var set, try the next one */
continue;
}
/* parse the config var and print it */
switch( map[i].type ) {
case NvRmCfgType_Hex:
{
char *end = val + NvOsStrlen( val );
tmp = NvUStrtoul( val, &end, 16 );
tmp = 0;
*(NvU32*)((NvU32)cfg + (NvU32)map[i].offset) = tmp;
NV_DEBUG_PRINTF(("Request: %s=0x%08x\n", map[i].name, tmp));
break;
}
case NvRmCfgType_Char:
*(char*)((NvU32)cfg + (NvU32)map[i].offset) = val[0];
NV_DEBUG_PRINTF(("Request: %s=%c\n", map[i].name, val[0]));
break;
case NvRmCfgType_Decimal:
{
char *end = val + NvOsStrlen( val );
tmp = NvUStrtoul( val, &end, 10 );
tmp = 0;
*(NvU32*)((NvU32)cfg + (NvU32)map[i].offset) = tmp;
NV_DEBUG_PRINTF(("Request: %s=%d\n", map[i].name, tmp));
break;
}
case NvRmCfgType_String:
{
NvU32 len = NvOsStrlen( val );
if( len >= NVRM_CFG_MAXLEN )
{
len = NVRM_CFG_MAXLEN - 1;
}
NvOsMemset( (char *)(NvU32)cfg + (NvU32)map[i].offset, 0,
NVRM_CFG_MAXLEN );
NvOsStrncpy( (char *)(NvU32)cfg + (NvU32)map[i].offset, val, len );
NV_DEBUG_PRINTF(("Request: %s=%s\n", map[i].name, val));
break;
}
default:
NV_ASSERT(!" Illegal RM Configuration type. ");
}
}
return NvSuccess;
}
void
NvRmPrivAp20DttPolicyUpdate(
NvRmDeviceHandle hRmDevice,
NvS32 TemperatureC,
NvRmDtt* pDtt)
{
NvRmDttAp20PolicyRange Range;
// CPU throttling limits are set at 50% of CPU frequency range (no
// throttling below this value), and at CPU frequency boundary that
// matches specified voltage throttling limit.
if ((!s_CpuThrottleMaxKHz) || (!s_CpuThrottleMinKHz))
{
NvU32 steps;
const NvRmFreqKHz* p = NvRmPrivModuleVscaleGetMaxKHzList(
hRmDevice, NvRmModuleID_Cpu, &steps);
NV_ASSERT(p && steps);
for (; steps != 0 ; steps--)
{
if (NVRM_DTT_VOLTAGE_THROTTLE_MV >= NvRmPrivModuleVscaleGetMV(
hRmDevice, NvRmModuleID_Cpu, p[steps-1]))
break;
}
NV_ASSERT(steps);
s_CpuThrottleMaxKHz = NV_MIN(
NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz, p[steps-1]);
s_CpuThrottleMinKHz =
NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz /
NVRM_DTT_RATIO_MAX;
NV_ASSERT(s_CpuThrottleMaxKHz > s_CpuThrottleMinKHz);
NV_ASSERT(s_CpuThrottleMinKHz > NVRM_DTT_CPU_DELTA_KHZ);
s_CpuThrottleKHz = s_CpuThrottleMaxKHz;
NV_ASSERT(pDtt->TcoreCaps.Tmin <
(NVRM_DTT_DEGREES_LOW - NVRM_DTT_DEGREES_HYSTERESIS));
NV_ASSERT(pDtt->TcoreCaps.Tmax > NVRM_DTT_DEGREES_HIGH);
}
// Advanced policy range state machine (one step at a time)
Range = (NvRmDttAp20PolicyRange)pDtt->TcorePolicy.PolicyRange;
switch (Range)
{
case NvRmDttAp20PolicyRange_Unknown:
Range = NvRmDttAp20PolicyRange_FreeRunning;
// fall through
case NvRmDttAp20PolicyRange_FreeRunning:
if (TemperatureC >= NVRM_DTT_DEGREES_LOW)
Range = NvRmDttAp20PolicyRange_LimitVoltage;
break;
case NvRmDttAp20PolicyRange_LimitVoltage:
if (TemperatureC <=
(NVRM_DTT_DEGREES_LOW - NVRM_DTT_DEGREES_HYSTERESIS))
Range = NvRmDttAp20PolicyRange_FreeRunning;
else if (TemperatureC >= NVRM_DTT_DEGREES_HIGH)
Range = NvRmDttAp20PolicyRange_ThrottleDown;
break;
case NvRmDttAp20PolicyRange_ThrottleDown:
if (TemperatureC <=
(NVRM_DTT_DEGREES_HIGH - NVRM_DTT_DEGREES_HYSTERESIS))
Range = NvRmDttAp20PolicyRange_LimitVoltage;
break;
default:
break;
}
/*
* Fill in new policy. Temperature limits are set around current
* temperature for the next out-of-limit interrupt (possible exception
* - temperature "jump" over two ranges would result in two interrupts
* in a row before limits cover the temperature). Polling time is set
* always in ThrottleDown range, and only for poll mode in other ranges.
*/
pDtt->CoreTemperatureC = TemperatureC;
switch (Range)
{
case NvRmDttAp20PolicyRange_FreeRunning:
pDtt->TcorePolicy.LowLimit = pDtt->TcoreLowLimitCaps.MinValue;
pDtt->TcorePolicy.HighLimit = NVRM_DTT_DEGREES_LOW;
pDtt->TcorePolicy.UpdateIntervalUs = pDtt->UseIntr ?
NV_WAIT_INFINITE : (NVRM_DTT_POLL_MS_SLOW * 1000);
break;
case NvRmDttAp20PolicyRange_LimitVoltage:
pDtt->TcorePolicy.LowLimit =
NVRM_DTT_DEGREES_LOW - NVRM_DTT_DEGREES_HYSTERESIS;
pDtt->TcorePolicy.HighLimit = NVRM_DTT_DEGREES_HIGH;
pDtt->TcorePolicy.UpdateIntervalUs = pDtt->UseIntr ?
NV_WAIT_INFINITE : (NVRM_DTT_POLL_MS_FAST * 1000);
break;
case NvRmDttAp20PolicyRange_ThrottleDown:
pDtt->TcorePolicy.LowLimit =
NVRM_DTT_DEGREES_HIGH - NVRM_DTT_DEGREES_HYSTERESIS;
pDtt->TcorePolicy.HighLimit = pDtt->TcoreHighLimitCaps.MaxValue;
pDtt->TcorePolicy.UpdateIntervalUs = NVRM_DTT_POLL_MS_CRITICAL * 1000;
break;
default:
NV_ASSERT(!"Invalid DTT policy range");
NvOsDebugPrintf("DTT: Invalid Range = %d\n", Range);
pDtt->TcorePolicy.HighLimit = ODM_TMON_PARAMETER_UNSPECIFIED;
pDtt->TcorePolicy.LowLimit = ODM_TMON_PARAMETER_UNSPECIFIED;
pDtt->TcorePolicy.PolicyRange = NvRmDttAp20PolicyRange_Unknown;
return;
}
pDtt->TcorePolicy.PolicyRange = (NvU32)Range;
}
NvRmPmRequest
NvRmPrivAp20GetPmRequest(
NvRmDeviceHandle hRmDevice,
const NvRmDfsSampler* pCpuSampler,
NvRmFreqKHz* pCpuKHz)
{
// Assume initial slave CPU1 On request
static NvRmPmRequest s_LastPmRequest = (NvRmPmRequest_CpuOnFlag | 0x1);
NvRmFreqKHz s_Cpu1OnMinKHz = 0;
NvRmFreqKHz s_Cpu1OffMaxKHz= 0;
static NvU32 s_Cpu1OnPendingCnt = 0, s_Cpu1OffPendingCnt = 0;
NvU32 t;
NvRmPmRequest PmRequest = NvRmPmRequest_None;
NvBool Cpu1Off =
(0 != NV_DRF_VAL(CLK_RST_CONTROLLER, RST_CPU_CMPLX_SET, SET_CPURESET1,
NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0)));
NvRmFreqKHz CpuLoadGaugeKHz = *pCpuKHz;
// Slave CPU1 power management policy thresholds:
// - use fixed values if they are defined explicitly, otherwise
// - set CPU1 OffMax threshold at 2/3 of cpu frequency range,
// and half of that frequency as CPU1 OnMin threshold
if ((s_Cpu1OffMaxKHz == 0) && (s_Cpu1OnMinKHz == 0))
{
NvRmFreqKHz MaxKHz =
NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
s_Cpu1OnMinKHz = NVRM_CPU1_ON_MIN_KHZ;
s_Cpu1OffMaxKHz = NVRM_CPU1_OFF_MAX_KHZ;
NV_ASSERT(s_Cpu1OnMinKHz < s_Cpu1OffMaxKHz);
}
// Timestamp
if (s_pTimerUs == NULL)
s_pTimerUs = NvRmPrivAp15GetTimerUsVirtAddr(hRmDevice);
t = NV_READ32(s_pTimerUs);
/*
* Request OS kernel to turn CPU1 Off if all of the following is true:
* (a) CPU frequency is below OnMin threshold,
* (b) CPU1 is actually On
*
* Request OS kernel to turn CPU1 On if all of the following is true:
* (a) CPU frequency is above OffMax threshold
* (b) CPU1 is actually Off
*/
if (CpuLoadGaugeKHz < s_Cpu1OnMinKHz)
{
s_Cpu1OnPendingCnt = 0;
if ((s_Cpu1OffPendingCnt & 0x1) == 0)
{
s_Cpu1OffPendingCnt = t | 0x1; // Use LSb as a delay start flag
return PmRequest;
}
if ((t - s_Cpu1OffPendingCnt) < (NVRM_CPU1_OFF_PENDING_MS * 1000))
return PmRequest;
if (!Cpu1Off)
{
s_LastPmRequest = PmRequest = (NvRmPmRequest_CpuOffFlag | 0x1);
s_Cpu1OffPendingCnt = 0; // re-start delay after request
}
#if NVRM_TEST_PMREQUEST_UP_MODE
NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0,
CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_FIELD);
#endif
}
else if (CpuLoadGaugeKHz > s_Cpu1OffMaxKHz)
{
s_Cpu1OffPendingCnt = 0;
if ((s_Cpu1OnPendingCnt & 0x1) == 0)
{
s_Cpu1OnPendingCnt = t | 0x1; // Use LSb as a delay start flag
return PmRequest;
}
if ((t - s_Cpu1OnPendingCnt) < (NVRM_CPU1_ON_PENDING_MS * 1000))
return PmRequest;
if (Cpu1Off)
{
s_LastPmRequest = PmRequest = (NvRmPmRequest_CpuOnFlag | 0x1);
*pCpuKHz = NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
s_Cpu1OnPendingCnt = 0; // re-start delay after request
}
#if NVRM_TEST_PMREQUEST_UP_MODE
NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0,
CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_FIELD);
#endif
}
else
{ // Re-start both delays inside hysteresis loop
s_Cpu1OnPendingCnt = 0;
s_Cpu1OffPendingCnt = 0;
}
return PmRequest;
}
static NvError
NvRmPrivTvDcControl( NvRmDeviceHandle hDevice, NvBool enable, NvU32 inst,
void *Config, NvU32 ConfigLength )
{
NvRmAnalogTvDacConfig *cfg;
NvU32 ctrl, source;
NvU32 src_id;
NvU32 src_inst;
NV_ASSERT( ConfigLength == 0 ||
ConfigLength == sizeof(NvRmAnalogTvDacConfig) );
if( enable )
{
cfg = (NvRmAnalogTvDacConfig *)Config;
NV_ASSERT( cfg );
src_id = NVRM_MODULE_ID_MODULE( cfg->Source );
src_inst = NVRM_MODULE_ID_INSTANCE( cfg->Source );
ctrl = NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_IDDQ, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_POWERDOWN, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_DETECT_EN, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPR, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPG, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPB, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPR_EN, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPG_EN, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPB_EN, ENABLE );
if( src_id == NvRmModuleID_Tvo )
{
source = NV_DRF_DEF( APB_MISC_ASYNC, TVDACDINCONFIG,
DAC_SOURCE, TVO );
}
else
{
NV_ASSERT( src_id == NvRmModuleID_Display );
if( src_inst == 0 )
{
source = NV_DRF_DEF( APB_MISC_ASYNC, TVDACDINCONFIG,
DAC_SOURCE, DISPLAY );
}
else
{
source = NV_DRF_DEF( APB_MISC_ASYNC, TVDACDINCONFIG,
DAC_SOURCE, DISPLAYB );
}
}
source = NV_FLD_SET_DRF_NUM( APB_MISC_ASYNC, TVDACDINCONFIG, DAC_AMPIN,
cfg->DacAmplitude, source );
}
else
{
ctrl = NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_IDDQ, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_POWERDOWN, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_DETECT_EN, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPR, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPG, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPB, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPR_EN, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPG_EN, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPB_EN, DISABLE );
source = NV_DRF_DEF( APB_MISC_ASYNC, TVDACDINCONFIG,
DAC_SOURCE, TVDAC_OFF );
}
NV_REGW( hDevice, NvRmModuleID_Misc, 0, APB_MISC_ASYNC_TVDACCNTL_0,
ctrl );
NV_REGW( hDevice, NvRmModuleID_Misc, 0,
APB_MISC_ASYNC_TVDACDINCONFIG_0, source );
return NvSuccess;
}
void NvRmPrivCoreVoltageInit(NvRmDeviceHandle hRmDevice)
{
NvU32 CoreRailAddress, RtcRailAddress, CpuRailAddress;
const NvOdmPeripheralConnectivity* pPmuRail;
NvRmMilliVolts CurrentCoreMv = 0;
NvRmMilliVolts CurrentRtcMv = 0;
NvRmMilliVolts NominalCoreMv = NvRmPrivGetNominalMV(hRmDevice);
NV_ASSERT(hRmDevice);
if (NvRmPrivGetExecPlatform(hRmDevice) != ExecPlatform_Soc)
{
return;
}
pPmuRail = NvOdmPeripheralGetGuid(NV_VDD_CORE_ODM_ID);
NV_ASSERT(pPmuRail);
NV_ASSERT(pPmuRail->NumAddress);
CoreRailAddress = pPmuRail->AddressList[0].Address;
pPmuRail = NvOdmPeripheralGetGuid(NV_VDD_RTC_ODM_ID);
NV_ASSERT(pPmuRail);
NV_ASSERT(pPmuRail->NumAddress);
RtcRailAddress = pPmuRail->AddressList[0].Address;
// This function is called during PMU initialization when current (= boot)
// core voltage is expected to be within one safe step from nominal, and
// RTC voltage must be within one safe step from the core. Set nominal
// voltage (bump PMU ref count), if the above conditions are true.
NvRmPmuGetVoltage(hRmDevice, CoreRailAddress, &CurrentCoreMv);
NvRmPmuGetVoltage(hRmDevice, RtcRailAddress, &CurrentRtcMv);
if((CurrentCoreMv > (NominalCoreMv + NVRM_SAFE_VOLTAGE_STEP_MV)) ||
((CurrentCoreMv + NVRM_SAFE_VOLTAGE_STEP_MV) < NominalCoreMv))
{
NV_ASSERT(!"Unexpected initial core voltage");
return;
}
if((CurrentRtcMv > (CurrentCoreMv + NVRM_SAFE_VOLTAGE_STEP_MV)) ||
((CurrentRtcMv + NVRM_SAFE_VOLTAGE_STEP_MV) < CurrentCoreMv))
{
NV_ASSERT(!"Unexpected initial RTC voltage");
return;
}
// If core voltage is going up, update it before CPU
if (CurrentCoreMv <= NominalCoreMv)
{
NvRmPmuSetVoltage(hRmDevice, RtcRailAddress, NominalCoreMv, NULL);
NvRmPmuSetVoltage(hRmDevice, CoreRailAddress, NominalCoreMv, NULL);
}
// If the platform has dedicated CPU voltage rail, make sure it is set to
// nominal level as well (bump PMU ref count along the way).
if (NvRmPrivIsCpuRailDedicated(hRmDevice))
{
NvRmPmuVddRailCapabilities cap;
NvRmMilliVolts NominalCpuMv = NvRmPrivModuleVscaleGetMV(
hRmDevice, NvRmModuleID_Cpu,
NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz);
pPmuRail = NvOdmPeripheralGetGuid(NV_VDD_CPU_ODM_ID);
NV_ASSERT(pPmuRail);
NV_ASSERT(pPmuRail->NumAddress);
CpuRailAddress = pPmuRail->AddressList[0].Address;
// Clip nominal CPU voltage to minimal PMU capabilities, and set it.
// (note: PMU with CPU voltage range above nominal is temporary
// accepted exception; for other limit violations: PMU maximum level
// for CPU is not high enough, or PMU core range does not include
// nominal core voltage, assert is fired inside NvRmPmuSetVoltage())
NvRmPmuGetCapabilities(hRmDevice, CpuRailAddress, &cap);
NominalCpuMv = NV_MAX(NominalCpuMv, cap.MinMilliVolts);
NvRmPmuSetVoltage(hRmDevice, CpuRailAddress, NominalCpuMv, NULL);
if (CurrentCoreMv > NominalCoreMv)
NvOsWaitUS(NVRM_CPU_TO_CORE_DOWN_US); // delay if core to go down
}
// If core voltage is going down, update it after CPU voltage
if (CurrentCoreMv > NominalCoreMv)
{
NvRmPmuSetVoltage(hRmDevice, RtcRailAddress, NominalCoreMv, NULL);
NvRmPmuSetVoltage(hRmDevice, CoreRailAddress, NominalCoreMv, NULL);
}
// Always On System I/O, DDR IO and RX DDR (if exist) - set nominal,
// bump ref count
NvRmPrivPmuRailControl(hRmDevice, NV_VDD_SYS_ODM_ID, NV_TRUE);
NvRmPrivPmuRailControl(hRmDevice, NV_VDD_DDR_ODM_ID, NV_TRUE);
if (NvOdmPeripheralGetGuid(NV_VDD_DDR_RX_ODM_ID))
NvRmPrivPmuRailControl(hRmDevice, NV_VDD_DDR_RX_ODM_ID, NV_TRUE);
}
static void
PowerGroupPowerControl(
NvRmDeviceHandle hRmDeviceHandle,
NvU32 PowerGroup,
NvBool Enable)
{
NvU32 reg, Id, Mask, Status;
// Do nothing if not SoC platform
NV_ASSERT(hRmDeviceHandle);
if (NvRmPrivGetExecPlatform(hRmDeviceHandle) != ExecPlatform_Soc)
return;
// Do nothing if power group is already in requested state
NV_ASSERT(s_PowerGroupIds[PowerGroup] != NV_POWERGROUP_INVALID);
Id = s_PowerGroupIds[PowerGroup];
Mask = (0x1 << Id);
Status = Mask & NV_REGR(hRmDeviceHandle, NvRmModuleID_Pmif, 0,
APBDEV_PMC_PWRGATE_STATUS_0);
if (Enable == (Status != 0x0))
return;
/*
* Gating procedure:
* - assert resets to all modules in power group
* - toggle power gate
*
* Ungating procedure
* - assert resets to all modules in power group (redundunt)
* - toggle power gate
* - enable clocks to all modules in power group
* - reset propagation delay
* - remove clamping
* - disable clocks to all modules in power group
* - de-assert reset to all modules in power group
*
* Special note on toggle timers( shared with OAL which does CPU power
* gating): per convention with OAL default settings are never changed.
*/
PowerGroupResetControl(hRmDeviceHandle, PowerGroup, NV_TRUE);
reg = NV_DRF_DEF(APBDEV_PMC, PWRGATE_TOGGLE, START, ENABLE) | Id;
NV_REGW(hRmDeviceHandle, NvRmModuleID_Pmif, 0,
APBDEV_PMC_PWRGATE_TOGGLE_0, reg);
for (;;)
{
reg = NV_REGR(hRmDeviceHandle, NvRmModuleID_Pmif, 0,
APBDEV_PMC_PWRGATE_STATUS_0);
if (Status != (reg & Mask))
break;
}
if (Enable)
{
PowerGroupClockControl(hRmDeviceHandle, PowerGroup, NV_TRUE);
NvOsWaitUS(NVRM_RESET_DELAY);
// PCIE and VDE clamping masks are swapped relatively to
// partition Ids (bug 602975)
if (PowerGroup == NV_POWERGROUP_PCIE)
Mask = 0x1 << s_PowerGroupIds[NV_POWERGROUP_VDE];
else if (PowerGroup == NV_POWERGROUP_VDE)
Mask = 0x1 << s_PowerGroupIds[NV_POWERGROUP_PCIE];
NV_REGW(hRmDeviceHandle, NvRmModuleID_Pmif, 0,
APBDEV_PMC_REMOVE_CLAMPING_CMD_0, Mask);
for (;;)
{
reg = NV_REGR(hRmDeviceHandle, NvRmModuleID_Pmif, 0,
APBDEV_PMC_REMOVE_CLAMPING_CMD_0);
if (reg == 0)
break;
}
PowerGroupClockControl(hRmDeviceHandle, PowerGroup, NV_FALSE);
PowerGroupResetControl(hRmDeviceHandle, PowerGroup, NV_FALSE);
}
}
NvError
NvDdkUsbPhyOpen(
NvRmDeviceHandle hRm,
NvU32 Instance,
NvDdkUsbPhyHandle *hUsbPhy)
{
NvError e;
NvU32 MaxInstances = 0;
NvDdkUsbPhy *pUsbPhy = NULL;
NvOsMutexHandle UsbPhyMutex = NULL;
NvRmModuleInfo info[MAX_USB_INSTANCES];
NvU32 j;
NV_ASSERT(hRm);
NV_ASSERT(hUsbPhy);
NV_ASSERT(Instance < MAX_USB_INSTANCES);
NV_CHECK_ERROR(NvRmModuleGetModuleInfo( hRm, NvRmModuleID_Usb2Otg, &MaxInstances, NULL ));
if (MaxInstances > MAX_USB_INSTANCES)
{
// Ceil "instances" to MAX_USB_INSTANCES
MaxInstances = MAX_USB_INSTANCES;
}
NV_CHECK_ERROR(NvRmModuleGetModuleInfo( hRm, NvRmModuleID_Usb2Otg, &MaxInstances, info ));
for (j = 0; j < MaxInstances; j++)
{
// Check whether the requested instance is present
if(info[j].Instance == Instance)
break;
}
// No match found return
if (j == MaxInstances)
{
return NvError_ModuleNotPresent;
}
if (!s_UsbPhyMutex)
{
e = NvOsMutexCreate(&UsbPhyMutex);
if (e!=NvSuccess)
return e;
if (NvOsAtomicCompareExchange32(
(NvS32*)&s_UsbPhyMutex, 0, (NvS32)UsbPhyMutex)!=0)
{
NvOsMutexDestroy(UsbPhyMutex);
}
}
NvOsMutexLock(s_UsbPhyMutex);
if (!s_pUsbPhy)
{
s_pUsbPhy = NvOsAlloc(MaxInstances * sizeof(NvDdkUsbPhy));
if (s_pUsbPhy)
NvOsMemset(s_pUsbPhy, 0, MaxInstances * sizeof(NvDdkUsbPhy));
}
NvOsMutexUnlock(s_UsbPhyMutex);
if (!s_pUsbPhy)
return NvError_InsufficientMemory;
NvOsMutexLock(s_UsbPhyMutex);
if (!s_pUtmiPadConfig)
{
s_pUtmiPadConfig = NvOsAlloc(sizeof(NvDdkUsbPhyUtmiPadConfig));
if (s_pUtmiPadConfig)
{
NvRmPhysAddr PhyAddr;
NvOsMemset(s_pUtmiPadConfig, 0, sizeof(NvDdkUsbPhyUtmiPadConfig));
NvRmModuleGetBaseAddress(
hRm,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, 0),
&PhyAddr, &s_pUtmiPadConfig->BankSize);
NV_CHECK_ERROR_CLEANUP(
NvRmPhysicalMemMap(
PhyAddr, s_pUtmiPadConfig->BankSize, NVOS_MEM_READ_WRITE,
NvOsMemAttribute_Uncached, (void **)&s_pUtmiPadConfig->pVirAdr));
}
}
NvOsMutexUnlock(s_UsbPhyMutex);
if (!s_pUtmiPadConfig)
return NvError_InsufficientMemory;
pUsbPhy = &s_pUsbPhy[Instance];
NvOsMutexLock(s_UsbPhyMutex);
if (!pUsbPhy->RefCount)
{
NvRmPhysAddr PhysAddr;
NvOsMutexHandle ThreadSafetyMutex = NULL;
NvOsMemset(pUsbPhy, 0, sizeof(NvDdkUsbPhy));
pUsbPhy->Instance = Instance;
pUsbPhy->hRmDevice = hRm;
pUsbPhy->RefCount = 1;
pUsbPhy->IsPhyPoweredUp = NV_FALSE;
pUsbPhy->pUtmiPadConfig = s_pUtmiPadConfig;
pUsbPhy->pProperty = NvOdmQueryGetUsbProperty(
NvOdmIoModule_Usb, pUsbPhy->Instance);
pUsbPhy->TurnOffPowerRail = UsbPhyTurnOffPowerRail(MaxInstances);
NV_CHECK_ERROR_CLEANUP(NvOsMutexCreate(&ThreadSafetyMutex));
if (NvOsAtomicCompareExchange32(
(NvS32*)&pUsbPhy->ThreadSafetyMutex, 0,
(NvS32)ThreadSafetyMutex)!=0)
{
NvOsMutexDestroy(ThreadSafetyMutex);
}
NvRmModuleGetBaseAddress(
pUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, pUsbPhy->Instance),
&PhysAddr, &pUsbPhy->UsbBankSize);
NV_CHECK_ERROR_CLEANUP(
NvRmPhysicalMemMap(
PhysAddr, pUsbPhy->UsbBankSize, NVOS_MEM_READ_WRITE,
NvOsMemAttribute_Uncached, (void **)&pUsbPhy->UsbVirAdr));
NvRmModuleGetBaseAddress(
pUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Misc, 0),
&PhysAddr, &pUsbPhy->MiscBankSize);
NV_CHECK_ERROR_CLEANUP(
NvRmPhysicalMemMap(
PhysAddr, pUsbPhy->MiscBankSize, NVOS_MEM_READ_WRITE,
NvOsMemAttribute_Uncached, (void **)&pUsbPhy->MiscVirAdr));
if ( ( pUsbPhy->pProperty->UsbInterfaceType ==
NvOdmUsbInterfaceType_UlpiNullPhy) ||
( pUsbPhy->pProperty->UsbInterfaceType ==
NvOdmUsbInterfaceType_UlpiExternalPhy))
{
if (NvRmSetModuleTristate(
pUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, pUsbPhy->Instance),
NV_FALSE) != NvSuccess )
return NvError_NotSupported;
}
// Register with Power Manager
NV_CHECK_ERROR_CLEANUP(
NvOsSemaphoreCreate(&pUsbPhy->hPwrEventSem, 0));
pUsbPhy->RmPowerClientId = NVRM_POWER_CLIENT_TAG('U','S','B','p');
NV_CHECK_ERROR_CLEANUP(
NvRmPowerRegister(pUsbPhy->hRmDevice,
pUsbPhy->hPwrEventSem, &pUsbPhy->RmPowerClientId));
// Open the H/W interface
UsbPhyOpenHwInterface(pUsbPhy);
// Initialize the USB Phy
NV_CHECK_ERROR_CLEANUP(UsbPhyInitialize(pUsbPhy));
}
else
{
pUsbPhy->RefCount++;
}
*hUsbPhy = pUsbPhy;
NvOsMutexUnlock(s_UsbPhyMutex);
return NvSuccess;
fail:
NvDdkUsbPhyClose(pUsbPhy);
NvOsMutexUnlock(s_UsbPhyMutex);
return e;
}
/* Gets the actual scan code for a key press */
NvBool NvOdmCirGetKeyData(NvU8 showlog, NvU32 *pKeyScanCode, NvU8 *pRePeat, NvU32 Timeout)
{
NvError NvStatus = NvError_Success;
NvU32 OutCode, i;
NvU8 RepeatKey;
if (!pKeyScanCode || !pRePeat || s_CirDeinit)
{
return NV_FALSE;
}
if (Timeout != 0)
{
/* Use the timeout value */
if (!NvOdmOsSemaphoreWaitTimeout(s_hCirKeyScanRecvSema, Timeout))
return NV_FALSE; // timed out
}
else
{
/* wait till we receive a scan code from the EC */
NvOdmOsSemaphoreWait(s_hCirKeyScanRecvSema);
}
//NvOsDebugPrintf("$$$$$$$ In kernel cir nvodm_cir.c !! get key data \n");
// stop scanning
if (s_CirDeinit)
return NV_FALSE;
if (s_hEcEventRegistration)
{
NvStatus = NvEcGetEvent(s_hEcEventRegistration, &CirEvent, sizeof(NvEcEvent));
if (NvStatus != NvError_Success)
{
NV_ASSERT(!"Could not receive scan code");
return NV_FALSE;
}
if (CirEvent.NumPayloadBytes == 0)
{
NV_ASSERT(!"Received Cir event with no scan codes");
return NV_FALSE;
}
if(showlog){
for (i = 0; i < CirEvent.NumPayloadBytes; i++){
printk(KERN_INFO "EC Payload[%d]=0x%x\n",i,CirEvent.Payload[i]);
}
}
RepeatKey = 0x0; /*default is new key input*/
if(CirEvent.Payload[1] == NV_ODM_CIR_SCAN_CODE_REPET){
RepeatKey = NV_ODM_CIR_SCAN_CODE_REPET;
}
OutCode = CirEvent.Payload[3]; /*Ir Command */
if(showlog)
printk(KERN_INFO "nvec_cir OUT code: 0x%x,RepeatKey =%x\n", OutCode,RepeatKey );
*pRePeat = RepeatKey ;
*pKeyScanCode = OutCode;
return NV_TRUE;
}
return NV_FALSE;
}
NvError
NvDdkUsbPhyPowerUp(
NvDdkUsbPhyHandle hUsbPhy,
NvBool IsHostMode,
NvBool IsDpd)
{
NvError e = NvSuccess;
NV_ASSERT(hUsbPhy);
NvOsMutexLock(hUsbPhy->ThreadSafetyMutex);
if (hUsbPhy->IsPhyPoweredUp)
{
NvOsMutexUnlock(hUsbPhy->ThreadSafetyMutex);
return e;
}
if (hUsbPhy->TurnOffPowerRail)
{
NvOdmEnableUsbPhyPowerRail(NV_TRUE);
}
// Enable power for USB module
NV_CHECK_ERROR_CLEANUP(
NvRmPowerVoltageControl(hUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, hUsbPhy->Instance),
hUsbPhy->RmPowerClientId, NvRmVoltsUnspecified,
NvRmVoltsUnspecified, NULL, 0, NULL));
// On Ap20 We will not turn off the H-Clk so not required to turn on
if (!hUsbPhy->Caps.PhyRegInController)
{
NV_CHECK_ERROR_CLEANUP(
NvRmPowerModuleClockControl(hUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, hUsbPhy->Instance),
hUsbPhy->RmPowerClientId, NV_TRUE));
}
// Power up the Phy
NV_CHECK_ERROR_CLEANUP(hUsbPhy->PowerUp(hUsbPhy));
/* Allow restoring register context for the USB host if it is a ULPI
interface or if the lowest power state is LP1 */
if (hUsbPhy->pProperty->UsbMode == NvOdmUsbModeType_Host)
{
hUsbPhy->RestoreContext(hUsbPhy);
}
hUsbPhy->IsHostMode = IsHostMode;
if (IsHostMode)
{
UsbPrivEnableVbus(hUsbPhy, NV_TRUE);
}
else
{
/* Turn on the USB busy hints */
UsbPhyDfsBusyHint(hUsbPhy, NV_TRUE, NV_WAIT_INFINITE);
}
hUsbPhy->IsPhyPoweredUp = NV_TRUE;
fail:
NvOsMutexUnlock(hUsbPhy->ThreadSafetyMutex);
return e;
}
void
kmeans_feature(nv_matrix_t *fv, int fv_j,
const nv_matrix_t *src,
const nv_matrix_t *zca_m,
const nv_matrix_t *zca_u,
const nv_matrix_t *centroids)
{
nv_matrix_t *patches;
nv_matrix_t *conv;
int y, i;
NV_ASSERT(fv->n == DATA_N);
patches = nv_patch_matrix_alloc(src, PATCH_SIZE);
nv_patch_extract(patches, src, PATCH_SIZE);
nv_standardize_local_all(patches, 10.0f);
nv_zca_whitening_all(patches, zca_m, 0, zca_u);
conv = nv_matrix_alloc(centroids->m, GRID);
nv_matrix_zero(conv);
for (y = 0; y < patches->rows; ++y) {
int x;
for (x = 0; x < patches->cols; ++x) {
nv_matrix_t *z = nv_matrix_alloc(centroids->m, 1);
nv_matrix_t *d = nv_matrix_alloc(patches->n, 1);
int conv_index;
int r = (int)sqrtf(GRID);
int x_idx = (x / (patches->cols / r));
int y_idx = (y / (patches->rows / r));
if (x_idx >= r) {
x_idx = r -1;
}
if (y_idx >= r) {
y_idx = r -1;
}
conv_index = y_idx * r + x_idx;
if (conv_index >= GRID) {
conv_index = GRID - 1;
}
#if TRIANGLE_DISTANCE
{
float mean;
float min_z = FLT_MAX;
int k;
for (k = 0; k < centroids->m; ++k) {
NV_MAT_V(z, 0, k) = nv_euclidean(centroids, k, patches, NV_MAT_M(patches, y, x));
if (NV_MAT_V(z, 0, k) < min_z) {
min_z = NV_MAT_V(z, 0, k);
}
}
mean = nv_vector_mean(z, 0);
#if TRIANGLE_DISTANCE_HALF
mean = mean - (mean - min_z) / 4.0f;
#endif
for (k = 0; k < centroids->m; ++k) {
float v = mean - NV_MAT_V(z, 0, k);
if (0.0f < v) {
#if TRIANGLE_DISTANCE_MAX
if (NV_MAT_V(conv, conv_index, k) < v) {
NV_MAT_V(conv, conv_index, k) = v;
}
#else
NV_MAT_V(conv, conv_index, k) += v;
#endif
}
}
}
#else
{
int nn = nv_nn(centroids, patches, NV_MAT_M(patches, y, x));
NV_MAT_V(conv, conv_index, nn) += 1.0f;
}
#endif
nv_matrix_free(&z);
nv_matrix_free(&d);
}
}
for (i = 0; i < GRID; ++i) {
memmove(&NV_MAT_V(fv, fv_j, i * conv->n),
&NV_MAT_V(conv, i, 0), conv->n * sizeof(float));
}
nv_matrix_free(&patches);
nv_matrix_free(&conv);
}
void NvDdkUsbPhyMemoryPrefetch(NvDdkUsbPhyHandle hUsbPhy, NvBool Enable)
{
NV_ASSERT(hUsbPhy);
hUsbPhy->MemoryPrefetch(hUsbPhy, Enable);
}
struct NV_DrmInfoStatus_st *
DrmKernel_NvDrmPlugin_onProcessDrmInfo(int uniqueId,
const struct NV_DrmInfo_st *drmInfo) {
ALOGV("DrmKernel_NvDrmPlugin_onProcessDrmInfo - Entry");
ALOGV("uniqueId = %d", uniqueId);
struct NV_DrmInfoStatus_st *drmInfoStatus =
(struct NV_DrmInfoStatus_st *) NULL;
if (NULL != drmInfo) {
switch (drmInfo->infoType) {
case NV_DrmInfoRequest_TYPE_REGISTRATION_INFO: {
ALOGV(
"DrmKernel_NvDrmPlugin_onProcessDrmInfo - TYPE_REGISTRATION_INFO");
struct NV_DrmBuffer_st *emptyBuffer =
(struct NV_DrmBuffer_st *) malloc(
sizeof(struct NV_DrmBuffer_st));
NV_ASSERT("Buffer allocation error", emptyBuffer);
bzero(emptyBuffer, sizeof(struct NV_DrmBuffer_st));
drmInfoStatus = (struct NV_DrmInfoStatus_st *) malloc(
sizeof(struct NV_DrmInfoStatus_st));
NV_ASSERT("DrmInfoStatus allocation error", drmInfoStatus);
bzero(drmInfoStatus, sizeof(struct NV_DrmInfoStatus_st));
SecureRecord record;
record._key = "PERSO";
record._contentKey = USTR("");
record._contentKeySize = 0;
record._tag = USTR(
DrmInfo_AttributeGet(drmInfo, "PERSO", &record._tagSize));
drmInfoStatus->statusCode =
insertRecord(&mDatabaseConnection, &record) ?
NV_DrmInfoStatus_STATUS_OK :
NV_DrmInfoStatus_STATUS_ERROR;
drmInfoStatus->infoType = NV_DrmInfoRequest_TYPE_REGISTRATION_INFO;
drmInfoStatus->drmBuffer = emptyBuffer;
if (drmInfo->mimeType != NULL)
drmInfoStatus->mimeType = strdup(drmInfo->mimeType);
}
break;
case NV_DrmInfoRequest_TYPE_UNREGISTRATION_INFO: {
ALOGV(
"DrmKernel_NvDrmPlugin_onProcessDrmInfo - TYPE_UNREGISTRATION_INFO");
struct NV_DrmBuffer_st *emptyBuffer =
(struct NV_DrmBuffer_st *) malloc(
sizeof(struct NV_DrmBuffer_st));
NV_ASSERT("Buffer allocation error", emptyBuffer);
bzero(emptyBuffer, sizeof(struct NV_DrmBuffer_st));
drmInfoStatus = (struct NV_DrmInfoStatus_st *) malloc(
sizeof(struct NV_DrmInfoStatus_st));
NV_ASSERT("DrmInfoStatus allocation error", drmInfoStatus);
bzero(drmInfoStatus, sizeof(struct NV_DrmInfoStatus_st));
drmInfoStatus->statusCode = NV_DrmInfoStatus_STATUS_OK;
drmInfoStatus->infoType =
NV_DrmInfoRequest_TYPE_UNREGISTRATION_INFO;
drmInfoStatus->drmBuffer = emptyBuffer;
if (drmInfo->mimeType != NULL)
drmInfoStatus->mimeType = strdup(drmInfo->mimeType);
}
break;
case NV_DrmInfoRequest_TYPE_RIGHTS_ACQUISITION_INFO: {
ALOGV(
"DrmKernel_NvDrmPlugin_onProcessDrmInfo - TYPE_RIGHTS_ACQUISITION_INFO");
struct NV_DrmBuffer_st *buffer = (struct NV_DrmBuffer_st *) malloc(
sizeof(struct NV_DrmBuffer_st));
NV_ASSERT("Buffer allocation error", buffer);
bzero(buffer, sizeof(struct NV_DrmBuffer_st));
buffer->length = strlen("dummy_license_string");
buffer->data = (char *) malloc(buffer->length);
NV_ASSERT("Buffer data allocation error", buffer->data);
memcpy(buffer->data, "dummy_license_string", buffer->length);
drmInfoStatus = (struct NV_DrmInfoStatus_st *) malloc(
sizeof(struct NV_DrmInfoStatus_st));
NV_ASSERT("DrmInfoStatus allocation error", drmInfoStatus);
bzero(drmInfoStatus, sizeof(struct NV_DrmInfoStatus_st));
drmInfoStatus->statusCode = NV_DrmInfoStatus_STATUS_OK;
drmInfoStatus->infoType =
NV_DrmInfoRequest_TYPE_RIGHTS_ACQUISITION_INFO;
drmInfoStatus->drmBuffer = buffer;
if (drmInfo->mimeType != NULL)
drmInfoStatus->mimeType = strdup(drmInfo->mimeType);
}
break;
case NV_DrmInfoRequest_TYPE_RIGHTS_ACQUISITION_PROGRESS_INFO: {
ALOGV(
"DrmKernel_NvDrmPlugin_onProcessDrmInfo - TYPE_RIGHTS_ACQUISITION_PROGRESS_INFO");
struct NV_DrmBuffer_st *buffer = (struct NV_DrmBuffer_st *) malloc(
sizeof(struct NV_DrmBuffer_st));
NV_ASSERT("Buffer allocation error", buffer);
bzero(buffer, sizeof(struct NV_DrmBuffer_st));
buffer->length = strlen("dummy_license_string");
buffer->data = (char *) malloc(buffer->length);
NV_ASSERT("Buffer data allocation error", buffer->data);
memcpy(buffer->data, "dummy_license_string", buffer->length);
drmInfoStatus = (struct NV_DrmInfoStatus_st *) malloc(
sizeof(struct NV_DrmInfoStatus_st));
NV_ASSERT("DrmInfoStatus allocation error", drmInfoStatus);
bzero(drmInfoStatus, sizeof(struct NV_DrmInfoStatus_st));
drmInfoStatus->statusCode = NV_DrmInfoStatus_STATUS_OK;
drmInfoStatus->infoType =
NV_DrmInfoRequest_TYPE_RIGHTS_ACQUISITION_PROGRESS_INFO;
drmInfoStatus->drmBuffer = buffer;
if (drmInfo->mimeType != NULL)
drmInfoStatus->mimeType = strdup(drmInfo->mimeType);
}
break;
}
}
ALOGV("DrmKernel_NvDrmPlugin_onProcessDrmInfo - Exit (%p)",
drmInfoStatus);
return drmInfoStatus;
}
void
NvOdmQueryPinMux(
NvOdmIoModule IoModule,
const NvU32 **pPinMuxConfigTable,
NvU32 *pCount)
{
//20101023 add tegra-10.9.3[start]
NvU32 CustomerOption = 0;
NvU32 Personality = 0;
NvU32 Ril = 0;
NvOdmServicesKeyListHandle hKeyList;
if (hKeyList)
{
CustomerOption =
NvOdmServicesGetKeyValue(hKeyList,
NvOdmKeyListId_ReservedBctCustomerOption);
NvOdmServicesKeyListClose(hKeyList);
Personality =
NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, PERSONALITY, CustomerOption);
Ril =
NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, RIL, CustomerOption);
}
if (!Personality)
Personality = TEGRA_DEVKIT_DEFAULT_PERSONALITY;
if (!Ril)
Ril = TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_DEFAULT;
//20101023 add tegra-10.9.3[end]
switch (IoModule)
{
case NvOdmIoModule_Display:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Display;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Display);
break;
case NvOdmIoModule_Dap:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Dap;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Dap);
break;
case NvOdmIoModule_Hdcp:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Hdcp;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Hdcp);
break;
case NvOdmIoModule_Hdmi:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Hdmi;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Hdmi);
break;
case NvOdmIoModule_I2c:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_I2c;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_I2c);
break;
case NvOdmIoModule_I2c_Pmu:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_I2c_Pmu;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_I2c_Pmu);
break;
case NvOdmIoModule_Kbd:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Kbd;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Kbd);
break;
case NvOdmIoModule_Mio:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Mio;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Mio);
break;
case NvOdmIoModule_Nand:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Nand;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Nand);
break;
case NvOdmIoModule_Sdio:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Sdio;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Sdio);
break;
case NvOdmIoModule_Spdif:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Spdif;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Spdif);
break;
case NvOdmIoModule_Spi:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Spi;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Spi);
break;
case NvOdmIoModule_Uart:
if (Ril == TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW_ULPI)
{
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Uart_Hsi_Ulpi;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Uart_Hsi_Ulpi);
}
else if (Ril == TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW)
{
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Uart_Ril_Emp;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Uart_Ril_Emp);
}
else
{
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Uart;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Uart);
}
break;
case NvOdmIoModule_ExternalClock:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_ExternalClock;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_ExternalClock);
break;
case NvOdmIoModule_VideoInput:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_VideoInput;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_VideoInput);
break;
case NvOdmIoModule_Crt:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Crt;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Crt);
break;
case NvOdmIoModule_Tvo:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Tvo;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Tvo);
break;
case NvOdmIoModule_Ata:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Ata;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Ata);
break;
case NvOdmIoModule_Pwm:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Pwm;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Pwm);
break;
case NvOdmIoModule_Hsi:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Hsi;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Hsi);
break;
case NvOdmIoModule_Twc:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Twc;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Twc);
break;
case NvOdmIoModule_Ulpi:
*pPinMuxConfigTable = NULL;
*pCount = 0;
break;
case NvOdmIoModule_OneWire:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_OneWire;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_OneWire);
break;
case NvOdmIoModule_SyncNor:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_SyncNor;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_SyncNor);
break;
case NvOdmIoModule_PciExpress:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_PciExpress;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_PciExpress);
break;
case NvOdmIoModule_Trace:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Ptm;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Ptm);
break;
case NvOdmIoModule_BacklightPwm:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_BacklightPwm;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_BacklightPwm);
break;
//20100725 add CPU Panel [START]
#if !defined(CONFIG_MACH_STAR)
case NvOdmIoModule_Dsi:
*pPinMuxConfigTable = s_NvOdmPinMuxConfig_Dsi;
*pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Dsi);
break;
#endif
//20100725 add CPU Panel [END]
case NvOdmIoModule_Hsmmc:
case NvOdmIoModule_Csi:
//20100725 add CPU Panel [START]
#if defined(CONFIG_MACH_STAR)
case NvOdmIoModule_Dsi:
#endif
//20100725 add CPU Panel [END]
case NvOdmIoModule_Sflash:
case NvOdmIoModule_Slink:
case NvOdmIoModule_Gpio:
case NvOdmIoModule_I2s:
case NvOdmIoModule_Usb:
case NvOdmIoModule_Vdd:
case NvOdmIoModule_Xio:
case NvOdmIoModule_Tsense:
*pCount = 0;
break;
default:
NV_ASSERT(!"Bad Parameter!");
*pCount = 0;
break;
}
}
NvBool NvOdmKeyboardInit(void)
{
NvError NvStatus = NvError_Success;
NvEcRequest Request = {0};
NvEcResponse Response = {0};
/* get nvec handle */
NvStatus = NvEcOpen(&s_NvEcHandle, 0 /* instance */);
if (NvStatus != NvError_Success)
{
goto fail;
}
/* reset the EC to start the keyboard scanning */
Request.PacketType = NvEcPacketType_Request;
Request.RequestType = NvEcRequestResponseType_Keyboard;
Request.RequestSubtype = (NvEcRequestResponseSubtype) NvEcKeyboardSubtype_Enable;
Request.NumPayloadBytes = 0;
NvStatus = NvEcSendRequest(s_NvEcHandle, &Request, &Response, sizeof(Request), sizeof(Response));
if (NvStatus != NvError_Success)
{
#if defined(CONFIG_TEGRA_ODM_BETELGEUSE)
printk("%s failed to SendRequest Keyboard:Enable\n", __func__);
#endif
goto cleanup;
}
/* check if command passed */
if (Response.Status != NvEcStatus_Success)
{
#if defined(CONFIG_TEGRA_ODM_BETELGEUSE)
printk("%s got failed response from SendRequest Keyboard:Enable\n", __func__);
#endif
goto cleanup;
}
#if WAKE_FROM_KEYBOARD
hOdm = NvOdmOsAlloc(sizeof(NvOdmKbdContext));
if (!hOdm) {
#if defined(CONFIG_TEGRA_ODM_BETELGEUSE)
printk("%s failed to NvOdmOsAlloc NvOdmKbdContext\n", __func__);
#endif
goto cleanup;
}
/* Check the supported GPIOs */
hOdm->GpioPinInfo = NvOdmQueryGpioPinMap(NvOdmGpioPinGroup_EmbeddedController,
0, &hOdm->PinCount);
NvRmGpioAcquirePinHandle(s_hGpioGlobal,
hOdm->GpioPinInfo->Port,
hOdm->GpioPinInfo->Pin,
&hOdm->hPin);
NV_ASSERT(hOdm->hPin);
if (!hOdm->hPin) {
#if defined(CONFIG_TEGRA_ODM_BETELGEUSE)
printk("%s failed to NvRmGpioAcuqirePinHandle\n", __func__);
#endif
goto cleanup;
}
/* register to receive GPIO events */
NvStatus = NvRmGpioInterruptRegister(s_hGpioGlobal,
s_hRmGlobal,
hOdm->hPin,
(NvOsInterruptHandler)GpioInterruptHandler,
NvRmGpioPinMode_InputData,
hOdm,
&hOdm->GpioIntrHandle,
DEBOUNCE_TIME_MS);
if (NvStatus != NvError_Success) {
#if defined(CONFIG_TEGRA_ODM_BETELGEUSE)
printk("%s failed to NvRmGpioInterrupRegister\n", __func__);
#endif
goto cleanup;
}
NvStatus = NvRmGpioInterruptEnable(hOdm->GpioIntrHandle);
if (NvStatus != NvError_Success) {
#if defined(CONFIG_TEGRA_ODM_BETELGEUSE)
printk("%s failed to NvRmGpioInterruptEnable\n", __func__);
#endif
goto cleanup;
}
/* enable keyboard as wake up source */
Request.PacketType = NvEcPacketType_Request;
Request.RequestType = NvEcRequestResponseType_Keyboard;
Request.RequestSubtype = (NvEcRequestResponseSubtype)
NvEcKeyboardSubtype_ConfigureWake;
Request.NumPayloadBytes = 2;
Request.Payload[0] = NVEC_KEYBOARD_WAKE_ENABLE_0_ACTION_ENABLE;
Request.Payload[1] = NVEC_KEYBOARD_EVENT_TYPE_0_ANY_KEY_PRESS_ENABLE;
NvStatus = NvEcSendRequest(s_NvEcHandle,
&Request,
&Response,
sizeof(Request),
sizeof(Response));
if (NvStatus != NvError_Success) {
#if defined(CONFIG_TEGRA_ODM_BETELGEUSE)
printk("%s failed to SendRequest Keyboard:ConfigureWake\n", __func__);
#endif
goto cleanup;
}
if (Response.Status != NvEcStatus_Success) {
#if defined(CONFIG_TEGRA_ODM_BETELGEUSE)
printk("%s got failed response from SendRequest Keyboard:ConfigureWake\n", __func__);
#endif
goto cleanup;
}
/* enable key reporting on wake up */
Request.PacketType = NvEcPacketType_Request;
Request.RequestType = NvEcRequestResponseType_Keyboard;
Request.RequestSubtype = (NvEcRequestResponseSubtype)
NvEcKeyboardSubtype_ConfigureWakeKeyReport;
Request.NumPayloadBytes = 1;
Request.Payload[0] = NVEC_KEYBOARD_REPORT_WAKE_KEY_0_ACTION_ENABLE;
NvStatus = NvEcSendRequest(s_NvEcHandle,
&Request,
&Response,
sizeof(Request),
sizeof(Response));
if (NvStatus != NvError_Success) {
#if defined(CONFIG_TEGRA_ODM_BETELGEUSE)
printk("%s failed to SendRequest Keyboard:ConfigureWakeKeyReport\n", __func__);
#endif
goto cleanup;
}
if (Response.Status != NvEcStatus_Success) {
#if defined(CONFIG_TEGRA_ODM_BETELGEUSE)
printk("%s got failed response from SendRequest Keyboard:ConfigureWakeKeyReport\n", __func__);
#endif
goto cleanup;
}
#endif
/* create semaphore which can be used to send scan codes to the clients */
s_hKbcKeyScanRecvSema = NvOdmOsSemaphoreCreate(0);
if (!s_hKbcKeyScanRecvSema)
{
#if defined(CONFIG_TEGRA_ODM_BETELGEUSE)
printk("%s failed to NvOdmOsSemaphoreCreate\n", __func__);
#endif
goto cleanup;
}
/* register for keyboard events */
NvStatus = NvEcRegisterForEvents(
s_NvEcHandle, // nvec handle
&s_hEcEventRegistration,
(NvOsSemaphoreHandle)s_hKbcKeyScanRecvSema,
sizeof(EventTypes)/sizeof(NvEcEventType),
EventTypes, // receive keyboard scan codes
1, // currently buffer only 1 packet from ECI at a time
sizeof(NvEcEvent));
if (NvStatus != NvError_Success)
{
#if defined(CONFIG_TEGRA_ODM_BETELGEUSE)
printk("%s failed to RegisterForEvents\n", __func__);
#endif
goto cleanup;
}
/* success */
return NV_TRUE;
cleanup:
#if WAKE_FROM_KEYBOARD
#if defined(CONFIG_TEGRA_ODM_BETELGEUSE)
if (hOdm)
{
if (hOdm->GpioIntrHandle)
{
NvRmGpioInterruptUnregister(s_hGpioGlobal, s_hRmGlobal, hOdm->GpioIntrHandle);
hOdm->GpioIntrHandle = NULL;
}
if (hOdm->hPin)
{
NvRmGpioReleasePinHandles(s_hGpioGlobal, &hOdm->hPin, hOdm->PinCount);
}
NvOdmOsFree(hOdm);
hOdm = NULL;
}
#endif //defined(CONFIG_TEGRA_ODM_BETELGEUSE)
#endif
(void)NvEcUnregisterForEvents(s_hEcEventRegistration);
s_hEcEventRegistration = NULL;
NvOdmOsSemaphoreDestroy(s_hKbcKeyScanRecvSema);
s_hKbcKeyScanRecvSema = NULL;
NvEcClose(s_NvEcHandle);
fail:
s_NvEcHandle = NULL;
return NV_FALSE;
}
static void
test_hash(void)
{
otama_variant_pool_t *pool = otama_variant_pool_alloc();
otama_variant_t *hash = otama_variant_new(pool);
int i;
otama_variant_t *var, *keys;
otama_variant_set_hash(hash);
var = otama_variant_hash_at(hash, "hoge");
otama_variant_set_string(var, "123hoge");
var = otama_variant_hash_at(hash, "piyo");
otama_variant_set_string(var, "-100.5");
NV_ASSERT(otama_variant_hash_exist(hash, "hoge") == 1);
NV_ASSERT(otama_variant_hash_exist(hash, "hage") == 0);
NV_ASSERT(otama_variant_hash_exist(hash, "piyo") == 1);
keys = otama_variant_hash_keys(hash);
NV_ASSERT(otama_variant_type(keys) == OTAMA_VARIANT_TYPE_ARRAY);
NV_ASSERT(otama_variant_array_count(keys) == 2);
if (strcmp(otama_variant_to_string(otama_variant_array_at(keys, 0)),
"hoge") == 0)
{
NV_ASSERT(strcmp(otama_variant_to_string(otama_variant_array_at(keys, 0)),
"hoge") == 0);
NV_ASSERT(strcmp(otama_variant_to_string(otama_variant_array_at(keys, 1)),
"piyo") == 0);
} else {
NV_ASSERT(strcmp(otama_variant_to_string(otama_variant_array_at(keys, 1)),
"hoge") == 0);
NV_ASSERT(strcmp(otama_variant_to_string(otama_variant_array_at(keys, 0)),
"piyo") == 0);
}
otama_variant_hash_remove(hash, "hoge");
otama_variant_hash_remove(hash, "piyo");
NV_ASSERT(otama_variant_hash_exist(hash, "hoge") == 0);
NV_ASSERT(otama_variant_hash_exist(hash, "piyo") == 0);
#ifdef _OPENMP
#pragma omp parallel for
#endif
for (i = 0; i < 100; ++i) {
otama_variant_t *key = otama_variant_new(pool);
otama_variant_t *v;
otama_variant_set_int(key, i);
v = otama_variant_hash_at2(hash, key);
otama_variant_set_int(v, i);
}
NV_ASSERT(otama_variant_array_count(otama_variant_hash_keys(hash)) == 100);
for (i = 0; i < 100; ++i) {
otama_variant_t *key = otama_variant_new(pool);
otama_variant_set_int(key, i);
var = otama_variant_hash_at2(hash, key);
NV_ASSERT(otama_variant_to_int(var) == i);
}
otama_variant_pool_free(&pool);
}
/* Gets the actual scan code for a key press */
NvBool NvOdmKeyboardGetKeyData(NvU32 *pKeyScanCode, NvU8 *pScanCodeFlags, NvU32 Timeout)
{
NvError NvStatus = NvError_Success;
NvU32 OutCode, OutCodeBytes, i;
NvU8 ScanCodeFlags;
if (!pKeyScanCode || !pScanCodeFlags || s_KeyboardDeinit)
{
return NV_FALSE;
}
if (Timeout != 0)
{
/* Use the timeout value */
if (!NvOdmOsSemaphoreWaitTimeout(s_hKbcKeyScanRecvSema, Timeout))
return NV_FALSE; // timed out
}
else
{
/* wait till we receive a scan code from the EC */
NvOdmOsSemaphoreWait(s_hKbcKeyScanRecvSema);
}
// stop scanning
if (s_KeyboardDeinit)
return NV_FALSE;
if (s_hEcEventRegistration)
{
NvStatus = NvEcGetEvent(s_hEcEventRegistration, &KbdEvent, sizeof(NvEcEvent));
if (NvStatus != NvError_Success)
{
NV_ASSERT(!"Could not receive scan code");
return NV_FALSE;
}
if (KbdEvent.NumPayloadBytes == 0)
{
NV_ASSERT(!"Received keyboard event with no scan codes");
return NV_FALSE;
}
// Pack scan code bytes from payload buffer into 32-bit dword
OutCode = (NvU32)KbdEvent.Payload[0];
OutCodeBytes = 1;
ScanCodeFlags = 0;
if (KbdEvent.NumPayloadBytes == 1)
NVODM_PRINTF(("EC Payload = 0x%x", KbdEvent.Payload[0]));
else
{
for (i = 0; i < KbdEvent.NumPayloadBytes; i++)
NVODM_PRINTF(("EC Payload = 0x%x", KbdEvent.Payload[i]));
}
for (i = 1; i < KbdEvent.NumPayloadBytes; i++)
{
if (KbdEvent.Payload[i-1] == SC1_PREFIX_E0)
{
// Temporary clear break flag just to check for extended shifts.
// If detected, remove the entire extended shift sequence, as
// it has no effect on SC1-to-VK translation
NvU8 sc = KbdEvent.Payload[i] & (~SC1_BREAK_MASK);
if ((sc == SC1_LSHIFT) || (sc == SC1_RSHIFT))
{
OutCode = OutCode >> 8;
OutCodeBytes--;
continue;
}
else if (KbdEvent.Payload[i] == SC1_SCROLL)
{
// If extended ScrollLock = Ctrl+Break, detected store it,
// set both make/break flags, and abort buffer packing, as
// the following bytes are just the break part of sequence
OutCode = (OutCode << 8) | ((NvU32)KbdEvent.Payload[i]);
OutCodeBytes++;
ScanCodeFlags = NV_ODM_SCAN_CODE_FLAG_MAKE |
NV_ODM_SCAN_CODE_FLAG_BREAK;
break;
}
}
int
nv_eigen(nv_matrix_t *eigen_vec,
nv_matrix_t *eigen_val,
const nv_matrix_t *mat,
int n,
int max_epoch)
{
int i;
nv_matrix_t *a = nv_matrix_dup(mat);
nv_matrix_t *vec_tmp = nv_matrix_alloc(a->m, 1);
#if NV_ENABLE_SSE2
const int pk_lp = (a->n & 0xfffffffc);
#endif
NV_ASSERT(n > 0);
NV_ASSERT(n <= mat->m);
NV_ASSERT(n <= eigen_vec->m);
NV_ASSERT(n <= eigen_val->m);
NV_ASSERT(mat->m == mat->n);
NV_ASSERT(mat->m == eigen_vec->n);
nv_matrix_zero(eigen_val);
nv_matrix_fill(eigen_vec, 1.0f);
nv_vector_normalize_all(eigen_vec);
for (i = 0; i < n; ++i) {
int k, jj;
float lambda_old;
for (k = 0; k < max_epoch; ++k) {
int j;
float lambda;
#ifdef _OPENMP
#pragma omp parallel for
#endif
for (j = 0; j < a->m; ++j) {
NV_MAT_V(vec_tmp, 0, j) = nv_vector_dot(a, j, eigen_vec, i);
}
lambda = nv_vector_norm(vec_tmp, 0);
if (lambda > 0.0f) {
nv_vector_muls(vec_tmp, 0, vec_tmp, 0, 1.0f / lambda);
}
NV_MAT_V(eigen_val, i, 0) = lambda;
nv_vector_copy(eigen_vec, i, vec_tmp, 0);
if (k > 0) {
if (fabsf(lambda_old - lambda) < FLT_EPSILON) {
break;
}
}
lambda_old = NV_MAT_V(eigen_val, i, 0);
}
#if NV_ENABLE_SSE2
{
const __m128 val = _mm_set1_ps(NV_MAT_V(eigen_val, i, 0));
#ifdef _OPENMP
#pragma omp parallel for
#endif
for (jj = 0; jj < a->m; ++jj) {
int ii;
const __m128 vjj = _mm_set1_ps(NV_MAT_V(eigen_vec, i, jj));
for (ii = 0; ii < pk_lp; ii += 4) {
_mm_store_ps(&NV_MAT_V(a, jj, ii),
_mm_sub_ps(*(const __m128 *)&NV_MAT_V(a, jj, ii),
_mm_mul_ps(val,_mm_mul_ps(vjj, *(const __m128 *)&NV_MAT_V(eigen_vec, i, ii)))));
}
for (; ii < a->n; ++ii) {
NV_MAT_V(a, jj, ii) -=
NV_MAT_V(eigen_val, i, 0)
* NV_MAT_V(eigen_vec, i, ii)
* NV_MAT_V(eigen_vec, i, jj);
}
}
}
#else
#ifdef _OPENMP
#pragma omp parallel for
#endif
for (jj = 0; jj < a->m; ++jj) {
int ii;
for (ii = 0; ii < a->n; ++ii) {
NV_MAT_V(a, jj, ii) -=
NV_MAT_V(eigen_val, i, 0)
* NV_MAT_V(eigen_vec, i, ii)
* NV_MAT_V(eigen_vec, i, jj);
}
}
#endif
}
nv_matrix_free(&vec_tmp);
nv_matrix_free(&a);
return 0;
}
NvBool Adt7461Init(NvOdmTmonDeviceHandle hTmon)
{
NvU8 Data;
NvBool ExtRange;
NvU32 i = 0;
NvU32 I2cInstance = 0;
NvOdmIoModule I2cModule = NvOdmIoModule_Num; // Inavlid module
const ADT7461RegisterInfo* pReg = NULL;
ADT7461PrivData* pPrivData = NULL;
NV_ASSERT(hTmon && hTmon->pConn && hTmon->pConn->AddressList);
// Allocate and clear priavte data
pPrivData = (ADT7461PrivData*) NvOdmOsAlloc(sizeof(ADT7461PrivData));
if (pPrivData == NULL)
{
NVODM_ADT7461_PRINTF(("ADT7461: Error Allocating PrivData. \n"));
return NV_FALSE;
}
NvOdmOsMemset(pPrivData, 0, sizeof(ADT7461PrivData));
hTmon->pPrivate = pPrivData;
// Register for PMU services
pPrivData->hOdmPmuSevice = NvOdmServicesPmuOpen();
if (pPrivData->hOdmPmuSevice == NULL)
{
NVODM_ADT7461_PRINTF(("ADT7461: Error Open PMU service. \n"));
goto fail;
}
// Register for GPIO services
pPrivData->hGpio = NvOdmGpioOpen();
if (pPrivData->hOdmPmuSevice == NULL)
{
NVODM_ADT7461_PRINTF(("ADT7461: Error Open GPIO service. \n"));
goto fail;
}
/*
* Parse connectivity data: turn On power to the device, acquire I2C
* interface and GPIO interrupt (optional); map device channels to
* thermal zones
*/
for (i = 0; i < hTmon->pConn->NumAddress; i ++)
{
const NvOdmIoAddress* pIoAddress = &hTmon->pConn->AddressList[i];
if (pIoAddress->Interface == NvOdmIoModule_I2c_Pmu)
{
I2cModule = NvOdmIoModule_I2c_Pmu;
I2cInstance = pIoAddress->Instance;
NV_ASSERT(pIoAddress->Address != 0);
pPrivData->DeviceI2cAddr = pIoAddress->Address;
}
else if (pIoAddress->Interface == NvOdmIoModule_Tsense)
{
NV_ASSERT(pIoAddress->Instance < NvOdmTmonZoneID_Num);
NV_ASSERT(pIoAddress->Address < ADT7461ChannelID_Num);
pPrivData->ConnectivityMap[pIoAddress->Instance] =
pIoAddress->Address;
}
else if (pIoAddress->Interface == NvOdmIoModule_Vdd)
{
NvU32 usec = 0;
NvU32 RailAddress = pIoAddress->Address;
NvOdmServicesPmuVddRailCapabilities RailCapabilities;
NvOdmServicesPmuGetCapabilities(
pPrivData->hOdmPmuSevice, RailAddress, &RailCapabilities);
NvOdmServicesPmuSetVoltage(pPrivData->hOdmPmuSevice, RailAddress,
RailCapabilities.requestMilliVolts, &usec);
NvOdmOsWaitUS(usec + (ADT7461_POWERUP_DELAY_MS * 1000));
}
else if (pIoAddress->Interface == NvOdmIoModule_Gpio)
{
NvU32 port = pIoAddress->Instance;
NvU32 pin = pIoAddress->Address;
pPrivData->hGpioPin = NvOdmGpioAcquirePinHandle(
pPrivData->hGpio, port, pin);
}
}
NV_ASSERT(I2cModule == NvOdmIoModule_I2c_Pmu);
pPrivData->hOdmI2C = NvOdmI2cOpen(I2cModule, I2cInstance);
if (pPrivData->hOdmI2C == NULL)
{
NVODM_ADT7461_PRINTF(("ADT7461: Error Open I2C device. \n"));
goto fail;
}
/*
* Initialize device info and configuration. Force standby mode to avoid
* glitch on shutdown comparator output when temperature range and/or
* comparator limit is changing during initialization. The Adt7461Run()
* call from the hal that follows initialization will switch device to
* run mode and re-start temperature monitoring (note that out of limit
* interrupt is always masked during and after initialization)
*/
pPrivData->pDeviceInfo = &s_Adt7461Info;
pPrivData->ShadowRegPtr = ADT7461_INVALID_ADDR;
pReg = &pPrivData->pDeviceInfo->Config;
if (!Adt7461ReadReg(pPrivData, pReg, &Data))
goto fail;
if ((Data & ADT7461ConfigBits_ExtendedRange) !=
(ADT7461_INITIAL_CONFIG & ADT7461ConfigBits_ExtendedRange))
{
// Only switch from standard to extended range is supported
NV_ASSERT((Data & ADT7461ConfigBits_ExtendedRange) == 0);
Data |= ADT7461ConfigBits_Standby;
if(!Adt7461WriteReg(pPrivData, pReg, Data))
goto fail;
}
Data = ADT7461_INITIAL_CONFIG | ADT7461ConfigBits_Standby;
if(!Adt7461WriteReg(pPrivData, pReg, Data))
goto fail;
pPrivData->ShadowConfig = Data;
ExtRange = ((Data & ADT7461ConfigBits_ExtendedRange) != 0);
// Program shutdown comparators settings
Data = ADT7461_T_VALUE_TO_DATA(
ExtRange, ADT7461_ODM_LOCAL_COMPARATOR_LIMIT_VALUE);
pReg = &pPrivData->pDeviceInfo->Channels[
ADT7461ChannelID_Local].ComparatorLimit;
if(!Adt7461WriteReg(pPrivData, pReg, Data))
goto fail;
Data = ADT7461_T_VALUE_TO_DATA(
ExtRange, ADT7461_ODM_REMOTE_COMPARATOR_LIMIT_VALUE);
pReg = &pPrivData->pDeviceInfo->Channels[
ADT7461ChannelID_Remote].ComparatorLimit;
if(!Adt7461WriteReg(pPrivData, pReg, Data))
goto fail;
// Set interrupt limits to the range boundaries to prevent out of limit
// interrupt
Data = ADT7461_T_VALUE_TO_DATA(
ExtRange, ADT7461_T_RANGE_LIMIT_HIGH(ExtRange));
pReg = &pPrivData->pDeviceInfo->Channels[
ADT7461ChannelID_Local].IntrLimitHigh;
if(!Adt7461WriteReg(pPrivData, pReg, Data))
goto fail;
pReg = &pPrivData->pDeviceInfo->Channels[
ADT7461ChannelID_Remote].IntrLimitHigh;
if(!Adt7461WriteReg(pPrivData, pReg, Data))
goto fail;
Data = ADT7461_T_VALUE_TO_DATA(
ExtRange, ADT7461_T_RANGE_LIMIT_LOW(ExtRange));
pReg = &pPrivData->pDeviceInfo->Channels[
ADT7461ChannelID_Local].IntrLimitLow;
if(!Adt7461WriteReg(pPrivData, pReg, Data))
goto fail;
pReg = &pPrivData->pDeviceInfo->Channels[
ADT7461ChannelID_Remote].IntrLimitLow;
if(!Adt7461WriteReg(pPrivData, pReg, Data))
goto fail;
// Set initial rate
Data = ADT7461_INITIAL_RATE_SETTING;
pReg = &pPrivData->pDeviceInfo->Rate;
if(!Adt7461WriteReg(pPrivData, pReg, Data))
goto fail;
pPrivData->ShadowRate = Data;
// Set remote channel offset (8-bit 2's complement value for any range)
Data = ((NvU8)ADT7461_ODM_REMOTE_OFFSET_VALUE);
pReg = &pPrivData->pDeviceInfo->Channels[
ADT7461ChannelID_Remote].Toffset;
if(!Adt7461WriteReg(pPrivData, pReg, Data))
goto fail;
// Read ADT7461 status and ARA (clear pending Alert interrupt, if any)
pReg = &pPrivData->pDeviceInfo->Status;
if (!Adt7461ReadReg(pPrivData, pReg, &Data))
goto fail;
// TODO: check open remote circuit error
Adt7461ReadAra(pPrivData);
return NV_TRUE;
fail:
Adt7461FreePrivData(pPrivData);
hTmon->pPrivate = NULL;
return NV_FALSE;
}
NvModelExtVK::NvModelExtVK(NvModelExt* pSourceModel) :
m_pSourceModel(pSourceModel),
m_instanced(false)
{
NV_ASSERT(NULL != pSourceModel);
}
NvBool
Adt7461ParameterConfig(
NvOdmTmonDeviceHandle hTmon,
NvOdmTmonZoneID ZoneId,
NvOdmTmonConfigParam ParamId,
NvS32* pSetting)
{
NvU8 Data;
NvBool ExtRange, OdmProtected;
ADT7461PrivData* pPrivData;
const ADT7461RegisterInfo* pReg;
const ADT7461ChannelInfo* pChannel;
NV_ASSERT(hTmon && hTmon->pPrivate && pSetting);
pPrivData = hTmon->pPrivate;
ExtRange = ((pPrivData->ShadowConfig &
ADT7461ConfigBits_ExtendedRange) != 0);
pChannel = &pPrivData->pDeviceInfo->Channels[(
pPrivData->ConnectivityMap[ZoneId])];
switch (ParamId)
{
case NvOdmTmonConfigParam_IntrLimitHigh:
pReg = &pChannel->IntrLimitHigh;
OdmProtected = pChannel->ChannelPolicy.IntrLimitsOdmProtected;
break;
case NvOdmTmonConfigParam_IntrLimitLow:
pReg = &pChannel->IntrLimitLow;
OdmProtected = pChannel->ChannelPolicy.IntrLimitsOdmProtected;
break;
case NvOdmTmonConfigParam_HwLimitCrit:
pReg = &pChannel->ComparatorLimit;
OdmProtected = pChannel->ChannelPolicy.HwLimitCritOdmProtected;
break;
case NvOdmTmonConfigParam_SampleMs:
OdmProtected = pChannel->ChannelPolicy.RateOdmProtected;
return Adt7461ConfigureSampleInterval(
pPrivData, OdmProtected, pSetting);
default: // unsupported parameter
*pSetting = ODM_TMON_PARAMETER_UNSPECIFIED;
return NV_TRUE;
}
// Common processing for temperature limits configuration
if ((OdmProtected) ||
((*pSetting) == ODM_TMON_PARAMETER_UNSPECIFIED))
{
// Read ADT7461 register and convert data to current parameter value
if(!Adt7461ReadReg(pPrivData, pReg, &Data))
return NV_FALSE;
*pSetting = ADT7461_T_DATA_TO_VALUE(ExtRange, Data);
}
else
{
// Clip target setting to temperature range
if ((*pSetting) > ADT7461_T_RANGE_LIMIT_HIGH(ExtRange))
*pSetting = ADT7461_T_RANGE_LIMIT_HIGH(ExtRange);
else if ((*pSetting) < ADT7461_T_RANGE_LIMIT_LOW(ExtRange))
*pSetting = ADT7461_T_RANGE_LIMIT_LOW(ExtRange);
// Convert new configuration setting and write to ADT7461 register
Data = ADT7461_T_VALUE_TO_DATA(ExtRange, *pSetting);
if(!Adt7461WriteReg(pPrivData, pReg, Data))
return NV_FALSE;
}
return NV_TRUE;
}
CNvEvent::CNvEvent(bool bManual, bool bSet) :
m_pThreading(INvThreading::GetThreading())
{
NV_ASSERT(m_pThreading->EventCreate(&m_uHandle, bManual, bSet) == RESULT_OK);
}
/*
* After enable/disable threshold, we should remove all of interrupt flag
* that may be left from that last threshold.
*/
NvBool
NvOdmAccelSetIntEnable(NvOdmAccelHandle hDevice,
NvOdmAccelIntType IntType,
NvOdmAccelAxisType IntAxis,
NvU32 IntNum,
NvBool Toggle)
{
NvU32 uTemp = 0;
NV_ASSERT(NULL != hDevice);
switch(IntType)
{
case NvOdmAccelInt_MotionThreshold:
NvOdmAccelerometerGetParameter(hDevice, XLR_INTCONTROL, &uTemp);
//NvOdmOsDebugPrintf("INTCONTROL is 0x%x g\n", uTemp);
uTemp |= XLR_INTCONTROL_COM_INT_ENABLE;
switch(IntAxis)
{
case NvOdmAccelAxis_X:
{
if(Toggle == NV_TRUE)
{
uTemp |= XLR_INTCONTROL_COM_SRC_X;
}
else
{
uTemp &= XLR_INTCONTROL_COM_SRC_X_MASK;
}
break;
}
case NvOdmAccelAxis_Y:
{
if(Toggle == NV_TRUE)
{
uTemp |= XLR_INTCONTROL_COM_SRC_Y;
}
else
{
uTemp &= XLR_INTCONTROL_COM_SRC_Y_MASK;
}
break;
}
case NvOdmAccelAxis_Z:
{
if(Toggle == NV_TRUE)
{
uTemp |= XLR_INTCONTROL_COM_SRC_Z;
}
else
{
uTemp &= XLR_INTCONTROL_COM_SRC_Z_MASK;
}
break;
}
case NvOdmAccelAxis_All:
{
if(Toggle == NV_TRUE)
{
uTemp |= XLR_INTCONTROL_COM_SRC_X;
uTemp |= XLR_INTCONTROL_COM_SRC_Y;
uTemp |= XLR_INTCONTROL_COM_SRC_Z;
}
else
{
uTemp &= XLR_INTCONTROL_COM_SRC_X_MASK;
uTemp &= XLR_INTCONTROL_COM_SRC_Y_MASK;
uTemp &= XLR_INTCONTROL_COM_SRC_Z_MASK;
}
break;
}
default:
return NV_FALSE;
}
NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL, uTemp);
break;
case NvOdmAccelInt_TapThreshold:
NvOdmAccelerometerGetParameter(hDevice, XLR_INTCONTROL, &uTemp);
//NvOdmOsDebugPrintf("INTCONTROL is 0x%x \n", uTemp);
uTemp |= XLR_INTCONTROL_TAP_INT_ENABLE;
NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL, uTemp);
NvOdmAccelerometerGetParameter(hDevice, XLR_INTCONTROL2, &uTemp);
//NvOdmOsDebugPrintf("INTCONTROL2 is 0x%x \n", uTemp);
switch(IntAxis)
{
case NvOdmAccelAxis_X:
{
if(Toggle == NV_TRUE)
{
uTemp |= XLR_INTCONTROL2_TAP_SRC_X;
}
else
{
uTemp &= XLR_INTCONTROL2_TAP_SRC_X_MASK;
}
break;
}
case NvOdmAccelAxis_Y:
{
if(Toggle == NV_TRUE)
{
uTemp |= XLR_INTCONTROL2_TAP_SRC_Y;
}
else
{
uTemp &= XLR_INTCONTROL2_TAP_SRC_Y_MASK;
}
break;
}
case NvOdmAccelAxis_Z:
{
if(Toggle == NV_TRUE)
{
uTemp |= XLR_INTCONTROL2_TAP_SRC_Z;
}
else
{
uTemp &= XLR_INTCONTROL2_TAP_SRC_Z_MASK;
}
break;
}
case NvOdmAccelAxis_All:
{
if(Toggle == NV_TRUE)
{
uTemp |= XLR_INTCONTROL2_TAP_SRC_X;
uTemp |= XLR_INTCONTROL2_TAP_SRC_Y;
uTemp |= XLR_INTCONTROL2_TAP_SRC_Z;
}
else
{
uTemp &= XLR_INTCONTROL2_TAP_SRC_X_MASK;
uTemp &= XLR_INTCONTROL2_TAP_SRC_Y_MASK;
uTemp &= XLR_INTCONTROL2_TAP_SRC_Z_MASK;
}
break;
}
default:
return NV_FALSE;
}
NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL2, uTemp);
break;
default:
//NVODMACCELEROMETER_PRINTF("Do not support such Interrupt!\n");
return NV_FALSE;
}
// Clear interrupt flag.
NvOdmAccelerometerGetParameter(hDevice, XLR_INTCONTROL2, &uTemp);
uTemp |= XLR_INTCONTROL2_CLR_INT;
NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL2, uTemp);
uTemp &= XLR_INTCONTROL2_CLR_INT_MASK;
NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL2, uTemp);
return NV_TRUE;
}