//------------------------------------------------------------------------------
//
// Function: UpdateVoltageLevels
//
// update voltage levels
//
void UpdateVoltageLevels(pCPU_OPP_Settings opp_setting)
{
OMAP_PRCM_GLOBAL_PRM_REGS* pPrcmGblPRM = OALPAtoUA(OMAP_PRCM_GLOBAL_PRM_REGS_PA);
//---------------------------------
// setup voltage processors
//
// setup i2c for smps communication
OUTREG32(&pPrcmGblPRM->PRM_VC_SMPS_SA, BSP_VC_SMPS_SA_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VC_SMPS_VOL_RA, BSP_VC_SMPS_VOL_RA_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VC_SMPS_CMD_RA, BSP_VC_SMPS_CMD_RA_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VC_CH_CONF, BSP_VC_CH_CONF_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VC_I2C_CFG, BSP_PRM_VC_I2C_CFG_INIT);
// set intial voltage levels
OUTREG32(&pPrcmGblPRM->PRM_VC_CMD_VAL_0, (opp_setting->VDD1Init << 24) | BSP_PRM_VC_CMD_VAL_0_INIT );
OUTREG32(&pPrcmGblPRM->PRM_VC_CMD_VAL_1, (opp_setting->VDD2Init << 24) | BSP_PRM_VC_CMD_VAL_1_INIT);
// set PowerIC error offset, gains, and initial voltage
OUTREG32(&pPrcmGblPRM->PRM_VP1_CONFIG, (opp_setting->VDD1Init << 8) | BSP_PRM_VP1_CONFIG_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VP2_CONFIG, (opp_setting->VDD2Init << 8) | BSP_PRM_VP2_CONFIG_INIT);
// set PowerIC slew range
OUTREG32(&pPrcmGblPRM->PRM_VP1_VSTEPMIN, BSP_PRM_VP1_VSTEPMIN_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VP1_VSTEPMAX, BSP_PRM_VP1_VSTEPMAX_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VP2_VSTEPMIN, BSP_PRM_VP2_VSTEPMIN_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VP2_VSTEPMAX, BSP_PRM_VP2_VSTEPMAX_INIT);
// set PowerIC voltage limits and timeout
OUTREG32(&pPrcmGblPRM->PRM_VP1_VLIMITTO, BSP_PRM_VP1_VLIMITTO_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VP2_VLIMITTO, BSP_PRM_VP2_VLIMITTO_INIT);
// enable voltage processor
SETREG32(&pPrcmGblPRM->PRM_VP1_CONFIG, SMPS_VPENABLE);
SETREG32(&pPrcmGblPRM->PRM_VP2_CONFIG, SMPS_VPENABLE);
// enable timeout
SETREG32(&pPrcmGblPRM->PRM_VP1_CONFIG, SMPS_TIMEOUTEN);
SETREG32(&pPrcmGblPRM->PRM_VP2_CONFIG, SMPS_TIMEOUTEN);
// flush commands to smps
SETREG32(&pPrcmGblPRM->PRM_VP1_CONFIG, SMPS_FORCEUPDATE | SMPS_INITVDD);
SETREG32(&pPrcmGblPRM->PRM_VP2_CONFIG, SMPS_FORCEUPDATE | SMPS_INITVDD);
// allow voltage to settle
OALStall(100);
// disable voltage processor
CLRREG32(&pPrcmGblPRM->PRM_VP1_CONFIG, SMPS_VPENABLE | SMPS_FORCEUPDATE | SMPS_INITVDD | SMPS_TIMEOUTEN);
CLRREG32(&pPrcmGblPRM->PRM_VP2_CONFIG, SMPS_VPENABLE | SMPS_FORCEUPDATE | SMPS_INITVDD | SMPS_TIMEOUTEN);
}
void LcdSleep(DWORD dwMilliseconds)
{
OALStall(1000 * dwMilliseconds);
}
void LcdStall(DWORD dwMicroseconds)
{
OALStall(dwMicroseconds);
}
//------------------------------------------------------------------------------
//
// Function: MemorySetup
//
// Initializes memory interfaces.
//
static VOID MemorySetup()
{
OMAP_GPMC_REGS* pGpmc = OALPAtoUA(OMAP_GPMC_REGS_PA);
OMAP_SDRC_REGS* pSdrc = OALPAtoUA(OMAP_SDRC_REGS_PA);
OMAP_PRCM_GLOBAL_PRM_REGS * pPrmGlobal = OALPAtoUA(OMAP_PRCM_GLOBAL_PRM_REGS_PA);
OMAP_SYSC_PADCONFS_REGS *pConfig = OALPAtoUA(OMAP_SYSC_PADCONFS_REGS_PA);
DDR_DEVICE_TYPE ddr_type = DDR_TYPE_MICRON;
DDR_DEVICE_PARAM *pDDR_param;
unsigned int val = 0;
BOOL bColdBoot;
#ifdef FIX_DDR_STALL_ERRATA
OMAP_PRCM_CORE_CM_REGS* pPrcmCoreCM = OALPAtoUA(OMAP_PRCM_CORE_CM_REGS_PA);
OMAP_SMS_REGS* pSms = OALPAtoUA(OMAP_SMS_REGS_PA);
#endif
// Global GPMC Configuration
OUTREG32(&pGpmc->GPMC_SYSCONFIG, 0x00000008); // No idle, L3 clock free running
OUTREG32(&pGpmc->GPMC_IRQENABLE, 0x00000000); // All interrupts disabled
OUTREG32(&pGpmc->GPMC_TIMEOUT_CONTROL, 0x00000000); // Time out disabled
OUTREG32(&pGpmc->GPMC_CONFIG, 0x00000011); // WP high, force posted write for NAND
#ifdef FMD_ONENAND
// Configure CS0 for OneNAND, Base Address 0x0C000000
OUTREG32(&pGpmc->GPMC_CONFIG1_0, BSP_GPMC_ONENAND_CONFIG1);
OUTREG32(&pGpmc->GPMC_CONFIG2_0, BSP_GPMC_ONENAND_CONFIG2);
OUTREG32(&pGpmc->GPMC_CONFIG3_0, BSP_GPMC_ONENAND_CONFIG3);
OUTREG32(&pGpmc->GPMC_CONFIG4_0, BSP_GPMC_ONENAND_CONFIG4);
OUTREG32(&pGpmc->GPMC_CONFIG5_0, BSP_GPMC_ONENAND_CONFIG5);
OUTREG32(&pGpmc->GPMC_CONFIG6_0, BSP_GPMC_ONENAND_CONFIG6);
OUTREG32(&pGpmc->GPMC_CONFIG7_0, BSP_GPMC_ONENAND_CONFIG7);
#endif
if(gCPU_family == CPU_FAMILY_DM37XX)
{
#ifdef FMD_NAND
// Configure CS0 for NAND, Base Address 0x08000000
OUTREG32(&pGpmc->GPMC_CONFIG1_0, BSP_GPMC_NAND_CONFIG1_200);
OUTREG32(&pGpmc->GPMC_CONFIG2_0, BSP_GPMC_NAND_CONFIG2_200);
OUTREG32(&pGpmc->GPMC_CONFIG3_0, BSP_GPMC_NAND_CONFIG3_200);
OUTREG32(&pGpmc->GPMC_CONFIG4_0, BSP_GPMC_NAND_CONFIG4_200);
OUTREG32(&pGpmc->GPMC_CONFIG5_0, BSP_GPMC_NAND_CONFIG5_200);
OUTREG32(&pGpmc->GPMC_CONFIG6_0, BSP_GPMC_NAND_CONFIG6_200);
OUTREG32(&pGpmc->GPMC_CONFIG7_0, BSP_GPMC_NAND_CONFIG7);
#endif
// Configure CS5 for LAN, Base Address 0x15000000
OUTREG32(&pGpmc->GPMC_CONFIG1_5, BSP_GPMC_LAN_CONFIG1_200);
OUTREG32(&pGpmc->GPMC_CONFIG2_5, BSP_GPMC_LAN_CONFIG2_200);
OUTREG32(&pGpmc->GPMC_CONFIG3_5, BSP_GPMC_LAN_CONFIG3_200);
OUTREG32(&pGpmc->GPMC_CONFIG4_5, BSP_GPMC_LAN_CONFIG4_200);
OUTREG32(&pGpmc->GPMC_CONFIG5_5, BSP_GPMC_LAN_CONFIG5_200);
OUTREG32(&pGpmc->GPMC_CONFIG6_5, BSP_GPMC_LAN_CONFIG6_200);
OUTREG32(&pGpmc->GPMC_CONFIG7_5, BSP_GPMC_LAN_CONFIG7);
ddr_type = DDR_TYPE_HYNIX;
}
else if (gCPU_family == CPU_FAMILY_OMAP35XX)
{
#ifdef FMD_NAND
// Configure CS0 for NAND, Base Address 0x08000000
OUTREG32(&pGpmc->GPMC_CONFIG1_0, BSP_GPMC_NAND_CONFIG1_166);
OUTREG32(&pGpmc->GPMC_CONFIG2_0, BSP_GPMC_NAND_CONFIG2_166);
OUTREG32(&pGpmc->GPMC_CONFIG3_0, BSP_GPMC_NAND_CONFIG3_166);
OUTREG32(&pGpmc->GPMC_CONFIG4_0, BSP_GPMC_NAND_CONFIG4_166);
OUTREG32(&pGpmc->GPMC_CONFIG5_0, BSP_GPMC_NAND_CONFIG5_166);
OUTREG32(&pGpmc->GPMC_CONFIG6_0, BSP_GPMC_NAND_CONFIG6_166);
OUTREG32(&pGpmc->GPMC_CONFIG7_0, BSP_GPMC_NAND_CONFIG7);
#endif
// Configure CS5 for LAN, Base Address 0x15000000
OUTREG32(&pGpmc->GPMC_CONFIG1_5, BSP_GPMC_LAN_CONFIG1_166);
OUTREG32(&pGpmc->GPMC_CONFIG2_5, BSP_GPMC_LAN_CONFIG2_166);
OUTREG32(&pGpmc->GPMC_CONFIG3_5, BSP_GPMC_LAN_CONFIG3_166);
OUTREG32(&pGpmc->GPMC_CONFIG4_5, BSP_GPMC_LAN_CONFIG4_166);
OUTREG32(&pGpmc->GPMC_CONFIG5_5, BSP_GPMC_LAN_CONFIG5_166);
OUTREG32(&pGpmc->GPMC_CONFIG6_5, BSP_GPMC_LAN_CONFIG6_166);
OUTREG32(&pGpmc->GPMC_CONFIG7_5, BSP_GPMC_LAN_CONFIG7);
ddr_type = DDR_TYPE_MICRON;
}
else
{
/* Not supported CPU family , use default ddr_type */
}
// check global reset status
val = INREG32(&pPrmGlobal->PRM_RSTST);
if (val & (GLOBAL_SW_RST | EXTERNAL_WARM_RST))
bColdBoot = FALSE;
else
bColdBoot = TRUE;
#ifdef FIX_DDR_STALL_ERRATA
// Re-enable SDRC interface clock in case we come back from warm reset
SETREG32(&pPrcmCoreCM->CM_ICLKEN1_CORE, CM_CLKEN_SDRC);
{
volatile int timeout = 1000;
while(((INREG32(&pPrcmCoreCM->CM_IDLEST1_CORE) & CM_CLKEN_SDRC) != 0) || (timeout-- > 0))
{
OALStall(1);
}
}
#endif
// read config register
INREG32(&pSdrc->SDRC_SYSCONFIG);
pDDR_param = &BSP_DDR_device_params[ddr_type];
if (bColdBoot == FALSE)
{
#ifdef FIX_DDR_STALL_ERRATA
// As per advisory 3.1.1.178 in errata sheet
// Reset SMS controller first
SETREG32(&pSms->SMS_SYSCONFIG, SMS_SYSCONFIG_SOFTRESET);
{
volatile int timeout = 1000;
while(((INREG32(&pSms->SMS_SYSSTATUS) & SMS_SYSSTATUS_RESETDONE) == 0) || (timeout-- > 0))
{
OALStall(1);
}
}
//Reset SDRC controller
OUTREG32(&pSdrc->SDRC_SYSCONFIG, SDRC_SYSCONFIG_SOFTRESET);
{
volatile int timeout = 1000;
while(((INREG32(&pSdrc->SDRC_SYSSTATUS) & SDRC_SYSSTATUS_RESETDONE) == 0) || (timeout-- > 0))
{
OALStall(1);
}
}
#else
//After warm reset, the SDRC will be unreliable and this will cause eboot image can't be copied from NAND flash to SDRAM correctly.
//Therefore, we have to force SDRC to reset after warm reset to solve this issue.
//SDRC reset by software
OUTREG32(&pSdrc->SDRC_SYSCONFIG, SDRC_SYSCONFIG_SOFTRESET);
// wait for at least 1000us
OALStall(1000);
//After SDRC reset, we do below steps to configure SDRC regisger again.
#endif
}
//if (bColdBoot == TRUE)
{
// Disable SDRC power saving mode
CLRREG32(&pSdrc->SDRC_POWER, SDRC_POWER_PWDENA);
// update memory cofiguration
OUTREG32(&pSdrc->SDRC_MCFG_0, pDDR_param->mcfg0);
OUTREG32(&pSdrc->SDRC_MCFG_1, pDDR_param->mcfg1);
OUTREG32(&pSdrc->SDRC_SHARING, BSP_SDRC_SHARING);
// wait for at least 200us
OALStall(2000);
// set autorefresh
OUTREG32(&pSdrc->SDRC_RFR_CTRL_0, pDDR_param->rfr_ctrl0);
OUTREG32(&pSdrc->SDRC_RFR_CTRL_1, pDDR_param->rfr_ctrl1);
// setup ac timings
OUTREG32(&pSdrc->SDRC_ACTIM_CTRLA_0, pDDR_param->actim_ctrla0);
OUTREG32(&pSdrc->SDRC_ACTIM_CTRLA_1, pDDR_param->actim_ctrla1);
OUTREG32(&pSdrc->SDRC_ACTIM_CTRLB_0, pDDR_param->actim_ctrlb0);
OUTREG32(&pSdrc->SDRC_ACTIM_CTRLB_1, pDDR_param->actim_ctrlb1);
// manual command sequence to start bank 0
OUTREG32(&pSdrc->SDRC_MANUAL_0, 0);
// wait for at least 200us
OALStall(2000);
OUTREG32(&pSdrc->SDRC_MANUAL_0, 1);
OUTREG32(&pSdrc->SDRC_MANUAL_0, 2);
OUTREG32(&pSdrc->SDRC_MANUAL_0, 2);
OUTREG32(&pSdrc->SDRC_MR_0, BSP_SDRC_MR_0);
#if BSP_MICRON_RAMSIZE_1
// manual command sequence to start bank 1
OUTREG32(&pSdrc->SDRC_MANUAL_1, 0);
// wait for at least 200us
OALStall(2000);
OUTREG32(&pSdrc->SDRC_MANUAL_1, 1);
OUTREG32(&pSdrc->SDRC_MANUAL_1, 2);
OUTREG32(&pSdrc->SDRC_MANUAL_1, 2);
OUTREG32(&pSdrc->SDRC_MR_1, BSP_SDRC_MR_1);
#endif
// re-enable power saving mode
SETREG32(&pSdrc->SDRC_POWER, SDRC_POWER_PWDENA | SDRC_POWER_SRFRONIDLEREQ);
// update sdrc dll timings
OUTREG32(&pSdrc->SDRC_DLLA_CTRL, BSP_SDRC_DLLA_CTRL);
OUTREG32(&pSdrc->SDRC_DLLB_CTRL, BSP_SDRC_DLLB_CTRL);
// update sdram characteristics
OUTREG32(&pSdrc->SDRC_EMR2_0, BSP_SDRC_EMR2_0);
OUTREG32(&pSdrc->SDRC_EMR2_1, BSP_SDRC_EMR2_1);
}
SETREG32(&pSdrc->SDRC_POWER, SDRC_POWER_SRFRONRESET);
// allow SDRC to settle
OALStall(100);
// release the force on the clke signals
OUTREG16(&pConfig->CONTROL_PADCONF_SDRC_CKE0, (INPUT_DISABLE | PULL_INACTIVE | MUX_MODE_0));
OUTREG16(&pConfig->CONTROL_PADCONF_SDRC_CKE1, (INPUT_DISABLE | PULL_INACTIVE | MUX_MODE_0));
}
//------------------------------------------------------------------------------
//
// Function: OALPCIInit
//
BOOL OALPCIInit()
{
VRC5477_REGS *pVRC5477Regs = OALPAtoUA(VRC5477_REG_PA);
M1535_CFG_REGS *pM1535Regs = OALPAtoUA(BSP_REG_PA_M1535_CFG);
OAL_PCI_LOCATION pciLoc;
UINT32 u32;
//----------------------------------------------------------------------
// External PCI
//----------------------------------------------------------------------
// Cold reset
OUTREG32(&pVRC5477Regs->PCICTL0H, PCI_CTRL_CRST);
OALStall(100000);
OUTREG32(&pVRC5477Regs->PCICTL0H, 0);
OALStall(100000);
// Setup windows
OUTREG32(&pVRC5477Regs->PCIINIT00, BSP_PCI_INIT00);
OUTREG32(&pVRC5477Regs->PCIW0, BSP_PCI_W0);
OUTREG32(&pVRC5477Regs->PCIINIT10, BSP_PCI_INIT10);
OUTREG32(&pVRC5477Regs->PCIW1, BSP_PCI_W1);
// Setup control & arbiter registers
OUTREG32(&pVRC5477Regs->PCICTL0L, BSP_PCI_CTL0L);
OUTREG32(&pVRC5477Regs->PCICTL0H, BSP_PCI_CTL0H);
OUTREG32(&pVRC5477Regs->PCIARB0L, BSP_PCI_ARB0L);
OUTREG32(&pVRC5477Regs->PCIARB0H, BSP_PCI_ARB0H);
// Setup configuration space
OUTREG16(&pVRC5477Regs->PCICMD0, BSP_PCI_CMD0);
OUTREG8(&pVRC5477Regs->MLTIM0, BSP_PCI_MLTIM0);
OUTREG32(&pVRC5477Regs->BARC0, BSP_PCI_BARC0);
OUTREG32(&pVRC5477Regs->BARM010, BSP_PCI_BARM010);
OUTREG32(&pVRC5477Regs->BARM230, BSP_PCI_BARM230);
OUTREG32(&pVRC5477Regs->BAR00, BSP_PCI_BAR00);
OUTREG32(&pVRC5477Regs->BAR10, BSP_PCI_BAR10);
OUTREG32(&pVRC5477Regs->BAR20, BSP_PCI_BAR20);
OUTREG32(&pVRC5477Regs->BARB0, BSP_PCI_BARB0);
OUTREG32(&pVRC5477Regs->BARP00, BSP_PCI_BARP00);
OUTREG32(&pVRC5477Regs->BARP10, BSP_PCI_BARP10);
//----------------------------------------------------------------------
// Internal PCI
//----------------------------------------------------------------------
OUTREG32(&pVRC5477Regs->PCICTL1H, PCI_CTRL_CRST);
OALStall(100000);
OUTREG32(&pVRC5477Regs->PCICTL1H, 0);
OALStall(100000);
// Setup internal PCI windows
OUTREG32(&pVRC5477Regs->PCIINIT01, BSP_PCI_INIT01);
OUTREG32(&pVRC5477Regs->IOPCIW0, BSP_IOPCI_W0);
OUTREG32(&pVRC5477Regs->PCIINIT11, BSP_PCI_INIT11);
OUTREG32(&pVRC5477Regs->IOPCIW1, BSP_IOPCI_W1);
// Setup control & arbiter registers
OUTREG32(&pVRC5477Regs->PCICTL1L, BSP_PCI_CTL1L);
OUTREG32(&pVRC5477Regs->PCICTL1H, BSP_PCI_CTL1H);
OUTREG32(&pVRC5477Regs->PCIARB1L, BSP_PCI_ARB1L);
OUTREG32(&pVRC5477Regs->PCIARB1H, BSP_PCI_ARB1H);
// Setup configuration space
OUTREG16(&pVRC5477Regs->PCICMD1, BSP_PCI_CMD1);
OUTREG8(&pVRC5477Regs->MLTIM1, BSP_PCI_MLTIM1);
OUTREG32(&pVRC5477Regs->BARC1, BSP_PCI_BARC1);
OUTREG32(&pVRC5477Regs->BARM011, BSP_PCI_BARM011);
OUTREG32(&pVRC5477Regs->BARM231, BSP_PCI_BARM231);
OUTREG32(&pVRC5477Regs->BAR01, BSP_PCI_BAR01);
OUTREG32(&pVRC5477Regs->BAR11, BSP_PCI_BAR11);
OUTREG32(&pVRC5477Regs->BAR21, BSP_PCI_BAR21);
OUTREG32(&pVRC5477Regs->BARB1, BSP_PCI_BARB1);
OUTREG32(&pVRC5477Regs->BARP01, BSP_PCI_BARP01);
OUTREG32(&pVRC5477Regs->BARP11, BSP_PCI_BARP11);
OALStall(10000);
//----------------------------------------------------------------------
// ALI M1535+ South Bridge
//----------------------------------------------------------------------
// Is there ALI M1535+ bridge = CPU board is inserted to SG2 mother board,
// in such case we must do some initialization --- default config address
// lines for some ALI M1535+ internal devices colide with PCI slot config
// address lines.
pciLoc.bus = 0;
pciLoc.dev = 8;
pciLoc.fnc = 0;
OALPCICfgRead(0, pciLoc, 0, sizeof(u32), &u32);
if (u32 != 0x153310B9) goto cleanUp;
//----------------------------------------------------------------------
// PCI-ISA bridge initialize
//----------------------------------------------------------------------
OALLog(L"INFO: OALPCIInit: ALI M1535+ Bridge detected\r\n");
u32 = 0x0000C119; // I/O control, select PS2 keyboad/mouse
OALPCICfgWrite(0, pciLoc, 0x40, sizeof(u32), &u32);
u32 = 0x0000025D; // Primary IDE IRQ14
OALPCICfgWrite(0, pciLoc, 0x44, sizeof(u32), &u32);
u32 = 0x70000009; // Audio->IRQ6, PCI INTC->IRQ11
OALPCICfgWrite(0, pciLoc, 0x48, sizeof(u32), &u32);
u32 = 0x00000000; // USB1 enable
OALPCICfgWrite(0, pciLoc, 0x50, sizeof(u32), &u32);
u32 = 0x00000000; // PCSJ
OALPCICfgWrite(0, pciLoc, 0x54, sizeof(u32), &u32);
u32 = 0x0000007C; // IDE IDSEL(AD15), INTR
OALPCICfgWrite(0, pciLoc, 0x58, sizeof(u32), &u32);
u32 = 0x00004000; // Document recommend???
OALPCICfgWrite(0, pciLoc, 0x6C, sizeof(u32), &u32);
u32 = 0x002600D2; // PMU IDSEL(AD14), USB IDSEL(AD13)
OALPCICfgWrite(0, pciLoc, 0x70, sizeof(u32), &u32);
u32 = 0x40801F01; // No modem, USB INTR(IRQ09), 2nd IDE IRQ15, AC97 IDSEL(AD17)
OALPCICfgWrite(0, pciLoc, 0x74, sizeof(u32), &u32);
u32 = 0x00000000; // USB2 disable
OALPCICfgWrite(0, pciLoc, 0x7C, sizeof(u32), &u32);
//---------------------------
// Configure super I/O chip
//---------------------------
OUTPORT8(&pM1535Regs->config, 0x51); // Enter config mode
OUTPORT8(&pM1535Regs->config, 0x23);
// Enable parallel port
OUTPORT8(&pM1535Regs->index, 0x07);
OUTPORT8(&pM1535Regs->data, 0x03); // Select logical device 3
OUTPORT8(&pM1535Regs->index, 0x30);
OUTPORT8(&pM1535Regs->data, 0x01); // Enable device
OUTPORT8(&pM1535Regs->index, 0x60);
OUTPORT8(&pM1535Regs->data, 0x03); // I/O address: 378h
OUTPORT8(&pM1535Regs->index, 0x61);
OUTPORT8(&pM1535Regs->data, 0x78); // I/O address: 378h
OUTPORT8(&pM1535Regs->index, 0x70);
OUTPORT8(&pM1535Regs->data, 0x07); // Irq: 7
// Enable UART1
OUTPORT8(&pM1535Regs->index, 0x07);
OUTPORT8(&pM1535Regs->data, 0x04); // Select logical device 4
OUTPORT8(&pM1535Regs->index, 0x30);
OUTPORT8(&pM1535Regs->data, 0x01); // Enable device
OUTPORT8(&pM1535Regs->index, 0x60);
OUTPORT8(&pM1535Regs->data, 0x03); // I/O address: 3F8h
OUTPORT8(&pM1535Regs->index, 0x61);
OUTPORT8(&pM1535Regs->data, 0xF8); // I/O address: 3F8h
OUTPORT8(&pM1535Regs->index, 0x70);
OUTPORT8(&pM1535Regs->data, 0x04); // Irq: 4
// Enable UART2/INFRA
OUTPORT8(&pM1535Regs->index, 0x07);
OUTPORT8(&pM1535Regs->data, 0x05); // Select logical device 5
OUTPORT8(&pM1535Regs->index, 0x30);
OUTPORT8(&pM1535Regs->data, 0x01); // Enable device
OUTPORT8(&pM1535Regs->index, 0x60);
OUTPORT8(&pM1535Regs->data, 0x03); // I/O address: 3E8h
OUTPORT8(&pM1535Regs->index, 0x61);
OUTPORT8(&pM1535Regs->data, 0xE8); // I/O address: 3E8h
OUTPORT8(&pM1535Regs->index, 0x70);
OUTPORT8(&pM1535Regs->data, 0x05); // Irq: 5
// Enable PS/2 controller
OUTPORT8(&pM1535Regs->index, 0x07);
OUTPORT8(&pM1535Regs->data, 0x07); // Select logical device 7.
OUTPORT8(&pM1535Regs->index, 0x30);
OUTPORT8(&pM1535Regs->data, 0x01); // Enable device
OUTPORT8(&pM1535Regs->index, 0x70);
OUTPORT8(&pM1535Regs->data, 0x01); // Irq: 1 - keyboard
OUTPORT8(&pM1535Regs->index, 0x72);
OUTPORT8(&pM1535Regs->data, 0x0C); // Irq: 12 - mouse
// Enable UART3
OUTPORT8(&pM1535Regs->index, 0x07);
OUTPORT8(&pM1535Regs->data, 0x0B); // Select logical device 11
OUTPORT8(&pM1535Regs->index, 0x30);
OUTPORT8(&pM1535Regs->data, 0x01); // Enable device
OUTPORT8(&pM1535Regs->index, 0x60);
OUTPORT8(&pM1535Regs->data, 0x02); // I/O address: 2F8h
OUTPORT8(&pM1535Regs->index, 0x61);
OUTPORT8(&pM1535Regs->data, 0xF8); // I/O address: 2F8h
OUTPORT8(&pM1535Regs->index, 0x70);
OUTPORT8(&pM1535Regs->data, 0x03); // Irq: 3
// Exit config mode
OUTPORT8(&pM1535Regs->config, 0xBB);
cleanUp:
return TRUE;
}
//------------------------------------------------------------------------------
//
// Function: OEMPlatformInit
//
// This function provide platform initialization functions. It is called
// from boot loader after OEMDebugInit is called. Note that boot loader
// BootloaderMain is called from s/init.s code which is run after reset.
//
BOOL
OEMPlatformInit(
)
{
OMAP_GPTIMER_REGS *pTimerRegs;
UINT32 CpuRevision, version;
HANDLE hTwl,hGPIO;
static UCHAR allocationPool[512];
static const PAD_INFO ebootPinMux[] = {
DSS_PADS
GPIO_PADS
USBOTG_PADS
END_OF_PAD_ARRAY
};
static const PAD_INFO ebootPinMux_37XX[] = {
DSS_PADS_37XX
GPIO_PADS_37XX
USBOTG_PADS
END_OF_PAD_ARRAY
};
OALLocalAllocInit(allocationPool,sizeof(allocationPool));
// Get processor and companion chip versions
g_CPUFamily = CPU_FAMILY_OMAP35XX;
CpuRevision = Get_CPUVersion();
version = CPU_REVISION(CpuRevision);
g_CPUFamily = CPU_FAMILY(CpuRevision);
// Set GPTIMER1 regs pointer
pTimerRegs = OALPAtoUA(OMAP_GPTIMER1_REGS_PA);
if(g_CPUFamily == CPU_FAMILY_DM37XX)
{
ConfigurePadArray(ebootPinMux_37XX);
}
else
{
ConfigurePadArray(ebootPinMux);
}
//OALLogSetZones(
// (1<<OAL_LOG_VERBOSE) |
// (1<<OAL_LOG_INFO) |
// (1<<OAL_LOG_ERROR) |
// (1<<OAL_LOG_WARN) |
// (1<<OAL_LOG_FUNC) |
// (1<<OAL_LOG_IO) |
// 0);
OALLog(
L"\r\nTexas Instruments Windows CE EBOOT for OMAP35xx/37xx, "
L"Built %S at %S\r\n", __DATE__, __TIME__
);
OALLog(
L"EBOOT Version %d.%d, BSP " BSP_VERSION_STRING L"\r\n",
EBOOT_VERSION_MAJOR, EBOOT_VERSION_MINOR
);
// Soft reset GPTIMER1
OUTREG32(&pTimerRegs->TIOCP, SYSCONFIG_SOFTRESET);
// While until done
while ((INREG32(&pTimerRegs->TISTAT) & GPTIMER_TISTAT_RESETDONE) == 0);
// Enable posted mode
OUTREG32(&pTimerRegs->TSICR, GPTIMER_TSICR_POSTED);
// Start timer
OUTREG32(&pTimerRegs->TCLR, GPTIMER_TCLR_AR|GPTIMER_TCLR_ST);
// Enable device clocks used by the bootloader
EnableDeviceClocks(OMAP_DEVICE_GPIO1,TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO2,TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO3,TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO4,TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO5,TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO6,TRUE);
// configure i2c devices
OALI2CInit(OMAP_DEVICE_I2C1);
OALI2CInit(OMAP_DEVICE_I2C2);
OALI2CInit(OMAP_DEVICE_I2C3);
GPIOInit();
// Note that T2 accesses must occur after I2C initialization
hTwl = TWLOpen();
hGPIO = GPIOOpen();
// Clear Reset on ethernet controller
GPIOSetBit(hGPIO,LAN9115_RESET_GPIO);
GPIOSetMode(hGPIO, LAN9115_RESET_GPIO,GPIO_DIR_OUTPUT);
//rst usb hub
GPIOClrBit(hGPIO,13);
GPIOSetMode(hGPIO, 13,GPIO_DIR_OUTPUT);
OALStall(10000);
GPIOSetBit(hGPIO,13);
OALStall(1000);
GPIOClrBit(hGPIO,13);
OALLog(L"\r\nTI OMAP%x Version 0x%08x (%s)\r\n", CPU_ID(CpuRevision), CPU_REVISION(CpuRevision),
version == CPU_FAMILY_35XX_REVISION_ES_1_0 ? L"ES1.0" :
version == CPU_FAMILY_35XX_REVISION_ES_2_0 ? L"ES2.0" :
version == CPU_FAMILY_35XX_REVISION_ES_2_1 ? L"ES2.1" :
version == CPU_FAMILY_35XX_REVISION_ES_2_0_CRC ? L"ES2.0, ID determined using CRC" :
version == CPU_FAMILY_35XX_REVISION_ES_2_1_CRC ? L"ES2.1, ID determined using CRC" :
version == CPU_FAMILY_35XX_REVISION_ES_3_0 ? L"ES3.0" :
version == CPU_FAMILY_35XX_REVISION_ES_3_1 ? L"ES3.1" :
version == CPU_FAMILY_37XX_REVISION_ES_1_0? L"ES1.0" :
version == CPU_FAMILY_37XX_REVISION_ES_1_1? L"ES1.1" :
version == CPU_FAMILY_37XX_REVISION_ES_1_2? L"ES1.2" :
L"Unknown" );
/* Initialize Device Prefix */
if(g_CPUFamily == CPU_FAMILY_DM37XX)
{
gDevice_prefix = BSP_DEVICE_37xx_PREFIX;
}
else if (g_CPUFamily == CPU_FAMILY_OMAP35XX)
{
gDevice_prefix = BSP_DEVICE_35xx_PREFIX;
}
else
{
OALLog(L"INFO: UnKnown CPU family:%d....\r\n", g_CPUFamily);
gDevice_prefix = BSP_DEVICE_35xx_PREFIX;
}
version = TWLReadIDCode(hTwl);
OALLog(L"TPS659XX Version 0x%02x (%s)\r\n", version,
version == 0x00 ? L"ES1.0" :
version == 0x10 ? L"ES1.1" :
version == 0x20 ? L"ES1.2" :
version == 0x30 ? L"ES1.3" : L"Unknown" );
g_ecctype = (UCHAR)dwEbootECCtype;
// Done
return TRUE;
}
// parses the setup packet received on EP0
BOOL HandleSetupPacket(USB_DEVICE_REQUEST *pUdr, EP0_REQUEST *pRequest)
{
if (pUdr->bmRequestType & (USB_REQUEST_CLASS | USB_REQUEST_VENDOR)) {
if (PDD_DoVendorCommand(pUdr, pRequest)) {
// do nothing
} else {
OALMSG(OAL_ERROR, (
L"**** Unhandled verndor command 0x%x\r\n", pUdr->bRequest
));
pRequest->eDir = EP0Setup;
pRequest->pucData = NULL;
pRequest->dwExpectedSize = 0;
pRequest->dwActualSize = 0;
pRequest->pfnNotification = NULL;
pRequest->pvUser = NULL;
}
return TRUE;
}
// standard chapter 9 commands
pRequest->eDir = EP0Setup;
pRequest->pucData = NULL;
pRequest->dwExpectedSize = 0;
pRequest->dwActualSize = 0;
pRequest->pfnNotification = NULL;
pRequest->pvUser = NULL;
switch(pUdr->bRequest) {
case USB_REQUEST_GET_STATUS:
if (pUdr->bmRequestType == 0x82) {
// TODO: handle this
OALMSG(OAL_WARN, (L"***RequestType==0x82\r\n"));
// check for the stall bit
}
break;
case USB_REQUEST_CLEAR_FEATURE:
if (pUdr->bmRequestType == 0x02) {
// TODO: handle this
OALMSG(OAL_WARN, (L"***RequestType==0x02\r\n"));
}
break;
case USB_REQUEST_SET_FEATURE:
if (pUdr->bmRequestType == 0x02) {
// TODO: handle this
OALMSG(OAL_WARN, (L"***RequestType==0x02\r\n"));
}
break;
case USB_REQUEST_SET_ADDRESS:
// TODO: handle this
break;
case USB_REQUEST_GET_DESCRIPTOR:
if (PDD_GetDescriptor(pUdr, pRequest)) {
// do nothing
} else {
OALMSG(OAL_ERROR, (
L"*** UnHandled GET_DESCRIPTOR request:0x%x\r\n",
pUdr->wValue
));
}
break;
case USB_REQUEST_SET_DESCRIPTOR:
// TODO: handle this
break;
case USB_REQUEST_GET_CONFIGURATION:
// TODO: handle this
break;
case USB_REQUEST_SET_CONFIGURATION:
OALStall(5000);
// setup RX transfer on EP1
SetupEP1Transfer();
////pDev->ucConfigValue = (BYTE)pUdr->wValue;
break;
case USB_REQUEST_GET_INTERFACE:
// TODO: handle this
break;
case USB_REQUEST_SET_INTERFACE:
// TODO: handle this
break;
case USB_REQUEST_SYNC_FRAME:
// TODO: handle this
break;
default:
OALMSG(OAL_WARN, (
L"*** Unknown request 0x%x\r\n", pUdr->bRequest
));
}
return TRUE;
}
BOOL
OEMKitlStartup(
)
{
BOOL rc = FALSE;
OAL_KITL_ARGS *pArgs, args;
CHAR *szDeviceId;
KITLSetDebug(
ZONE_ERROR |
ZONE_WARNING |
// ZONE_INIT |
// ZONE_KITL_OAL |
// ZONE_KITL_ETHER |
0);
KITL_RETAILMSG(ZONE_KITL_OAL, ("+OALKitlStart\r\n"));
// First get boot args and device id
pArgs = (OAL_KITL_ARGS*)OALArgsQuery(OAL_ARGS_QUERY_KITL);
// If we don't get kitl arguments use default
if (pArgs == NULL)
{
const UINT16 defaultMac[] = DEFAULT_MAC_ADDRESS;
KITL_RETAILMSG(ZONE_WARNING, (
"WARN: Boot arguments not found, use defaults\r\n"
));
memset(&args, 0, sizeof(args));
args.flags = OAL_KITL_FLAGS_ENABLED|OAL_KITL_FLAGS_DHCP;
args.devLoc.IfcType = Internal;
args.devLoc.BusNumber = 0;
args.devLoc.LogicalLoc = BSP_LAN9115_REGS_PA;
memcpy(args.mac,defaultMac,sizeof(args.mac));
pArgs = &args;
}
// We always create device name
// Try to generate from device id...
szDeviceId = OALArgsQuery(OAL_ARGS_QUERY_DEVICE_PREFIX);
if (szDeviceId == NULL) {
szDeviceId = BSP_DEVICE_35xx_PREFIX;
}
pArgs->flags |= OAL_KITL_FLAGS_EXTNAME;
// Initialize debug device
switch (pArgs->devLoc.IfcType)
{
case Internal:
switch (pArgs->devLoc.LogicalLoc)
{
case BSP_LAN9115_REGS_PA:
#if 0
// enable clocks to GPIO banks that have KITL dependencies so we can do initialization
OEMKitlEnableClocks(TRUE);
// Reset LAN chip
pGPIORegs = OALPAtoUA(BSP_RESET_ETHER_KITL_GPIO_PA);
CLRREG32(&pGPIORegs->DATAOUT, 1 << (BSP_RESET_ETHER_KITL_GPIO % 32));
OALStall(1000);
SETREG32(&pGPIORegs->DATAOUT, 1 << (BSP_RESET_ETHER_KITL_GPIO % 32));
OALStall(1000);
// Prepare interrupt
pGPIORegs = OALPAtoUA(BSP_ETHER_GPIO_PA);
SETREG32(&pGPIORegs->OE, 1 << (BSP_IRQ_ETHER_KITL % 32));
// Interrupt on falling edge
SETREG32(&pGPIORegs->FALLINGDETECT, 1 << (BSP_IRQ_ETHER_KITL % 32));
OEMKitlEnableClocks(FALSE);
#endif
break;
}
break;
}
// Finally call KITL library
rc = OALKitlInit(szDeviceId, pArgs, g_kitlDevices);
// If it failed or KITL is disabled
if (!rc || (pArgs->flags & OAL_KITL_FLAGS_ENABLED) == 0) goto cleanUp;
// enable kitl interrupts
s_bKitlActive = TRUE;
OEMKitlEnable(TRUE);
cleanUp:
KITL_RETAILMSG(ZONE_KITL_OAL, ("-OALKitlStart(rc = %d)\r\n", rc));
return rc;
}
// parses the setup packet received on EP0
BOOL HandleSetupPacket(USB_DEVICE_REQUEST *pUdr, EP0_REQUEST *pRequest)
{
BOOL rc = TRUE;
OALMSG(OAL_ETHER&&OAL_FUNC, (L"+HandleSetupPacket\r\n"));
if (pUdr->bmRequestType & (USB_REQUEST_CLASS | USB_REQUEST_VENDOR)) {
if (PDD_DoVendorCommand(pUdr, pRequest)) {
// do nothing
} else {
OALMSG(OAL_ERROR, (
L"**** Unhandled verndor command 0x%x\r\n", pUdr->bRequest
));
pRequest->eDir = EP0Setup;
pRequest->pucData = NULL;
pRequest->dwExpectedSize = 0;
pRequest->dwActualSize = 0;
pRequest->pfnNotification = NULL;
pRequest->pvUser = NULL;
}
goto ErrorReturn;
}
// standard chapter 9 commands
pRequest->eDir = EP0Setup;
pRequest->pucData = NULL;
pRequest->dwExpectedSize = 0;
pRequest->dwActualSize = 0;
pRequest->pfnNotification = NULL;
pRequest->pvUser = NULL;
switch(pUdr->bRequest) {
case USB_REQUEST_GET_STATUS:
if (pUdr->bmRequestType == 0x82) {
// Not currently handled...
OALMSG(OAL_WARN, (L"***RequestType==0x82\r\n"));
// check for the stall bit
}
break;
case USB_REQUEST_CLEAR_FEATURE:
if (pUdr->bmRequestType == 0x02) {
// Not currently handled...
OALMSG(OAL_WARN, (L"***RequestType==0x02\r\n"));
}
break;
case USB_REQUEST_SET_FEATURE:
if (pUdr->bmRequestType == 0x02) {
// Not currently handled...
OALMSG(OAL_WARN, (L"***RequestType==0x02\r\n"));
}
break;
case USB_REQUEST_SET_ADDRESS:
g_pddInterface.pfnSetAddress( g_pddInterface.pvPddContext, (UCHAR)pUdr->wValue );
break;
case USB_REQUEST_GET_DESCRIPTOR:
if (PDD_GetDescriptor(pUdr, pRequest)) {
// do nothing
} else {
OALMSG(OAL_ERROR, (
L"*** UnHandled GET_DESCRIPTOR request:0x%x\r\n",
pUdr->wValue
));
}
break;
case USB_REQUEST_SET_DESCRIPTOR:
// Not currently handled...
break;
case USB_REQUEST_GET_CONFIGURATION:
// Not currently handled...
break;
case USB_REQUEST_SET_CONFIGURATION:
OALStall(5000);
// setup RX transfer on EP1
SetupEP1Transfer();
////pDev->ucConfigValue = (BYTE)pUdr->wValue;
break;
case USB_REQUEST_GET_INTERFACE:
// Not currently handled...
break;
case USB_REQUEST_SET_INTERFACE:
// Not currently handled...
break;
case USB_REQUEST_SYNC_FRAME:
// Not currently handled...
break;
default:
OALMSG(OAL_WARN, (
L"*** Unknown request 0x%x\r\n", pUdr->bRequest
));
}
ErrorReturn:
OALMSG(OAL_ETHER&&OAL_FUNC, (L"-HandleSetupPacket\r\n"));
return rc;
}
