void __init omap_init_irq(void)
{
unsigned long nr_of_irqs = 0;
unsigned int nr_banks = 0;
int i;
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
struct omap_irq_bank *bank = irq_banks + i;
if (cpu_is_omap24xx())
bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
else if (cpu_is_omap34xx())
bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE);
omap_irq_bank_init_one(bank);
nr_of_irqs += bank->nr_irqs;
nr_banks++;
}
printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
for (i = 0; i < nr_of_irqs; i++) {
set_irq_chip(i, &omap_irq_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}
void __init omap_init_irq(void)
{
unsigned long nr_of_irqs = 0;
unsigned int nr_banks = 0;
int i;
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
struct omap_irq_bank *bank = irq_banks + i;
if (cpu_is_omapw3g())
bank->base_reg = OMAP2_IO_ADDRESS(OMAPW3G_IC_BASE);
else if (cpu_is_omap24xx())
bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
else if (cpu_is_omap34xx())
bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE);
omap_irq_bank_init_one(bank);
nr_of_irqs += bank->nr_irqs;
nr_banks++;
}
printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
for (i = 0; i < nr_of_irqs; i++) {
/* Regardless of reserved IRQ, the interrupt must be handled using kernel's main irq handler */
omap_irq_set_cfg(i, 0, irq_priority[i]);
set_irq_chip(i, &omap_irq_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}
void omap_writel(u32 v, u32 pa)
{
if (cpu_class_is_omap1())
__raw_writel(v, OMAP1_IO_ADDRESS(pa));
else
__raw_writel(v, OMAP2_IO_ADDRESS(pa));
}
static void ssi_save_ctx(struct platform_device *pdev)
{
struct hsi_platform_data *pdata = pdev->dev.platform_data;
void __iomem *base = OMAP2_IO_ADDRESS(pdev->resource[0].start);
struct port_ctx *p;
int port;
/* TODO: update support for omap_pm_get_dev_context_loss_count
pdata->ctx.loss_count =
omap_pm_get_dev_context_loss_count(&pdev->dev);
*/
pdata->ctx.sysconfig = hsi_inl(base + HSI_SYS_SYSCONFIG_REG);
pdata->ctx.gdd_gcr = hsi_inl(base + HSI_GDD_GCR_REG);
for (port = 1; port <= pdata->num_ports; port++) {
p = &pdata->ctx.pctx[port - 1];
p->sys_mpu_enable[0] = hsi_inl(base +
HSI_SYS_MPU_ENABLE_REG(port, 0));
p->sys_mpu_enable[1] = hsi_inl(base +
HSI_SYS_MPU_ENABLE_REG(port, 1));
p->hst.frame_size = hsi_inl(base +
HSI_HST_FRAMESIZE_REG(port));
p->hst.divisor = hsi_inl(base + HSI_HST_DIVISOR_REG(port));
p->hst.channels = hsi_inl(base + HSI_HST_CHANNELS_REG(port));
p->hst.arb_mode = hsi_inl(base + HSI_HST_ARBMODE_REG(port));
p->hsr.frame_size = hsi_inl(base +
HSI_HSR_FRAMESIZE_REG(port));
p->hsr.timeout = hsi_inl(base + HSI_HSR_COUNTERS_REG(port));
p->hsr.channels = hsi_inl(base + HSI_HSR_CHANNELS_REG(port));
}
}
/**
* _read_32ksynct - read the OMAP 32K sync timer
*
* Returns the current value of the 32KiHz synchronization counter.
* XXX this should be generalized to simply read the system clocksource.
* XXX this should be moved to a separate synctimer32k.c file
*/
static u32 _read_32ksynct(void)
{
if (!cpu_class_is_omap2())
BUG();
return __raw_readl(OMAP2_IO_ADDRESS(OMAP_32KSYNCT_BASE + 0x010));
}
static void hsi_restore_ctx(struct platform_device *pdev)
{
struct hsi_platform_data *pdata = pdev->dev.platform_data;
void __iomem *base = OMAP2_IO_ADDRESS(pdev->resource[0].start);
struct port_ctx *p;
int port;
int loss_count;
loss_count = omap_pm_get_dev_context_loss_count(&pdev->dev);
if (loss_count == pdata->ctx.loss_count)
return;
hsi_outl(pdata->ctx.sysconfig, base + HSI_SYS_SYSCONFIG_REG);
hsi_outl(pdata->ctx.gdd_gcr, base + HSI_GDD_GCR_REG);
for (port = 1; port <= pdata->num_ports; port++) {
p = &pdata->ctx.pctx[port - 1];
hsi_outl(p->sys_mpu_enable[0], base +
HSI_SYS_MPU_ENABLE_REG(port, 0));
hsi_outl(p->sys_mpu_enable[1], base +
HSI_SYS_MPU_U_ENABLE_REG(port, 0));
hsi_outl(p->hst.frame_size, base +
HSI_HST_FRAMESIZE_REG(port));
hsi_outl(p->hst.divisor, base + HSI_HST_DIVISOR_REG(port));
hsi_outl(p->hst.channels, base + HSI_HST_CHANNELS_REG(port));
hsi_outl(p->hst.arb_mode, base + HSI_HST_ARBMODE_REG(port));
hsi_outl(p->hsr.frame_size, base +
HSI_HSR_FRAMESIZE_REG(port));
/* FIXME - check this register */
hsi_outl(p->hsr.timeout, base + HSI_HSR_COUNTERS_REG(port));
hsi_outl(p->hsr.channels, base + HSI_HSR_CHANNELS_REG(port));
}
}
u32 omap_readl(u32 pa)
{
if (cpu_class_is_omap1())
return __raw_readl(OMAP1_IO_ADDRESS(pa));
else
return __raw_readl(OMAP2_IO_ADDRESS(pa));
}
void omap_reset_to(u16 devices[4])
{
struct omap3_boot_config boot_config;
struct omap3_scratchpad scratchpad;
if (cpu_is_omap34xx())
{
#ifdef CONFIG_MAGIC_SYSRQ
/* emergency sync */
PWARN("calling 'sysrq + s' for emergency sync\n");
handle_sysrq('s', NULL);
/* emergency umount */
PWARN("calling 'sysrq + u' for emergency umount\n");
handle_sysrq('u', NULL);
#endif
// Disable IRQ
local_irq_disable();
local_fiq_disable();
// 0xAC boot config offset = reserve for 0x1C wakeup header + 0x38 PRCM block + 0x58 SDRC block
scratchpad.boot_config_ptr = OMAP343X_SCRATCHPAD + 0xAC;
scratchpad.public_restore_ptr = 0;
scratchpad.secure_ram_restore_ptr = 0;
scratchpad.sdrc_module_semaphore = 0;
scratchpad.prcm_block_offset = 0;
scratchpad.sdrc_block_offset = 0;
memcpy_toio(OMAP2_IO_ADDRESS(OMAP343X_SCRATCHPAD), &scratchpad, sizeof(scratchpad));
boot_config.magic = OMAP3_BOOT_MAGIC;
boot_config.size = 0xC;
boot_config.ch_mask = 0;
boot_config.devices[0] = devices[0];
boot_config.devices[1] = devices[1];
boot_config.devices[2] = devices[2];
boot_config.devices[3] = devices[3];
memcpy_toio(OMAP2_IO_ADDRESS(OMAP343X_SCRATCHPAD) + 0xAC, &boot_config, sizeof(boot_config));
#define GLOBAL_REG_PRM 0x48307200
__raw_writel(0x04, OMAP2_IO_ADDRESS(GLOBAL_REG_PRM) + 0x50);
}
else
WARN_ON(1);
}
static void __init omap2_gp_timer_init(void)
{
#ifdef CONFIG_LOCAL_TIMERS
twd_base = OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE);
#endif
omap_dm_timer_init();
omap2_gp_clockevent_init();
omap2_gp_clocksource_init();
}
static void ssi_set_mode(struct platform_device *pdev, u32 mode)
{
struct hsi_platform_data *pdata = pdev->dev.platform_data;
void __iomem *base = OMAP2_IO_ADDRESS(pdev->resource[0].start);
int port;
for (port = 1; port <= pdata->num_ports; port++) {
outl(mode, (unsigned int) base + HSI_HST_MODE_REG(port));
outl(mode, (unsigned int) base + HSI_HSR_MODE_REG(port));
}
}
static void hsi_restore_mode(struct platform_device *pdev)
{
struct hsi_platform_data *pdata = pdev->dev.platform_data;
void __iomem *base = OMAP2_IO_ADDRESS(pdev->resource[0].start);
struct port_ctx *p;
int port;
for (port = 1; port <= pdata->num_ports; port++) {
p = &pdata->ctx.pctx[port - 1];
hsi_outl(p->hst.mode, base + HSI_HST_MODE_REG(port));
hsi_outl(p->hsr.mode, base + HSI_HSR_MODE_REG(port));
}
}
static void hsi_set_mode(struct platform_device *pdev, u32 mode)
{
struct hsi_platform_data *pdata = pdev->dev.platform_data;
void __iomem *base = OMAP2_IO_ADDRESS(pdev->resource[0].start);
int port;
for (port = 1; port <= pdata->num_ports; port++) {
/* FIXME - to update: need read/modify/write or something else:
* this register now also contains flow and wake ctrl
*/
hsi_outl(mode, base + HSI_HST_MODE_REG(port));
hsi_outl(mode, base + HSI_HSR_MODE_REG(port));
}
}
/*
* Clears the scratchpad contents in case of cold boot-
* called during bootup
*/
void omap3_clear_scratchpad_contents(void)
{
u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
u32 *v_addr;
u32 offset = 0;
v_addr = OMAP2_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
OMAP3430_GLOBAL_COLD_RST) {
for ( ; offset <= max_offset; offset += 0x4)
__raw_writel(0x0, (v_addr + offset));
prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD,
OMAP3_PRM_RSTST_OFFSET);
}
}
/*
* FIXME: TO BE REMOVED.
* This hack allows us to ensure that clocks are stable before accehsing
* HSI controller registers. To be removed when PM functionalty is in place.
*/
static int check_hsi_active(void)
{
u32 reg;
unsigned long dl = jiffies + msecs_to_jiffies(500);
void __iomem *cm_idlest1 = OMAP2_IO_ADDRESS(0x48004a20);
reg = inl(cm_idlest1);
while ((!(reg & 0x01)) && (time_before(jiffies, dl)))
reg = inl(cm_idlest1);
if (!(reg & 0x01)) { /* HST */
pr_err("HSI is still in STANDBY ! (BUG !?)\n");
return -1;
}
return 0;
}
void __cpuinit platform_secondary_init(unsigned int cpu)
{
trace_hardirqs_off();
/*
* If any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
void omap3_scratchpad_dpll4autoidle(int enable)
{
void * __iomem scratchpad_address;
struct omap3_scratchpad_prcm_block prcm_block_contents;
scratchpad_address = OMAP2_IO_ADDRESS(OMAP343X_SCRATCHPAD);
memcpy_fromio(&prcm_block_contents, scratchpad_address + 0x2C,
sizeof(prcm_block_contents));
if (enable)
prcm_block_contents.cm_autoidle_pll |=
(1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT);
else
prcm_block_contents.cm_autoidle_pll &=
~OMAP3430_AUTO_PERIPH_DPLL_MASK;
memcpy_toio(scratchpad_address + 0x2C, &prcm_block_contents,
sizeof(prcm_block_contents));
}
static void __init gic_init_irq(void)
{
gic_dist_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29);
gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
}
/* Populate the scratchpad structure with restore structure */
void omap3_save_scratchpad_contents(void)
{
void * __iomem scratchpad_address;
u32 arm_context_addr;
struct omap3_scratchpad scratchpad_contents;
struct omap3_scratchpad_prcm_block prcm_block_contents;
struct omap3_scratchpad_sdrc_block sdrc_block_contents;
/* Populate the Scratchpad contents */
scratchpad_contents.boot_config_ptr = 0x0;
if (omap_rev() != OMAP3430_REV_ES3_0 &&
omap_rev() != OMAP3430_REV_ES3_1)
scratchpad_contents.public_restore_ptr =
virt_to_phys(get_restore_pointer());
else
scratchpad_contents.public_restore_ptr =
virt_to_phys(get_es3_restore_pointer());
if (omap_type() == OMAP2_DEVICE_TYPE_GP)
scratchpad_contents.secure_ram_restore_ptr = 0x0;
else
scratchpad_contents.secure_ram_restore_ptr =
(u32) __pa(omap3_secure_ram_storage);
scratchpad_contents.sdrc_module_semaphore = 0x0;
scratchpad_contents.prcm_block_offset = 0x2C;
scratchpad_contents.sdrc_block_offset = 0x64;
/* Populate the PRCM block contents */
prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
OMAP3_PRM_CLKSEL_OFFSET);
prcm_block_contents.cm_clksel_core =
cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
prcm_block_contents.cm_clksel_wkup =
cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
prcm_block_contents.cm_clken_pll =
cm_read_mod_reg(PLL_MOD, CM_CLKEN);
prcm_block_contents.cm_autoidle_pll =
cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
prcm_block_contents.cm_clksel1_pll =
cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
prcm_block_contents.cm_clksel2_pll =
cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
prcm_block_contents.cm_clksel3_pll =
cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
prcm_block_contents.cm_clken_pll_mpu =
cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
prcm_block_contents.cm_autoidle_pll_mpu =
cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
prcm_block_contents.cm_clksel1_pll_mpu =
cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
prcm_block_contents.cm_clksel2_pll_mpu =
cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
prcm_block_contents.prcm_block_size = 0x0;
/* Populate the SDRC block contents */
sdrc_block_contents.sysconfig =
(sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
sdrc_block_contents.cs_cfg =
(sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
sdrc_block_contents.sharing =
(sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
sdrc_block_contents.err_type =
(sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
sdrc_block_contents.dll_b_ctrl = 0x0;
sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
~(SDRC_POWER_AUTOCOUNT_MASK|SDRC_POWER_CLKCTRL_MASK)) |
(1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
SDRC_SELF_REFRESH_ON_AUTOCOUNT;
sdrc_block_contents.cs_0 = 0x0;
sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
sdrc_block_contents.emr_1_0 = 0x0;
sdrc_block_contents.emr_2_0 = 0x0;
sdrc_block_contents.emr_3_0 = 0x0;
sdrc_block_contents.actim_ctrla_0 =
sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
sdrc_block_contents.actim_ctrlb_0 =
sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
sdrc_block_contents.rfr_ctrl_0 =
sdrc_read_reg(SDRC_RFR_CTRL_0);
sdrc_block_contents.cs_1 = 0x0;
sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
sdrc_block_contents.emr_1_1 = 0x0;
sdrc_block_contents.emr_2_1 = 0x0;
sdrc_block_contents.emr_3_1 = 0x0;
sdrc_block_contents.actim_ctrla_1 =
sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
sdrc_block_contents.actim_ctrlb_1 =
sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
sdrc_block_contents.rfr_ctrl_1 =
sdrc_read_reg(SDRC_RFR_CTRL_1);
sdrc_block_contents.dcdl_1_ctrl = 0x0;
sdrc_block_contents.dcdl_2_ctrl = 0x0;
sdrc_block_contents.flags = 0x0;
sdrc_block_contents.block_size = 0x0;
arm_context_addr = virt_to_phys(omap3_arm_context);
/* Copy all the contents to the scratchpad location */
scratchpad_address = OMAP2_IO_ADDRESS(OMAP343X_SCRATCHPAD);
memcpy_toio(scratchpad_address, &scratchpad_contents,
sizeof(scratchpad_contents));
/* Scratchpad contents being 32 bits, a divide by 4 done here */
memcpy_toio(scratchpad_address +
scratchpad_contents.prcm_block_offset,
&prcm_block_contents, sizeof(prcm_block_contents));
memcpy_toio(scratchpad_address +
scratchpad_contents.sdrc_block_offset,
&sdrc_block_contents, sizeof(sdrc_block_contents));
/*
* Copies the address of the location in SDRAM where ARM
* registers get saved during a MPU OFF transition.
*/
memcpy_toio(scratchpad_address +
scratchpad_contents.sdrc_block_offset +
sizeof(sdrc_block_contents), &arm_context_addr, 4);
}
static int hci_h4p_probe(struct platform_device *pdev)
{
struct omap_bluetooth_config *bt_config;
struct hci_h4p_info *info;
int irq, err;
dev_info(&pdev->dev, "Registering HCI H4P device\n");
info = kzalloc(sizeof(struct hci_h4p_info), GFP_KERNEL);
if (!info)
return -ENOMEM;
info->dev = &pdev->dev;
info->pm_enabled = 0;
info->tx_enabled = 1;
info->rx_enabled = 1;
info->garbage_bytes = 0;
info->tx_clocks_en = 0;
info->rx_clocks_en = 0;
irq = 0;
spin_lock_init(&info->lock);
spin_lock_init(&info->clocks_lock);
skb_queue_head_init(&info->txq);
if (pdev->dev.platform_data == NULL) {
dev_err(&pdev->dev, "Could not get Bluetooth config data\n");
kfree(info);
return -ENODATA;
}
bt_config = pdev->dev.platform_data;
info->chip_type = bt_config->chip_type;
info->bt_wakeup_gpio = bt_config->bt_wakeup_gpio;
info->host_wakeup_gpio = bt_config->host_wakeup_gpio;
info->reset_gpio = bt_config->reset_gpio;
info->bt_sysclk = bt_config->bt_sysclk;
NBT_DBG("RESET gpio: %d\n", info->reset_gpio);
NBT_DBG("BTWU gpio: %d\n", info->bt_wakeup_gpio);
NBT_DBG("HOSTWU gpio: %d\n", info->host_wakeup_gpio);
NBT_DBG("Uart: %d\n", bt_config->bt_uart);
NBT_DBG("sysclk: %d\n", info->bt_sysclk);
err = gpio_request(info->reset_gpio, "bt_reset");
if (err < 0) {
dev_err(&pdev->dev, "Cannot get GPIO line %d\n",
info->reset_gpio);
goto cleanup_setup;
}
err = gpio_request(info->bt_wakeup_gpio, "bt_wakeup");
if (err < 0)
{
dev_err(info->dev, "Cannot get GPIO line 0x%d",
info->bt_wakeup_gpio);
gpio_free(info->reset_gpio);
goto cleanup_setup;
}
err = gpio_request(info->host_wakeup_gpio, "host_wakeup");
if (err < 0)
{
dev_err(info->dev, "Cannot get GPIO line %d",
info->host_wakeup_gpio);
gpio_free(info->reset_gpio);
gpio_free(info->bt_wakeup_gpio);
goto cleanup_setup;
}
gpio_direction_output(info->reset_gpio, 0);
gpio_direction_output(info->bt_wakeup_gpio, 0);
gpio_direction_input(info->host_wakeup_gpio);
switch (bt_config->bt_uart) {
case 1:
if (cpu_is_omap16xx()) {
irq = INT_UART1;
info->uart_fclk = clk_get(NULL, "uart1_ck");
} else if (cpu_is_omap24xx()) {
irq = INT_24XX_UART1_IRQ;
info->uart_iclk = clk_get(NULL, "uart1_ick");
info->uart_fclk = clk_get(NULL, "uart1_fck");
}
info->uart_base = OMAP2_IO_ADDRESS(OMAP_UART1_BASE);
break;
case 2:
if (cpu_is_omap16xx()) {
irq = INT_UART2;
info->uart_fclk = clk_get(NULL, "uart2_ck");
} else {
irq = INT_24XX_UART2_IRQ;
info->uart_iclk = clk_get(NULL, "uart2_ick");
info->uart_fclk = clk_get(NULL, "uart2_fck");
}
info->uart_base = OMAP2_IO_ADDRESS(OMAP_UART2_BASE);
break;
case 3:
if (cpu_is_omap16xx()) {
irq = INT_UART3;
info->uart_fclk = clk_get(NULL, "uart3_ck");
} else {
irq = INT_24XX_UART3_IRQ;
info->uart_iclk = clk_get(NULL, "uart3_ick");
info->uart_fclk = clk_get(NULL, "uart3_fck");
}
info->uart_base = OMAP2_IO_ADDRESS(OMAP_UART3_BASE);
break;
default:
dev_err(info->dev, "No uart defined\n");
goto cleanup;
}
info->irq = irq;
err = request_irq(irq, hci_h4p_interrupt, IRQF_DISABLED, "hci_h4p",
info);
if (err < 0) {
dev_err(info->dev, "hci_h4p: unable to get IRQ %d\n", irq);
goto cleanup;
}
err = request_irq(gpio_to_irq(info->host_wakeup_gpio),
hci_h4p_wakeup_interrupt, IRQF_TRIGGER_FALLING |
IRQF_TRIGGER_RISING | IRQF_DISABLED,
"hci_h4p_wkup", info);
if (err < 0) {
dev_err(info->dev, "hci_h4p: unable to get wakeup IRQ %d\n",
gpio_to_irq(info->host_wakeup_gpio));
free_irq(irq, info);
goto cleanup;
}
err = set_irq_wake(gpio_to_irq(info->host_wakeup_gpio), 1);
if (err < 0) {
dev_err(info->dev, "hci_h4p: unable to set wakeup for IRQ %d\n",
gpio_to_irq(info->host_wakeup_gpio));
free_irq(irq, info);
free_irq(gpio_to_irq(info->host_wakeup_gpio), info);
goto cleanup;
}
init_timer_deferrable(&info->lazy_release);
info->lazy_release.function = hci_h4p_lazy_clock_release;
info->lazy_release.data = (unsigned long)info;
hci_h4p_set_clk(info, &info->tx_clocks_en, 1);
err = hci_h4p_reset_uart(info);
if (err < 0)
goto cleanup_irq;
hci_h4p_init_uart(info);
hci_h4p_set_rts(info, 0);
err = hci_h4p_reset(info);
hci_h4p_reset_uart(info);
if (err < 0)
goto cleanup_irq;
gpio_set_value(info->reset_gpio, 0);
hci_h4p_set_clk(info, &info->tx_clocks_en, 0);
platform_set_drvdata(pdev, info);
if (hci_h4p_register_hdev(info) < 0) {
dev_err(info->dev, "failed to register hci_h4p hci device\n");
goto cleanup_irq;
}
return 0;
cleanup_irq:
free_irq(irq, (void *)info);
free_irq(gpio_to_irq(info->host_wakeup_gpio), info);
cleanup:
gpio_set_value(info->reset_gpio, 0);
gpio_free(info->reset_gpio);
gpio_free(info->bt_wakeup_gpio);
gpio_free(info->host_wakeup_gpio);
cleanup_setup:
kfree(info);
return err;
}
static void __init __omap2_set_globals(void)
{
omap2_set_globals_tap(omap2_globals);
omap2_set_globals_memory(omap2_globals);
omap2_set_globals_control(omap2_globals);
omap2_set_globals_prcm(omap2_globals);
}
#endif
#if defined(CONFIG_ARCH_OMAP2420)
static struct omap_globals omap242x_globals = {
.class = OMAP242X_CLASS,
.tap = OMAP2_IO_ADDRESS(0x48014000),
.sdrc = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
.sms = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
.ctrl = OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
.prm = OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
.cm = OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
};
void __init omap2_set_globals_242x(void)
{
omap2_globals = &omap242x_globals;
__omap2_set_globals();
}
#endif
#if defined(CONFIG_ARCH_OMAP2430)
SR_CLKACTIVITY_IOFF_FOFF);
clk_disable(sr->clk);
sr->is_sr_reset = 1;
}
static struct omap_sr sr1 = {
.srid = SR1,
.is_sr_reset = 1,
#ifdef CONFIG_OMAP_SMARTREFLEX_CLASS1P5
.is_autocomp_active = 1,
#else
.is_autocomp_active = 0,
#endif
.clk_length = 0,
.srbase_addr = OMAP2_IO_ADDRESS(OMAP34XX_SR1_BASE),
};
static struct omap_sr sr2 = {
.srid = SR2,
.is_sr_reset = 1,
#ifdef CONFIG_OMAP_SMARTREFLEX_CLASS1P5
.is_autocomp_active = 1,
#else
.is_autocomp_active = 0,
#endif
.clk_length = 0,
.srbase_addr = OMAP2_IO_ADDRESS(OMAP34XX_SR2_BASE),
};
static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
