static void test_init(void)
{
OpenEthState *s = OPEN_ETH_STATE(nc);
assert(0 == open_eth_reg_read(s, open_eth_reg(MODER)));
assert(0 == open_eth_reg_read(s, open_eth_reg(IPGT)));
assert(0 == open_eth_reg_read(s, open_eth_reg(IPGR1)));
assert(0 == open_eth_reg_read(s, open_eth_reg(IPGR2)));
assert(0 == open_eth_reg_read(s, open_eth_reg(PACKETLEN)));
assert(0 == open_eth_reg_read(s, open_eth_reg(COLLCONF)));
assert(0 == open_eth_reg_read(s, open_eth_reg(TX_BD_NUM)));
assert(0 == open_eth_reg_read(s, open_eth_reg(MIIMODER)));
/* reset MAC and MII */
open_eth_reg_write(s, open_eth_reg(MODER), MODER_RST);
assert(MODER_RST == open_eth_reg_read(s, open_eth_reg(MODER)));
assert(0x12 == open_eth_reg_read(s, open_eth_reg(IPGT)));
assert(0xc == open_eth_reg_read(s, open_eth_reg(IPGR1)));
assert(0x12 == open_eth_reg_read(s, open_eth_reg(IPGR2)));
assert(0x400600 == open_eth_reg_read(s, open_eth_reg(PACKETLEN)));
assert(0xf003f == open_eth_reg_read(s, open_eth_reg(COLLCONF)));
assert(__OPENETH_DESC_SIZE__/2 == open_eth_reg_read(s, open_eth_reg(TX_BD_NUM)));
assert(0x64 == open_eth_reg_read(s, open_eth_reg(MIIMODER)));
}
static void test_rx_busy(void)
{
const uint64_t tx_bd_num = __OPENETH_DESC_SIZE__-1;
uint64_t desc;
hwaddr desc_addr;
const uint8_t tx_packet[] = { /* recipient addr */
0x12U, 0x34U, 0x56U,
0x78U, 0x9AU, 0xBCU,
/* data */
0x20U, 0x21U, 0x22U,
0x30U, 0x31U, 0x32U,
0x40U, 0x41U, 0x42U,
0x50U, 0x51U, 0x52U
};
/* setup rx DMA buffer */
uint8_t rx_packet[sizeof(tx_packet)];
memset(rx_packet, 0, sizeof(rx_packet));
OpenEthState *s = OPEN_ETH_STATE(nc);
/* reset MAC and MII */
open_eth_reg_write(s, open_eth_reg(MODER), MODER_RST);
/* allocate only one RX buffer descriptor */
open_eth_reg_write(s, open_eth_reg(TX_BD_NUM), tx_bd_num);
/* setup MAC address */
open_eth_reg_write(s, open_eth_reg(MAC_ADDR0), 0x56789ABC);
open_eth_reg_write(s, open_eth_reg(MAC_ADDR1), 0x1234);
/* enable IRQ for incoming packets */
open_eth_reg_write(s, open_eth_reg(INT_MASK), INT_MASK_RXF_M);
/* setup address map to allow 32 bit hardware addresses */
cpu_physical_memory_init((uintptr_t) rx_packet);
/* calculate lowest rx buffer descriptor address */
desc_addr = tx_bd_num * 8;
/* setup rx buffer descriptor for DMA on rx_packet */
desc = (uint32_t) (uintptr_t) rx_packet;
desc <<= 32;
desc |= RXD_E | RXD_IRQ;
open_eth_desc_write(s, desc_addr, desc);
/* enable receiver and unmask BUSY interrupt */
open_eth_reg_write(s, open_eth_reg(MODER), MODER_RXEN);
/* trigger DMA operations */
open_eth_receive(s, tx_packet, sizeof(tx_packet));
assert((open_eth_reg_read(s, open_eth_reg(INT_SOURCE)) & INT_SOURCE_BUSY) == 0);
open_eth_receive(s, tx_packet, sizeof(tx_packet));
assert((open_eth_reg_read(s, open_eth_reg(INT_SOURCE)) & INT_SOURCE_BUSY) == INT_SOURCE_BUSY);
}
static void test_can_receive(void)
{
const uint64_t tx_bd_num = _ETHOC_DESC_SIZE_/2;
uint64_t desc;
hwaddr desc_addr;
/* setup rx DMA buffer */
uint8_t rx_packet[2];
memset(rx_packet, 0, sizeof(rx_packet));
OpenEthState *s = OPEN_ETH_STATE(nc);
/* reset MAC and MII */
open_eth_reg_write(s, open_eth_reg(MODER), MODER_RST);
assert(tx_bd_num == open_eth_reg_read(s, open_eth_reg(TX_BD_NUM)));
assert(tx_bd_num == s->regs[TX_BD_NUM]);
/* setup MAC address */
open_eth_reg_write(s, open_eth_reg(MAC_ADDR0), 0x56789ABC);
open_eth_reg_write(s, open_eth_reg(MAC_ADDR1), 0x1234);
/* enable IRQ for incoming packets */
open_eth_reg_write(s, open_eth_reg(INT_MASK), INT_MASK_RXF_M);
/* calculate lowest rx buffer descriptor address */
desc_addr = tx_bd_num * 8;
/* setup rx buffer descriptor for DMA on rx_packet */
desc = (uint32_t) (uintptr_t) rx_packet;
desc <<= 32;
desc |= RXD_E | RXD_IRQ;
open_eth_desc_write(s, desc_addr, desc);
assert(s->desc[tx_bd_num].len_flags & (RXD_E | RXD_IRQ));
/* enable receiver and unmask BUSY interrupt */
open_eth_reg_write(s, open_eth_reg(MODER), MODER_RXEN);
assert(tx_bd_num == s->regs[TX_BD_NUM]);
assert(s->rx_desc == s->regs[TX_BD_NUM]);
assert(s->desc[tx_bd_num].len_flags & (RXD_E | RXD_IRQ));
assert(open_eth_can_receive(s));
}
static void test_rx(void)
{
const uint64_t tx_bd_num = __OPENETH_DESC_SIZE__/2;
uint64_t desc;
hwaddr desc_addr;
const uint8_t tx_packet[] = { /* recipient addr */
0x12U, 0x34U, 0x56U,
0x78U, 0x9AU, 0xBCU,
/* data */
0x20U, 0x21U, 0x22U,
0x30U, 0x31U, 0x32U,
0x40U, 0x41U, 0x42U,
0x50U, 0x51U, 0x52U
};
/* setup rx DMA buffer */
uint8_t rx_packet[sizeof(tx_packet)];
memset(rx_packet, 0, sizeof(rx_packet));
OpenEthState *s = OPEN_ETH_STATE(nc);
/* reset MAC and MII */
open_eth_reg_write(s, open_eth_reg(MODER), MODER_RST);
assert(tx_bd_num == open_eth_reg_read(s, open_eth_reg(TX_BD_NUM)));
/* setup MAC address */
open_eth_reg_write(s, open_eth_reg(MAC_ADDR0), 0x56789ABC);
open_eth_reg_write(s, open_eth_reg(MAC_ADDR1), 0x1234);
/* enable IRQ for incoming packets */
open_eth_reg_write(s, open_eth_reg(INT_MASK), INT_MASK_RXF_M);
/* setup address map to allow 32 bit hardware addresses */
cpu_physical_memory_init((uintptr_t) rx_packet);
/* calculate lowest rx buffer descriptor address */
desc_addr = tx_bd_num * 8;
/* setup rx buffer descriptor for DMA on rx_packet */
desc = (uint32_t) (uintptr_t) rx_packet;
desc <<= 32;
desc |= RXD_E | RXD_IRQ;
open_eth_desc_write(s, desc_addr, desc);
/* enable receiver */
open_eth_reg_write(s, open_eth_reg(MODER), MODER_RXEN);
/* trigger DMA operation and IRQ */
raised_irq = false;
open_eth_receive(s, tx_packet, sizeof(tx_packet));
/* validate DMA buffer content and IRQ */
assert(sizeof(tx_packet) == sizeof(rx_packet));
#if 0
assert((uint8_t*)(s->desc[tx_bd_num].buf_ptr)==rx_packet);
assert(rx_packet[0]==0x12);
assert(memcmp(tx_packet, rx_packet, sizeof(tx_packet)) == 0);
#endif
assert((open_eth_reg_read(s, open_eth_reg(INT_SOURCE)) & INT_SOURCE_BUSY) == 0);
assert(raised_irq == true);
}
static void nc_open_eth_set_link_status(NetClientState *nc)
{
OpenEthState *s = OPEN_ETH_STATE(nc);
open_eth_set_link_status(s, s->nic->nc.link_down);
}
static ssize_t nc_open_eth_receive(NetClientState *nc,
const uint8_t *buf, size_t size)
{
return open_eth_receive(OPEN_ETH_STATE(nc), buf, size);
}
static int nc_open_eth_can_receive(NetClientState *nc)
{
return open_eth_can_receive(OPEN_ETH_STATE(nc));
}
static void test_rx(void)
{
const uint64_t tx_bd_num = _ETHOC_DESC_SIZE_/2;
uint64_t desc;
hwaddr desc_addr;
const uint8_t tx_packet[] = { /* recipient addr */
0x12U, 0x34U, 0x56U,
0x78U, 0x9AU, 0xBCU,
/* data */
0x20U, 0x21U, 0x22U,
0x30U, 0x31U, 0x32U,
0x40U, 0x41U, 0x42U,
0x50U, 0x51U, 0x52U };
/* setup rx DMA buffer */
uint8_t rx_packet[sizeof(tx_packet)];
memset(rx_packet, 0, sizeof(rx_packet));
OpenEthState *s = OPEN_ETH_STATE(nc);
/* reset MAC and MII */
open_eth_reg_write(s, open_eth_reg(MODER), MODER_RST);
assert(tx_bd_num == open_eth_reg_read(s, open_eth_reg(TX_BD_NUM)));
/* setup MAC address */
open_eth_reg_write(s, open_eth_reg(MAC_ADDR0), 0x56789ABC);
open_eth_reg_write(s, open_eth_reg(MAC_ADDR1), 0x1234);
/* enable IRQ for incoming packets */
open_eth_reg_write(s, open_eth_reg(INT_MASK), INT_MASK_RXF_M);
/* calculate lowest rx buffer descriptor address */
desc_addr = tx_bd_num * 8;
/* setup rx buffer descriptor for DMA on rx_packet */
desc = (uint32_t) (uintptr_t) rx_packet;
desc <<= 32;
desc |= RXD_E | RXD_IRQ;
open_eth_desc_write(s, desc_addr, desc);
/* enable receiver */
open_eth_reg_write(s, open_eth_reg(MODER), MODER_RXEN);
/* trigger DMA operation and IRQ */
raised_irq = false;
open_eth_receive(s, tx_packet, sizeof(tx_packet));
/* validate DMA buffer content and IRQ */
assert(sizeof(tx_packet) == sizeof(rx_packet));
assert((open_eth_reg_read(s, open_eth_reg(INT_SOURCE)) & INT_SOURCE_BUSY) == 0);
#ifdef _ETHOC_TEST_3_
/*
* Expected to fail when interrupts are asynchronously fired
*/
assert(raised_irq);
#endif
#ifdef _ETHOC_TEST_5_
/* wait for all pending interrupts to complete */
#ifdef _CBMC_
__CPROVER_assume(s->irq->threads_counter == 0);
#else
for (unsigned i = 0; i < _ETHOC_DESC_SIZE_; ++i)
pthread_join(s->irq->threads[i], NULL);
#endif
/*
* assertion always holds because we let all interrupts run to completion
*/
assert(raised_irq);
#endif
}
