/* init_ops write command */ static enum _ecore_status_t ecore_init_cmd_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, struct init_write_op *p_cmd, bool b_can_dmae) { enum _ecore_status_t rc = ECORE_SUCCESS; bool b_must_dmae; u32 addr, data; data = OSAL_LE32_TO_CPU(p_cmd->data); b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS); addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2; /* Sanitize */ if (b_must_dmae && !b_can_dmae) { DP_NOTICE(p_hwfn, true, "Need to write to %08x for Wide-bus but DMAE isn't" " allowed\n", addr); return ECORE_INVAL; } switch (GET_FIELD(data, INIT_WRITE_OP_SOURCE)) { case INIT_SRC_INLINE: data = OSAL_LE32_TO_CPU(p_cmd->args.inline_val); ecore_wr(p_hwfn, p_ptt, addr, data); break; case INIT_SRC_ZEROS: data = OSAL_LE32_TO_CPU(p_cmd->args.zeros_count); if (b_must_dmae || (b_can_dmae && (data >= 64))) rc = ecore_init_fill_dmae(p_hwfn, p_ptt, addr, 0, data); else ecore_init_fill(p_hwfn, p_ptt, addr, 0, data); break; case INIT_SRC_ARRAY: rc = ecore_init_cmd_array(p_hwfn, p_ptt, p_cmd, b_must_dmae, b_can_dmae); break; case INIT_SRC_RUNTIME: ecore_init_rt(p_hwfn, p_ptt, addr, OSAL_LE16_TO_CPU(p_cmd->args.runtime.offset), OSAL_LE16_TO_CPU(p_cmd->args.runtime.size), b_must_dmae); break; } return rc; }
static u32 ecore_init_cmd_mode(struct ecore_hwfn *p_hwfn, struct init_if_mode_op *p_cmd, int modes) { u16 offset = OSAL_LE16_TO_CPU(p_cmd->modes_buf_offset); if (ecore_init_cmd_mode_match(p_hwfn, &offset, modes)) return 0; else return GET_FIELD(OSAL_LE32_TO_CPU(p_cmd->op_data), INIT_IF_MODE_OP_CMD_OFFSET); }