static PVRSRV_ERROR PCIInitDev(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
IMG_UINT32 ui32MaxOffset = POULSBO_MAX_OFFSET;
#if defined(SUPPORT_DRI_DRM_EXT)
psSysSpecData->hSGXPCI = OSPCISetDev((IMG_VOID *)psSysSpecData->psPCIDev, 0);
ui32MaxOffset = POULSBO_MAX_OFFSET;
#else
#if defined(LDM_PCI) || defined(SUPPORT_DRI_DRM)
psSysSpecData->hSGXPCI = OSPCISetDev((IMG_VOID *)psSysSpecData->psPCIDev, HOST_PCI_INIT_FLAG_BUS_MASTER | HOST_PCI_INIT_FLAG_MSI);
#else
psSysSpecData->hSGXPCI = OSPCIAcquireDev(SYS_SGX_DEV_VENDOR_ID, SYS_SGX_DEV_DEVICE_ID, HOST_PCI_INIT_FLAG_BUS_MASTER | HOST_PCI_INIT_FLAG_MSI);
#endif
#endif
if (!psSysSpecData->hSGXPCI)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Failed to acquire PCI device"));
return PVRSRV_ERROR_PCI_DEVICE_NOT_FOUND;
}
SYS_SPECIFIC_DATA_SET(psSysSpecData, SYS_SPECIFIC_DATA_PCI_ACQUIRE_DEV);
PVR_TRACE(("PCI memory region: %x to %x", OSPCIAddrRangeStart(psSysSpecData->hSGXPCI, POULSBO_ADDR_RANGE_INDEX), OSPCIAddrRangeEnd(psSysSpecData->hSGXPCI, POULSBO_ADDR_RANGE_INDEX)));
#if defined(SGX_FEATURE_HOST_PORT)
PVR_TRACE(("Host Port region: %x to %x", OSPCIAddrRangeStart(psSysSpecData->hSGXPCI, POULSBO_HP_ADDR_RANGE_INDEX), OSPCIAddrRangeEnd(psSysSpecData->hSGXPCI, POULSBO_HP_ADDR_RANGE_INDEX)));
#endif
if (OSPCIAddrRangeLen(psSysSpecData->hSGXPCI, POULSBO_ADDR_RANGE_INDEX) < ui32MaxOffset)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region isn't big enough"));
return PVRSRV_ERROR_PCI_REGION_TOO_SMALL;
}
if (OSPCIRequestAddrRange(psSysSpecData->hSGXPCI, POULSBO_ADDR_RANGE_INDEX) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region not available"));
return PVRSRV_ERROR_PCI_REGION_UNAVAILABLE;
}
SYS_SPECIFIC_DATA_SET(psSysSpecData, SYS_SPECIFIC_DATA_PCI_REQUEST_SGX_ADDR_RANGE);
#if defined(SGX_FEATURE_HOST_PORT)
if (OSPCIRequestAddrRange(psSysSpecData->hSGXPCI, POULSBO_HP_ADDR_RANGE_INDEX) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Host Port region not available"));
return PVRSRV_ERROR_PCI_REGION_UNAVAILABLE;
}
SYS_SPECIFIC_DATA_SET(psSysSpecData, SYS_SPECIFIC_DATA_PCI_REQUEST_HOST_PORT_RANGE);
#endif
return PVRSRV_OK;
}
/*
PCIInitDev
*/
static PVRSRV_ERROR PCIInitDev(PLAT_DATA *psPlatData)
{
PVRSRV_DEVICE_CONFIG *psDevice = &sSysConfig.pasDevices[0];
PVRSRV_ERROR eError;
#if defined (LMA)
IMG_UINT32 uiLMACpuPAddr;
IMG_UINT32 uiLMASize;
#endif
psPlatData->hRGXPCI = OSPCIAcquireDev(SYS_RGX_DEV_VENDOR_ID,
SYS_RGX_DEV_DEVICE_ID,
HOST_PCI_INIT_FLAG_BUS_MASTER | HOST_PCI_INIT_FLAG_MSI);
if (!psPlatData->hRGXPCI)
{
psPlatData->hRGXPCI = OSPCIAcquireDev(SYS_RGX_DEV_VENDOR_ID,
SYS_RGX_DEV1_DEVICE_ID,
HOST_PCI_INIT_FLAG_BUS_MASTER | HOST_PCI_INIT_FLAG_MSI);
}
if (!psPlatData->hRGXPCI)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Failed to acquire PCI device"));
eError = PVRSRV_ERROR_PCI_DEVICE_NOT_FOUND;
goto e0;
}
psPlatData->uiICRCpuPAddr = OSPCIAddrRangeStart(psPlatData->hRGXPCI, EMULATOR_RGX_ICR_PCI_BASENUM);
psPlatData->uiICRSize = OSPCIAddrRangeLen(psPlatData->hRGXPCI, EMULATOR_RGX_ICR_PCI_BASENUM);
/* Check the address range is large enough. */
if (psPlatData->uiICRSize < EMULATOR_RGX_ICR_PCI_REGION_SIZE)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region isn't big enough (Emu reg) (was 0x%08x, required 0x%08x)",
psPlatData->uiICRSize, EMULATOR_RGX_ICR_PCI_REGION_SIZE));
eError = PVRSRV_ERROR_PCI_REGION_TOO_SMALL;
goto e1;
}
/* Reserve the address range */
if (OSPCIRequestAddrRange(psPlatData->hRGXPCI, EMULATOR_RGX_ICR_PCI_BASENUM)
!= PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region not available (Emu reg)"));
eError = PVRSRV_ERROR_PCI_REGION_UNAVAILABLE;
goto e1;
}
psDevice->sRegsCpuPBase.uiAddr = OSPCIAddrRangeStart(psPlatData->hRGXPCI, EMULATOR_RGX_REG_PCI_BASENUM);
psDevice->ui32RegsSize = OSPCIAddrRangeLen(psPlatData->hRGXPCI, EMULATOR_RGX_REG_PCI_BASENUM);
/* Check the address range is large enough. */
if (psDevice->ui32RegsSize < EMULATOR_RGX_REG_SIZE)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region isn't big enough (RGX reg) (was 0x%08x, required 0x%08x)",
psDevice->ui32RegsSize, EMULATOR_RGX_REG_SIZE));
eError = PVRSRV_ERROR_PCI_REGION_TOO_SMALL;
goto e2;
}
/* Reserve the address range */
if (OSPCIRequestAddrRange(psPlatData->hRGXPCI, EMULATOR_RGX_REG_PCI_BASENUM) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region not available (RGX reg) "));
eError = PVRSRV_ERROR_PCI_REGION_UNAVAILABLE;
goto e2;
}
#if defined (LMA)
uiLMACpuPAddr = OSPCIAddrRangeStart(psPlatData->hRGXPCI, EMULATOR_RGX_MEM_PCI_BASENUM);
uiLMASize = OSPCIAddrRangeLen(psPlatData->hRGXPCI, EMULATOR_RGX_MEM_PCI_BASENUM);
/* Setup the RGX heap */
gsPhysHeapConfig[0].sStartAddr.uiAddr = uiLMACpuPAddr;
gsPhysHeapConfig[0].uiSize = uiLMASize - RESERVE_DC_MEM_SIZE;
/* Setup the DC heap */
gsPhysHeapConfig[1].sStartAddr.uiAddr = uiLMACpuPAddr + gsPhysHeapConfig[0].uiSize;
gsPhysHeapConfig[1].uiSize = RESERVE_DC_MEM_SIZE;
/* Check the address range is large enough. */
if (uiLMASize < EMULATOR_RGX_MEM_REGION_SIZE)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region isn't big enough (was 0x%08x, required 0x%08x)",
uiLMASize, EMULATOR_RGX_MEM_REGION_SIZE));
eError = PVRSRV_ERROR_PCI_REGION_TOO_SMALL;
goto e3;
}
/* Reserve the address range */
if (OSPCIRequestAddrRange(psPlatData->hRGXPCI, EMULATOR_RGX_MEM_PCI_BASENUM) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region not available"));
eError = PVRSRV_ERROR_PCI_REGION_UNAVAILABLE;
goto e3;
}
#endif
if (OSPCIIRQ(psPlatData->hRGXPCI, &psDevice->ui32IRQ) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Couldn't get IRQ"));
eError = PVRSRV_ERROR_INVALID_DEVICE;
goto e4;
}
#if defined (LMA)
/* Save this info for later use */
psPlatData->uiLMACpuPAddr = uiLMACpuPAddr;
psPlatData->uiLMASize = uiLMASize;
#endif
/*
Reset the emulator design
*/
eError = EmuReset(psDevice->sRegsCpuPBase);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Couldn't reset emulator"));
goto e4;
}
/*
Init IRC IRQ_CTRL register
*/
Init_IRQ_CTRL(psPlatData);
return PVRSRV_OK;
e4:
#if defined (LMA)
OSPCIReleaseAddrRange(psPlatData->hRGXPCI, EMULATOR_RGX_MEM_PCI_BASENUM);
e3:
#endif
OSPCIReleaseAddrRange(psPlatData->hRGXPCI, EMULATOR_RGX_REG_PCI_BASENUM);
e2:
OSPCIReleaseAddrRange(psPlatData->hRGXPCI, EMULATOR_RGX_ICR_PCI_BASENUM);
e1:
OSPCIReleaseDev(psPlatData->hRGXPCI);
e0:
return eError;
}
/*!
******************************************************************************
@Function PCIInitDev
@Description
Initialise the PCI device for subsequent use.
@Input psSysData : System data
@Return PVRSRV_ERROR
******************************************************************************/
static PVRSRV_ERROR PCIInitDev(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
#if defined(LDM_PCI) || defined(SUPPORT_DRI_DRM)
psSysSpecData->hSGXPCI = OSPCISetDev((IMG_VOID *)psSysSpecData->psPCIDev, HOST_PCI_INIT_FLAG_BUS_MASTER);
#else
/* Old Test chip ID and Emulator board */
psSysSpecData->hSGXPCI = OSPCIAcquireDev(SYS_SGX_DEV_VENDOR_ID, SYS_SGX_DEV_DEVICE_ID, HOST_PCI_INIT_FLAG_BUS_MASTER);
#if defined (SYS_SGX_DEV1_DEVICE_ID)
if (!psSysSpecData->hSGXPCI)
{
PVR_TRACE(("PCIInitDev: Trying alternative PCI device ID"));
psSysSpecData->hSGXPCI = OSPCIAcquireDev(SYS_SGX_DEV_VENDOR_ID, SYS_SGX_DEV1_DEVICE_ID, HOST_PCI_INIT_FLAG_BUS_MASTER);
}
#endif
#endif /* defined(LDM_PCI) || defined(SUPPORT_DRI_DRM) */
if (!psSysSpecData->hSGXPCI)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Failed to acquire PCI device"));
return PVRSRV_ERROR_PCI_DEVICE_NOT_FOUND;
}
SYS_SPECIFIC_DATA_SET(psSysSpecData, SYS_SPECIFIC_DATA_ENABLE_PCI_DEV);
PVR_TRACE(("Atlas Reg PCI memory region: %x to %x", OSPCIAddrRangeStart(psSysSpecData->hSGXPCI, SYS_ATLAS_REG_PCI_BASENUM), OSPCIAddrRangeEnd(psSysSpecData->hSGXPCI, SYS_ATLAS_REG_PCI_BASENUM)));
/* Check the address range is large enough. */
if (OSPCIAddrRangeLen(psSysSpecData->hSGXPCI, SYS_ATLAS_REG_PCI_BASENUM) < SYS_ATLAS_REG_REGION_SIZE)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region isn't big enough (atlas reg)"));
return PVRSRV_ERROR_PCI_REGION_TOO_SMALL;
}
/* Reserve the address range */
if (OSPCIRequestAddrRange(psSysSpecData->hSGXPCI, SYS_ATLAS_REG_PCI_BASENUM) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region not available (atlas reg)"));
return PVRSRV_ERROR_PCI_REGION_UNAVAILABLE;
}
SYS_SPECIFIC_DATA_SET(psSysSpecData, SYS_SPECIFIC_DATA_ENABLE_PCI_ATL);
PVR_TRACE(("SGX Reg/SP PCI memory region: %x to %x", OSPCIAddrRangeStart(psSysSpecData->hSGXPCI, SYS_SGX_REG_PCI_BASENUM), OSPCIAddrRangeEnd(psSysSpecData->hSGXPCI, SYS_SGX_REG_PCI_BASENUM)));
/* Check the address range is large enough. */
if (OSPCIAddrRangeLen(psSysSpecData->hSGXPCI, SYS_SGX_REG_PCI_BASENUM) < SYS_SGX_REG_SIZE)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region isn't big enough (SGX reg)"));
return PVRSRV_ERROR_PCI_REGION_TOO_SMALL;
}
/* Reserve the address range */
if (OSPCIRequestAddrRange(psSysSpecData->hSGXPCI, SYS_SGX_REG_PCI_BASENUM) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region not available (SGX reg) "));
return PVRSRV_ERROR_PCI_REGION_UNAVAILABLE;
}
SYS_SPECIFIC_DATA_SET(psSysSpecData, SYS_SPECIFIC_DATA_ENABLE_PCI_REG);
PVR_TRACE(("SGX Mem PCI memory region: %x to %x", OSPCIAddrRangeStart(psSysSpecData->hSGXPCI, SYS_SGX_MEM_PCI_BASENUM), OSPCIAddrRangeEnd(psSysSpecData->hSGXPCI, SYS_SGX_MEM_PCI_BASENUM)));
/* Check the address range is large enough. */
if (OSPCIAddrRangeLen(psSysSpecData->hSGXPCI, SYS_SGX_MEM_PCI_BASENUM) < SYS_SGX_MEM_REGION_SIZE)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region isn't big enough"));
return PVRSRV_ERROR_PCI_REGION_TOO_SMALL;
}
/* Reserve the address range */
if (OSPCIRequestAddrRange(psSysSpecData->hSGXPCI, SYS_SGX_MEM_PCI_BASENUM) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region not available"));
return PVRSRV_ERROR_PCI_REGION_UNAVAILABLE;
}
SYS_SPECIFIC_DATA_SET(psSysSpecData, SYS_SPECIFIC_DATA_ENABLE_PCI_MEM);
return PVRSRV_OK;
}
/*
PCIInitDev
*/
static PVRSRV_ERROR PCIInitDev(PLAT_DATA *psPlatData)
{
PVRSRV_DEVICE_CONFIG *psDevice = &sSysConfig.pasDevices[0];
PVRSRV_ERROR eError;
IMG_UINT32 ui32MaxOffset;
IMG_UINT32 ui32BaseAddr = 0;
psPlatData->psDRMDev = gpsPVRDRMDev;
if (!psPlatData->psDRMDev)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: DRM device not initialized"));
return PVRSRV_ERROR_NOT_SUPPORTED;
}
if (!IS_MRFLD(psPlatData->psDRMDev))
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device 0x%08x not supported", psPlatData->psDRMDev->pci_device));
return PVRSRV_ERROR_NOT_SUPPORTED;
}
psPlatData->hRGXPCI = OSPCISetDev((IMG_VOID *)psPlatData->psDRMDev->pdev, 0);
if (!psPlatData->hRGXPCI)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Failed to acquire PCI device"));
return PVRSRV_ERROR_PCI_DEVICE_NOT_FOUND;
}
ui32MaxOffset = OSPCIAddrRangeLen(psPlatData->hRGXPCI, 0);
if (ui32MaxOffset < (RGX_REG_OFFSET + RGX_REG_SIZE))
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region 0x%08x isn't big enough", ui32MaxOffset));
return PVRSRV_ERROR_PCI_REGION_TOO_SMALL;
}
PVR_DPF((PVR_DBG_WARNING,"PCIInitDev: Device memory region len 0x%08x", ui32MaxOffset));
/* Reserve the address range */
if (OSPCIRequestAddrRange(psPlatData->hRGXPCI, 0) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region not available"));
return PVRSRV_ERROR_PCI_REGION_UNAVAILABLE;
}
ui32BaseAddr = OSPCIAddrRangeStart(psPlatData->hRGXPCI, 0);
if (OSPCIIRQ(psPlatData->hRGXPCI, &psDevice->ui32IRQ) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Couldn't get IRQ"));
eError = PVRSRV_ERROR_INVALID_DEVICE;
goto e4;
}
PVR_DPF((PVR_DBG_WARNING, "PCIInitDev: BaseAddr 0x%08x, EndAddr 0x%llx, IRQ %d",
ui32BaseAddr, OSPCIAddrRangeEnd(psPlatData->hRGXPCI, 0), psDevice->ui32IRQ));
psDevice->sRegsCpuPBase.uiAddr = ui32BaseAddr + RGX_REG_OFFSET;
psDevice->ui32RegsSize = RGX_REG_SIZE;
PVR_DPF((PVR_DBG_WARNING, "PCIInitDev: sRegsCpuPBase 0x%llx, size 0x%x",
psDevice->sRegsCpuPBase.uiAddr, psDevice->ui32RegsSize));
return PVRSRV_OK;
e4:
OSPCIReleaseAddrRange(psPlatData->hRGXPCI, 0);
OSPCIReleaseDev(psPlatData->hRGXPCI);
return eError;
}
