static IMG_VOID Init_IRQ_CTRL(PLAT_DATA *psPlatData)
{
IMG_CPU_PHYADDR sICRCpuPBase;
IMG_VOID *pvICRCpuVBase;
IMG_UINT32 ui32Value;
/* Map into CPU address space */
sICRCpuPBase.uiAddr = IMG_CAST_TO_CPUPHYADDR_UINT(psPlatData->uiICRCpuPAddr);
pvICRCpuVBase = OSMapPhysToLin(sICRCpuPBase,
psPlatData->uiICRSize,
0);
/* Configure IRQ_CTRL: For Rogue, enable IRQ, set sense to active low */
ui32Value = OSReadHWReg32(pvICRCpuVBase, EMULATOR_RGX_ICR_REG_IRQ_CTRL);
ui32Value &= ~EMULATOR_RGX_ICR_REG_IRQ_CTRL_IRQ_HINLO;
ui32Value |= EMULATOR_RGX_ICR_REG_IRQ_CTRL_IRQ_EN;
OSWriteHWReg32(pvICRCpuVBase,EMULATOR_RGX_ICR_REG_IRQ_CTRL, ui32Value);
/* Flush register write */
(void) OSReadHWReg32(pvICRCpuVBase, EMULATOR_RGX_ICR_REG_IRQ_CTRL);
OSWaitus(10);
PVR_TRACE(("Emulator FPGA image version (ICR_REG_CORE_REVISION): 0x%08x",
OSReadHWReg32(pvICRCpuVBase, EMULATOR_RGX_ICR_REG_CORE_REVISION)));
/* Unmap from CPU address space */
OSUnMapPhysToLin(pvICRCpuVBase, psPlatData->uiICRSize, 0);
}
/*!
******************************************************************************
@Function SysCreateVersionString
@Description Read the version string
@Return IMG_CHAR * : Version string
******************************************************************************/
static IMG_CHAR *SysCreateVersionString(void)
{
static IMG_CHAR aszVersionString[100];
SYS_DATA *psSysData;
IMG_UINT32 ui32SGXRevision;
IMG_INT32 i32Count;
#if !defined(NO_HARDWARE)
IMG_VOID *pvRegsLinAddr;
pvRegsLinAddr = OSMapPhysToLin(gsSGXDeviceMap.sRegsCpuPBase,
gsSGXDeviceMap.ui32RegsSize,
PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
IMG_NULL);
if(!pvRegsLinAddr)
{
return IMG_NULL;
}
#if SGX_CORE_REV == 105
ui32SGXRevision = 0x10005;
#else
ui32SGXRevision = OSReadHWReg((IMG_PVOID)((IMG_PBYTE)pvRegsLinAddr),
EUR_CR_CORE_REVISION);
#endif
#else
ui32SGXRevision = 0;
#endif
SysAcquireData(&psSysData);
i32Count = OSSNPrintf(aszVersionString, 100,
"SGX revision = %u.%u.%u",
(IMG_UINT)((ui32SGXRevision & EUR_CR_CORE_REVISION_MAJOR_MASK)
>> EUR_CR_CORE_REVISION_MAJOR_SHIFT),
(IMG_UINT)((ui32SGXRevision & EUR_CR_CORE_REVISION_MINOR_MASK)
>> EUR_CR_CORE_REVISION_MINOR_SHIFT),
(IMG_UINT)((ui32SGXRevision & EUR_CR_CORE_REVISION_MAINTENANCE_MASK)
>> EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT)
);
#if !defined(NO_HARDWARE)
OSUnMapPhysToLin(pvRegsLinAddr,
SYS_OMAP5430_SGX_REGS_SIZE,
PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
IMG_NULL);
#endif
if(i32Count == -1)
{
return IMG_NULL;
}
return aszVersionString;
}
IMG_VOID DisableSystemClocks(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
IMG_BOOL bPowerLock;
#if defined(DEBUG) || defined(TIMING)
IMG_CPU_PHYADDR TimerRegPhysBase;
IMG_HANDLE hTimerDisable;
IMG_UINT32 *pui32TimerDisable;
#endif
PVR_TRACE(("DisableSystemClocks: Disabling System Clocks"));
DisableSGXClocks(psSysData);
bPowerLock = PowerLockWrappedOnCPU(psSysSpecData);
if (bPowerLock)
{
PowerLockUnwrap(psSysSpecData);
}
#if defined(DEBUG) || defined(TIMING)
TimerRegPhysBase.uiAddr = SYS_OMAP3430_GP11TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerDisable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerDisable);
if (pui32TimerDisable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSystemClocks: OSMapPhysToLin failed"));
}
else
{
*pui32TimerDisable = 0;
OSUnMapPhysToLin(pui32TimerDisable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerDisable);
}
clk_disable(psSysSpecData->psGPT11_ICK);
clk_disable(psSysSpecData->psGPT11_FCK);
#endif
if (bPowerLock)
{
PowerLockWrap(psSysSpecData);
}
}
static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
IMG_HANDLE hTimerDisable;
IMG_UINT32 *pui32TimerDisable;
IMG_CPU_PHYADDR TimerRegPhysBase;
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
if (psSysSpecData->sTimerRegPhysBase.uiAddr == 0)
{
return;
}
#endif
TimerRegPhysBase.uiAddr = SYS_TI335x_GP7TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerDisable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerDisable);
if (pui32TimerDisable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSystemClocks: OSMapPhysToLin failed"));
}
else
{
*pui32TimerDisable = 0;
OSUnMapPhysToLin(pui32TimerDisable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerDisable);
}
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
psSysSpecData->sTimerRegPhysBase.uiAddr = 0;
#endif
#if defined(PVR_OMAP3_TIMING_PRCM)
clk_disable(psSysSpecData->psGPT11_ICK);
clk_disable(psSysSpecData->psGPT11_FCK);
#endif
}
PVRSRV_ERROR SysDebugInfo(PVRSRV_SYSTEM_CONFIG *psSysConfig)
{
PVRSRV_DEVICE_CONFIG *psDevice;
IMG_CPU_PHYADDR sWrapperRegsCpuPBase;
IMG_VOID *pvWrapperRegs;
psDevice = &sSysConfig.pasDevices[0];
sWrapperRegsCpuPBase.uiAddr = psDevice->sRegsCpuPBase.uiAddr + EMULATOR_RGX_REG_WRAPPER_OFFSET;
/* map emu registers */
pvWrapperRegs = OSMapPhysToLin(sWrapperRegsCpuPBase,
EMULATOR_RGX_REG_WRAPPER_SIZE,
0);
if (pvWrapperRegs == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR,"SysDebugDump: Failed to create wrapper register mapping\n"));
return PVRSRV_ERROR_BAD_MAPPING;
}
PVR_LOG(("------[ System Debug ]------"));
#define SYS_EMU_DBG_R32(R) PVR_LOG(("%-25s 0x%08X", #R ":", OSReadHWReg32(pvWrapperRegs, R)))
#define SYS_EMU_DBG_R64(R) PVR_LOG(("%-25s 0x%010llX", #R ":", OSReadHWReg64(pvWrapperRegs, R)))
SYS_EMU_DBG_R32(EMU_CR_PCI_MASTER);
SYS_EMU_DBG_R64(EMU_CR_WRAPPER_ERROR);
SYS_EMU_DBG_R32(EMU_CR_BANK_OUTSTANDING0);
SYS_EMU_DBG_R32(EMU_CR_BANK_OUTSTANDING1);
SYS_EMU_DBG_R32(EMU_CR_BANK_OUTSTANDING2);
SYS_EMU_DBG_R32(EMU_CR_BANK_OUTSTANDING3);
SYS_EMU_DBG_R32(EMU_CR_MEMORY_LATENCY);
/* remove mapping */
OSUnMapPhysToLin(pvWrapperRegs, EMULATOR_RGX_REG_WRAPPER_SIZE, 0);
return PVRSRV_OK;
}
/*!
******************************************************************************
@Function ReleaseGPTimer
@Description Release a GP timer
@Return PVRSRV_ERROR
******************************************************************************/
static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
IMG_HANDLE hTimerDisable;
IMG_UINT32 *pui32TimerDisable;
IMG_CPU_PHYADDR TimerRegPhysBase;
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
if (psSysSpecData->sTimerRegPhysBase.uiAddr == 0)
{
return;
}
#endif
/* Disable the timer */
pui32TimerDisable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerDisable);
if (pui32TimerDisable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSystemClocks: OSMapPhysToLin failed"));
}
else
{
*pui32TimerDisable = 0;
OSUnMapPhysToLin(pui32TimerDisable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerDisable);
}
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
psSysSpecData->sTimerRegPhysBase.uiAddr = 0;
#endif
#if defined(PVR_OMAP4_TIMING_PRCM)
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))
clk_disable(psSysSpecData->psGPT11_ICK);
#endif
clk_disable(psSysSpecData->psGPT11_FCK);
#endif /* defined(PVR_OMAP4_TIMING_PRCM) */
}
/***********************************************************************//**
* Deinitialise the system for unloading the driver
*
* @returns PVRSRV_OK for success, or failure code
**************************************************************************/
PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA * psSysSpecData;
PVRSRV_ERROR eError;
if (psSysData == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "SysDeinitialise: NULL SYS_DATA pointer."));
return PVRSRV_OK;
}
psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
#if defined(SYS_USING_INTERRUPTS)
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_IRQ_ENABLED))
{
SysDisableInterrupts(psSysData);
SYS_SPECIFIC_DATA_CLEAR(psSysSpecData, SYS_SPECIFIC_DATA_IRQ_ENABLED);
}
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_LISR_INSTALLED))
{
eError = OSUninstallSystemLISR(psSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: OSUninstallSystemLISR failed"));
return eError;
}
SYS_SPECIFIC_DATA_CLEAR(psSysSpecData, SYS_SPECIFIC_DATA_LISR_INSTALLED);
}
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_MISR_INSTALLED))
{
eError = OSUninstallMISR(psSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: OSUninstallMISR failed"));
return eError;
}
SYS_SPECIFIC_DATA_CLEAR(psSysSpecData, SYS_SPECIFIC_DATA_MISR_INSTALLED);
}
#endif /* #if defined(SYS_USING_INTERRUPTS) */
#if defined(SUPPORT_MSVDX)
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_INITVXDDEV))
{
/* de-initialise all services managed devices */
eError = PVRSRVDeinitialiseDevice(gui32MSVDXDeviceID);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: failed to de-init the device"));
return eError;
}
SYS_SPECIFIC_DATA_CLEAR(psSysSpecData, SYS_SPECIFIC_DATA_INITVXDDEV);
}
#endif
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_INITSGXDEV))
{
/* de-initialise all services managed devices */
eError = PVRSRVDeinitialiseDevice(gui32SGXDeviceID);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: failed to de-init the device"));
return eError;
}
SYS_SPECIFIC_DATA_CLEAR(psSysSpecData, SYS_SPECIFIC_DATA_INITSGXDEV);
}
SysFreeVersionString(psSysData);
PCIDeInitDev(psSysData);
SysDeinitialiseCommon(gpsSysData);
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_ENVDATA))
{
eError = OSDeInitEnvData(gpsSysData->pvEnvSpecificData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: failed to de-init env structure"));
return eError;
}
SYS_SPECIFIC_DATA_CLEAR(psSysSpecData, SYS_SPECIFIC_DATA_ENVDATA);
}
#if defined(NO_HARDWARE)
#if defined(SUPPORT_MSVDX)
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_DUMMY_MSVDX_REGS))
{
OSBaseFreeContigMemory(MSVDX_REG_SIZE,
gsMSVDXDeviceMap.sRegsCpuVBase,
gsMSVDXDeviceMap.sRegsCpuPBase);
SYS_SPECIFIC_DATA_CLEAR(psSysSpecData,
SYS_SPECIFIC_DATA_DUMMY_MSVDX_REGS);
}
#endif
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_DUMMY_SGX_REGS))
{
OSBaseFreeContigMemory(SYS_SGX_REG_SIZE,
gsSGXDeviceMap.pvRegsCpuVBase,
gsSGXDeviceMap.sRegsCpuPBase);
SYS_SPECIFIC_DATA_CLEAR(psSysSpecData,
SYS_SPECIFIC_DATA_DUMMY_SGX_REGS);
}
#endif
#if !defined(NO_HARDWARE)
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_SOC_REGS_MAPPED))
{
OSUnMapPhysToLin(gsSOCDeviceMap.sRegsCpuVBase,
SYS_SOC_REG_SIZE,
PVRSRV_HAP_KERNEL_ONLY | PVRSRV_HAP_UNCACHED,
IMG_NULL);
SYS_SPECIFIC_DATA_CLEAR(psSysSpecData, SYS_SPECIFIC_DATA_SOC_REGS_MAPPED);
}
#endif
psSysSpecData->ui32SysSpecificData = 0;
gpsSysData = IMG_NULL;
return PVRSRV_OK;
}
static IMG_BOOL ZeroBuf(struct BM_BUF *pBuf, struct BM_MAPPING *pMapping,
u32 ui32Bytes, u32 ui32Flags)
{
void *pvCpuVAddr;
if (pBuf->CpuVAddr) {
OSMemSet(pBuf->CpuVAddr, 0, ui32Bytes);
} else if (pMapping->eCpuMemoryOrigin == hm_contiguous ||
pMapping->eCpuMemoryOrigin == hm_wrapped) {
pvCpuVAddr = (void __force *)OSMapPhysToLin(pBuf->CpuPAddr,
ui32Bytes,
PVRSRV_HAP_KERNEL_ONLY |
(ui32Flags &
PVRSRV_HAP_CACHETYPE_MASK),
NULL);
if (!pvCpuVAddr) {
PVR_DPF(PVR_DBG_ERROR, "ZeroBuf: "
"OSMapPhysToLin for contiguous buffer failed");
return IMG_FALSE;
}
OSMemSet(pvCpuVAddr, 0, ui32Bytes);
OSUnMapPhysToLin((void __force __iomem *)pvCpuVAddr, ui32Bytes,
PVRSRV_HAP_KERNEL_ONLY |
(ui32Flags & PVRSRV_HAP_CACHETYPE_MASK),
NULL);
} else {
u32 ui32BytesRemaining = ui32Bytes;
u32 ui32CurrentOffset = 0;
struct IMG_CPU_PHYADDR CpuPAddr;
PVR_ASSERT(pBuf->hOSMemHandle);
while (ui32BytesRemaining > 0) {
u32 ui32BlockBytes =
MIN(ui32BytesRemaining, HOST_PAGESIZE());
CpuPAddr =
OSMemHandleToCpuPAddr(pBuf->hOSMemHandle,
ui32CurrentOffset);
if (CpuPAddr.uiAddr & (HOST_PAGESIZE() - 1))
ui32BlockBytes =
MIN(ui32BytesRemaining,
HOST_PAGEALIGN(CpuPAddr.uiAddr) -
CpuPAddr.uiAddr);
pvCpuVAddr = (void __force *)OSMapPhysToLin(CpuPAddr,
ui32BlockBytes,
PVRSRV_HAP_KERNEL_ONLY |
(ui32Flags &
PVRSRV_HAP_CACHETYPE_MASK),
NULL);
if (!pvCpuVAddr) {
PVR_DPF(PVR_DBG_ERROR, "ZeroBuf: "
"OSMapPhysToLin while "
"zeroing non-contiguous memory FAILED");
return IMG_FALSE;
}
OSMemSet(pvCpuVAddr, 0, ui32BlockBytes);
OSUnMapPhysToLin((void __force __iomem *)pvCpuVAddr,
ui32BlockBytes,
PVRSRV_HAP_KERNEL_ONLY |
(ui32Flags &
PVRSRV_HAP_CACHETYPE_MASK),
NULL);
ui32BytesRemaining -= ui32BlockBytes;
ui32CurrentOffset += ui32BlockBytes;
}
}
return IMG_TRUE;
}
static PVRSRV_ERROR SysCreateVersionString(SYS_DATA *psSysData)
{
IMG_UINT32 ui32MaxStrLen;
PVRSRV_ERROR eError;
IMG_INT32 i32Count;
IMG_CHAR *pszVersionString;
IMG_UINT32 ui32SGXRevision = 0;
IMG_VOID *pvSGXRegs;
pvSGXRegs = OSMapPhysToLin(gsSGXDeviceMap.sRegsCpuPBase,
gsSGXDeviceMap.ui32RegsSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
if (pvSGXRegs != IMG_NULL)
{
ui32SGXRevision = OSReadHWReg(pvSGXRegs, EUR_CR_CORE_REVISION);
OSUnMapPhysToLin(pvSGXRegs,
gsSGXDeviceMap.ui32RegsSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
}
else
{
PVR_DPF((PVR_DBG_ERROR,"SysCreateVersionString: Couldn't map SGX registers"));
}
ui32MaxStrLen = OSStringLength(VERSION_STR_MAX_LEN_TEMPLATE);
eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
ui32MaxStrLen + 1,
(IMG_PVOID *)&pszVersionString,
IMG_NULL,
"Version String");
if(eError != PVRSRV_OK)
{
return eError;
}
i32Count = OSSNPrintf(pszVersionString, ui32MaxStrLen + 1,
"SGX revision = %u.%u.%u",
(IMG_UINT)((ui32SGXRevision & EUR_CR_CORE_REVISION_MAJOR_MASK)
>> EUR_CR_CORE_REVISION_MAJOR_SHIFT),
(IMG_UINT)((ui32SGXRevision & EUR_CR_CORE_REVISION_MINOR_MASK)
>> EUR_CR_CORE_REVISION_MINOR_SHIFT),
(IMG_UINT)((ui32SGXRevision & EUR_CR_CORE_REVISION_MAINTENANCE_MASK)
>> EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT)
);
if(i32Count == -1)
{
ui32MaxStrLen = OSStringLength(VERSION_STR_MAX_LEN_TEMPLATE);
OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
ui32MaxStrLen + 1,
pszVersionString,
IMG_NULL);
return PVRSRV_ERROR_INVALID_PARAMS;
}
psSysData->pszVersionString = pszVersionString;
return PVRSRV_OK;
}
static PVRSRV_ERROR SysUnmapRegisters(IMG_VOID)
{
PVRSRV_DEVICE_NODE *psDeviceNodeList;
psDeviceNodeList = gpsSysData->psDeviceNodeList;
while (psDeviceNodeList)
{
switch (psDeviceNodeList->sDevId.eDeviceType)
{
case PVRSRV_DEVICE_TYPE_SGX:
{
PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNodeList->pvDevice;
#if !(defined(NO_HARDWARE) && defined(__linux__))
if (psDevInfo->pvRegsBaseKM)
{
OSUnMapPhysToLin(psDevInfo->pvRegsBaseKM,
gsSGXDeviceMap.ui32RegsSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_PM_UNMAP_SGX_REGS);
}
#endif
psDevInfo->pvRegsBaseKM = IMG_NULL;
psDevInfo->ui32RegSize = 0;
psDevInfo->sRegsPhysBase.uiAddr = 0;
#if defined(SGX_FEATURE_HOST_PORT)
if (gsSGXDeviceMap.ui32Flags & SGX_HOSTPORT_PRESENT)
{
if (psDevInfo->pvHostPortBaseKM)
{
OSUnMapPhysToLin(psDevInfo->pvHostPortBaseKM,
gsSGXDeviceMap.ui32HPSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_PM_UNMAP_SGX_HP);
psDevInfo->pvHostPortBaseKM = IMG_NULL;
}
psDevInfo->ui32HPSize = 0;
psDevInfo->sHPSysPAddr.uiAddr = 0;
}
#endif
break;
}
default:
break;
}
psDeviceNodeList = psDeviceNodeList->psNext;
}
#if !(defined(NO_HARDWARE) && defined(__linux__))
OSUnMapPhysToLin(gsPoulsboRegsCPUVaddr,
POULSBO_REG_SIZE,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
OSUnMapPhysToLin(gsPoulsboDisplayRegsCPUVaddr,
POULSBO_DISPLAY_REG_SIZE,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
#endif
return PVRSRV_OK;
}
PVRSRV_ERROR IMG_CALLCONV PVRSRVSaveRestoreLiveSegments(IMG_HANDLE hArena, IMG_PBYTE pbyBuffer,
IMG_SIZE_T *puiBufSize, IMG_BOOL bSave)
{
IMG_SIZE_T uiBytesSaved = 0;
IMG_PVOID pvLocalMemCPUVAddr;
RA_SEGMENT_DETAILS sSegDetails;
if (hArena == IMG_NULL)
{
return (PVRSRV_ERROR_INVALID_PARAMS);
}
sSegDetails.uiSize = 0;
sSegDetails.sCpuPhyAddr.uiAddr = 0;
sSegDetails.hSegment = 0;
while (RA_GetNextLiveSegment(hArena, &sSegDetails))
{
if (pbyBuffer == IMG_NULL)
{
uiBytesSaved += sizeof(sSegDetails.uiSize) + sSegDetails.uiSize;
}
else
{
if ((uiBytesSaved + sizeof(sSegDetails.uiSize) + sSegDetails.uiSize) > *puiBufSize)
{
return (PVRSRV_ERROR_OUT_OF_MEMORY);
}
PVR_DPF((PVR_DBG_MESSAGE, "PVRSRVSaveRestoreLiveSegments: Base %08x size %08x", sSegDetails.sCpuPhyAddr.uiAddr, sSegDetails.uiSize));
pvLocalMemCPUVAddr = OSMapPhysToLin(sSegDetails.sCpuPhyAddr,
sSegDetails.uiSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
if (pvLocalMemCPUVAddr == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVSaveRestoreLiveSegments: Failed to map local memory to host"));
return (PVRSRV_ERROR_OUT_OF_MEMORY);
}
if (bSave)
{
OSMemCopy(pbyBuffer, &sSegDetails.uiSize, sizeof(sSegDetails.uiSize));
pbyBuffer += sizeof(sSegDetails.uiSize);
OSMemCopy(pbyBuffer, pvLocalMemCPUVAddr, sSegDetails.uiSize);
pbyBuffer += sSegDetails.uiSize;
}
else
{
IMG_UINT32 uiSize;
OSMemCopy(&uiSize, pbyBuffer, sizeof(sSegDetails.uiSize));
if (uiSize != sSegDetails.uiSize)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVSaveRestoreLiveSegments: Segment size error"));
}
else
{
pbyBuffer += sizeof(sSegDetails.uiSize);
OSMemCopy(pvLocalMemCPUVAddr, pbyBuffer, sSegDetails.uiSize);
pbyBuffer += sSegDetails.uiSize;
}
}
uiBytesSaved += sizeof(sSegDetails.uiSize) + sSegDetails.uiSize;
OSUnMapPhysToLin(pvLocalMemCPUVAddr,
sSegDetails.uiSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
}
}
if (pbyBuffer == IMG_NULL)
{
*puiBufSize = uiBytesSaved;
}
return (PVRSRV_OK);
}
static void _DeferredFreePageTable(struct MMU_HEAP *pMMUHeap, u32 ui32PTIndex)
{
u32 *pui32PDEntry;
u32 i;
u32 ui32PDIndex;
struct SYS_DATA *psSysData;
struct MMU_PT_INFO **ppsPTInfoList;
if (SysAcquireData(&psSysData) != PVRSRV_OK) {
PVR_DPF(PVR_DBG_ERROR, "_DeferredFreePageTables: "
"ERROR call to SysAcquireData failed");
return;
}
ui32PDIndex =
pMMUHeap->psDevArena->BaseDevVAddr.uiAddr >> (SGX_MMU_PAGE_SHIFT +
SGX_MMU_PT_SHIFT);
ppsPTInfoList = &pMMUHeap->psMMUContext->apsPTInfoList[ui32PDIndex];
{
PVR_ASSERT(ppsPTInfoList[ui32PTIndex] == NULL ||
ppsPTInfoList[ui32PTIndex]->ui32ValidPTECount ==
0);
}
PDUMPCOMMENT("Free page table (page count == %08X)",
pMMUHeap->ui32PTPageCount);
if (ppsPTInfoList[ui32PTIndex]
&& ppsPTInfoList[ui32PTIndex]->PTPageCpuVAddr)
PDUMPFREEPAGETABLE(ppsPTInfoList[ui32PTIndex]->PTPageCpuVAddr);
switch (pMMUHeap->psDevArena->DevMemHeapType) {
case DEVICE_MEMORY_HEAP_SHARED:
case DEVICE_MEMORY_HEAP_SHARED_EXPORTED:
{
struct MMU_CONTEXT *psMMUContext =
(struct MMU_CONTEXT *)
pMMUHeap->psMMUContext->psDevInfo->pvMMUContextList;
while (psMMUContext) {
pui32PDEntry =
(u32 *) psMMUContext->pvPDCpuVAddr;
pui32PDEntry += ui32PDIndex;
pui32PDEntry[ui32PTIndex] = 0;
PDUMPPAGETABLE((void *) &pui32PDEntry
[ui32PTIndex],
sizeof(u32), IMG_FALSE,
PDUMP_PT_UNIQUETAG,
PDUMP_PT_UNIQUETAG);
psMMUContext = psMMUContext->psNext;
}
break;
}
case DEVICE_MEMORY_HEAP_PERCONTEXT:
case DEVICE_MEMORY_HEAP_KERNEL:
{
pui32PDEntry =
(u32 *) pMMUHeap->psMMUContext->pvPDCpuVAddr;
pui32PDEntry += ui32PDIndex;
pui32PDEntry[ui32PTIndex] = 0;
PDUMPPAGETABLE((void *) &pui32PDEntry[ui32PTIndex],
sizeof(u32), IMG_FALSE,
PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG);
break;
}
default:
{
PVR_DPF(PVR_DBG_ERROR,
"_DeferredFreePagetable: ERROR invalid heap type");
return;
}
}
if (ppsPTInfoList[ui32PTIndex] != NULL) {
if (ppsPTInfoList[ui32PTIndex]->PTPageCpuVAddr != NULL) {
u32 *pui32Tmp;
pui32Tmp =
(u32 *) ppsPTInfoList[ui32PTIndex]->
PTPageCpuVAddr;
for (i = 0;
(i < pMMUHeap->ui32PTEntryCount) && (i < 1024);
i++)
pui32Tmp[i] = 0;
if (pMMUHeap->psDevArena->psDeviceMemoryHeapInfo->
psLocalDevMemArena == NULL) {
OSFreePages(PVRSRV_HAP_WRITECOMBINE |
PVRSRV_HAP_KERNEL_ONLY,
SGX_MMU_PAGE_SIZE,
ppsPTInfoList[ui32PTIndex]->
PTPageCpuVAddr,
ppsPTInfoList[ui32PTIndex]->
hPTPageOSMemHandle);
} else {
struct IMG_SYS_PHYADDR sSysPAddr;
struct IMG_CPU_PHYADDR sCpuPAddr;
sCpuPAddr =
OSMapLinToCPUPhys(ppsPTInfoList
[ui32PTIndex]->
PTPageCpuVAddr);
sSysPAddr = SysCpuPAddrToSysPAddr(sCpuPAddr);
OSUnMapPhysToLin((void __force __iomem *)
ppsPTInfoList[ui32PTIndex]->
PTPageCpuVAddr,
SGX_MMU_PAGE_SIZE,
PVRSRV_HAP_WRITECOMBINE |
PVRSRV_HAP_KERNEL_ONLY,
ppsPTInfoList[ui32PTIndex]->
hPTPageOSMemHandle);
RA_Free(pMMUHeap->psDevArena->
psDeviceMemoryHeapInfo->
psLocalDevMemArena,
sSysPAddr.uiAddr, IMG_FALSE);
}
pMMUHeap->ui32PTEntryCount -= i;
} else {
pMMUHeap->ui32PTEntryCount -= 1024;
}
OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
sizeof(struct MMU_PT_INFO),
ppsPTInfoList[ui32PTIndex], NULL);
ppsPTInfoList[ui32PTIndex] = NULL;
} else {
pMMUHeap->ui32PTEntryCount -= 1024;
}
PDUMPCOMMENT("Finished free page table (page count == %08X)",
pMMUHeap->ui32PTPageCount);
}
static PVRSRV_ERROR SysUnmapRegisters(IMG_VOID)
{
PVRSRV_DEVICE_NODE *psDeviceNodeList;
psDeviceNodeList = gpsSysData->psDeviceNodeList;
while (psDeviceNodeList)
{
PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNodeList->pvDevice;
if (psDeviceNodeList->sDevId.eDeviceType == PVRSRV_DEVICE_TYPE_SGX)
{
#if !(defined(NO_HARDWARE) && defined(__linux__))
/* Unmap Regs */
if (psDevInfo->pvRegsBaseKM)
{
OSUnMapPhysToLin(psDevInfo->pvRegsBaseKM,
gsSGXDeviceMap.ui32RegsSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_PM_UNMAP_SGX_REGS);
}
#endif /* #if !(defined(NO_HARDWARE) && defined(__linux__)) */
psDevInfo->pvRegsBaseKM = IMG_NULL;
psDevInfo->ui32RegSize = 0;
psDevInfo->sRegsPhysBase.uiAddr = 0;
#if defined(SGX_FEATURE_HOST_PORT)
if (gsSGXDeviceMap.ui32Flags & SGX_HOSTPORT_PRESENT)
{
/* Unmap Host Port */
if (psDevInfo->pvHostPortBaseKM)
{
OSUnMapPhysToLin(psDevInfo->pvHostPortBaseKM,
gsSGXDeviceMap.ui32HPSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_PM_UNMAP_SGX_HP);
psDevInfo->pvHostPortBaseKM = IMG_NULL;
}
psDevInfo->ui32HPSize = 0;
psDevInfo->sHPSysPAddr.uiAddr = 0;
}
#endif /* #if defined(SGX_FEATURE_HOST_PORT) */
}
psDeviceNodeList = psDeviceNodeList->psNext;
}
#if defined(NO_HARDWARE)
PVR_ASSERT(gsSGXRegsCPUVAddr);
OSBaseFreeContigMemory(SYS_SGX_REG_SIZE, gsSGXRegsCPUVAddr, gsSGXDeviceMap.sRegsCpuPBase);
SYS_SPECIFIC_DATA_CLEAR(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_REG_MEM);
gsSGXRegsCPUVAddr = IMG_NULL;
#endif
/* Unmap the Atlas and PDP registers */
if (gpsSysData->pvSOCRegsBase)
{
OSUnMapPhysToLin(gpsSysData->pvSOCRegsBase,
SYS_ATLAS_REG_REGION_SIZE,
PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
IMG_NULL);
gpsSysData->pvSOCRegsBase = IMG_NULL;
}
return PVRSRV_OK;
}
enum PVRSRV_ERROR MMU_Initialise(struct PVRSRV_DEVICE_NODE *psDeviceNode,
struct MMU_CONTEXT **ppsMMUContext,
struct IMG_DEV_PHYADDR *psPDDevPAddr)
{
u32 *pui32Tmp;
u32 i;
void *pvPDCpuVAddr;
struct IMG_DEV_PHYADDR sPDDevPAddr;
struct IMG_CPU_PHYADDR sCpuPAddr;
struct IMG_SYS_PHYADDR sSysPAddr;
struct MMU_CONTEXT *psMMUContext;
void *hPDOSMemHandle;
struct SYS_DATA *psSysData;
struct PVRSRV_SGXDEV_INFO *psDevInfo;
PVR_DPF(PVR_DBG_MESSAGE, "MMU_Initialise");
if (SysAcquireData(&psSysData) != PVRSRV_OK) {
PVR_DPF(PVR_DBG_ERROR,
"MMU_Initialise: ERROR call to SysAcquireData failed");
return PVRSRV_ERROR_GENERIC;
}
if (OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
sizeof(struct MMU_CONTEXT), (void **) &psMMUContext, NULL)
!= PVRSRV_OK) {
PVR_DPF(PVR_DBG_ERROR,
"MMU_Initialise: ERROR call to OSAllocMem failed");
return PVRSRV_ERROR_GENERIC;
}
OSMemSet(psMMUContext, 0, sizeof(struct MMU_CONTEXT));
psDevInfo = (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
psMMUContext->psDevInfo = psDevInfo;
psMMUContext->psDeviceNode = psDeviceNode;
if (psDeviceNode->psLocalDevMemArena == NULL) {
if (OSAllocPages
(PVRSRV_HAP_WRITECOMBINE | PVRSRV_HAP_KERNEL_ONLY,
SGX_MMU_PAGE_SIZE, SGX_MMU_PAGE_SIZE, &pvPDCpuVAddr,
&hPDOSMemHandle) != PVRSRV_OK) {
PVR_DPF(PVR_DBG_ERROR, "MMU_Initialise: "
"ERROR call to OSAllocPages failed");
goto err1;
}
if (pvPDCpuVAddr)
sCpuPAddr = OSMapLinToCPUPhys(pvPDCpuVAddr);
else
sCpuPAddr = OSMemHandleToCpuPAddr(hPDOSMemHandle, 0);
sPDDevPAddr =
SysCpuPAddrToDevPAddr(PVRSRV_DEVICE_TYPE_SGX, sCpuPAddr);
} else {
if (RA_Alloc(psDeviceNode->psLocalDevMemArena,
SGX_MMU_PAGE_SIZE, NULL, 0, SGX_MMU_PAGE_SIZE,
&(sSysPAddr.uiAddr)) != IMG_TRUE) {
PVR_DPF(PVR_DBG_ERROR, "MMU_Initialise: "
"ERROR call to RA_Alloc failed");
goto err1;
}
sCpuPAddr = SysSysPAddrToCpuPAddr(sSysPAddr);
sPDDevPAddr =
SysSysPAddrToDevPAddr(PVRSRV_DEVICE_TYPE_SGX, sSysPAddr);
pvPDCpuVAddr = (void __force *)
OSMapPhysToLin(sCpuPAddr, SGX_MMU_PAGE_SIZE,
PVRSRV_HAP_WRITECOMBINE |
PVRSRV_HAP_KERNEL_ONLY, &hPDOSMemHandle);
if (!pvPDCpuVAddr) {
PVR_DPF(PVR_DBG_ERROR, "MMU_Initialise: "
"ERROR failed to map page tables");
goto err2;
}
}
PDUMPCOMMENT("Alloc page directory");
PDUMPMALLOCPAGETABLE(pvPDCpuVAddr, PDUMP_PD_UNIQUETAG);
if (pvPDCpuVAddr) {
pui32Tmp = (u32 *) pvPDCpuVAddr;
} else {
PVR_DPF(PVR_DBG_ERROR,
"MMU_Initialise: pvPDCpuVAddr invalid");
goto err3;
}
for (i = 0; i < SGX_MMU_PD_SIZE; i++)
pui32Tmp[i] = 0;
PDUMPCOMMENT("Page directory contents");
PDUMPPAGETABLE(pvPDCpuVAddr, SGX_MMU_PAGE_SIZE, IMG_TRUE,
PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG);
psMMUContext->pvPDCpuVAddr = pvPDCpuVAddr;
psMMUContext->sPDDevPAddr = sPDDevPAddr;
psMMUContext->hPDOSMemHandle = hPDOSMemHandle;
*ppsMMUContext = psMMUContext;
*psPDDevPAddr = sPDDevPAddr;
psMMUContext->psNext = (struct MMU_CONTEXT *)
psDevInfo->pvMMUContextList;
psDevInfo->pvMMUContextList = (void *) psMMUContext;
return PVRSRV_OK;
err3:
if (psDeviceNode->psLocalDevMemArena)
OSUnMapPhysToLin((void __iomem __force *)pvPDCpuVAddr,
SGX_MMU_PAGE_SIZE, PVRSRV_HAP_WRITECOMBINE |
PVRSRV_HAP_KERNEL_ONLY,
hPDOSMemHandle);
err2:
if (!psDeviceNode->psLocalDevMemArena)
OSFreePages(PVRSRV_HAP_WRITECOMBINE | PVRSRV_HAP_KERNEL_ONLY,
SGX_MMU_PAGE_SIZE, pvPDCpuVAddr, hPDOSMemHandle);
else
RA_Free(psDeviceNode->psLocalDevMemArena,
sSysPAddr.uiAddr, IMG_FALSE);
err1:
OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(struct MMU_CONTEXT),
psMMUContext, NULL);
return PVRSRV_ERROR_GENERIC;
}
static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
#if defined(PVR_OMAP3_TIMING_PRCM)
struct clk *psCLK;
IMG_INT res;
struct clk *sys_ck;
IMG_INT rate;
#endif
PVRSRV_ERROR eError;
IMG_CPU_PHYADDR sTimerRegPhysBase;
IMG_HANDLE hTimerEnable;
IMG_UINT32 *pui32TimerEnable;
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
PVR_ASSERT(psSysSpecData->sTimerRegPhysBase.uiAddr == 0);
#endif
#if defined(PVR_OMAP3_TIMING_PRCM)
psCLK = clk_get(NULL, "gpt7_fck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock"));
goto ExitError;
}
psSysSpecData->psGPT11_FCK = psCLK;
psCLK = clk_get(NULL, "gpt7_ick");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock"));
goto ExitError;
}
psSysSpecData->psGPT11_ICK = psCLK;
rate = clk_get_rate(psSysSpecData->psGPT11_FCK);
PVR_TRACE(("GPTIMER11 clock is %dMHz", HZ_TO_MHZ(rate)));
res = clk_enable(psSysSpecData->psGPT11_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res));
goto ExitError;
}
res = clk_enable(psSysSpecData->psGPT11_ICK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 interface clock (%d)", res));
goto ExitDisableGPT11FCK;
}
#endif
sTimerRegPhysBase.uiAddr = SYS_TI335x_GP7TIMER_TSICR_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
if(!(*pui32TimerEnable & 4))
{
PVR_TRACE(("Setting GPTIMER11 mode to posted (currently is non-posted)"));
*pui32TimerEnable |= 4;
}
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
sTimerRegPhysBase.uiAddr = SYS_TI335x_GP7TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
*pui32TimerEnable = 3;
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
psSysSpecData->sTimerRegPhysBase = sTimerRegPhysBase;
#endif
eError = PVRSRV_OK;
goto Exit;
ExitDisableGPT11ICK:
#if defined(PVR_OMAP3_TIMING_PRCM)
clk_disable(psSysSpecData->psGPT11_ICK);
ExitDisableGPT11FCK:
clk_disable(psSysSpecData->psGPT11_FCK);
ExitError:
#endif
eError = PVRSRV_ERROR_CLOCK_REQUEST_FAILED;
Exit:
return eError;
}
static IMG_BOOL
ZeroBuf(BM_BUF *pBuf, BM_MAPPING *pMapping, IMG_SIZE_T ui32Bytes, IMG_UINT32 ui32Flags)
{
IMG_VOID *pvCpuVAddr;
if(pBuf->CpuVAddr)
{
OSMemSet(pBuf->CpuVAddr, 0, ui32Bytes);
}
else if(pMapping->eCpuMemoryOrigin == hm_contiguous
|| pMapping->eCpuMemoryOrigin == hm_wrapped)
{
pvCpuVAddr = OSMapPhysToLin(pBuf->CpuPAddr,
ui32Bytes,
PVRSRV_HAP_KERNEL_ONLY
| (ui32Flags & PVRSRV_HAP_CACHETYPE_MASK),
IMG_NULL);
if(!pvCpuVAddr)
{
PVR_DPF((PVR_DBG_ERROR, "ZeroBuf: OSMapPhysToLin for contiguous buffer failed"));
return IMG_FALSE;
}
OSMemSet(pvCpuVAddr, 0, ui32Bytes);
OSUnMapPhysToLin(pvCpuVAddr,
ui32Bytes,
PVRSRV_HAP_KERNEL_ONLY
| (ui32Flags & PVRSRV_HAP_CACHETYPE_MASK),
IMG_NULL);
}
else
{
IMG_SIZE_T ui32BytesRemaining = ui32Bytes;
IMG_SIZE_T ui32CurrentOffset = 0;
IMG_CPU_PHYADDR CpuPAddr;
PVR_ASSERT(pBuf->hOSMemHandle);
while(ui32BytesRemaining > 0)
{
IMG_SIZE_T ui32BlockBytes = MIN(ui32BytesRemaining, HOST_PAGESIZE());
CpuPAddr = OSMemHandleToCpuPAddr(pBuf->hOSMemHandle, ui32CurrentOffset);
if(CpuPAddr.uiAddr & (HOST_PAGESIZE() -1))
{
ui32BlockBytes =
MIN(ui32BytesRemaining, (IMG_UINT32)(HOST_PAGEALIGN(CpuPAddr.uiAddr) - CpuPAddr.uiAddr));
}
pvCpuVAddr = OSMapPhysToLin(CpuPAddr,
ui32BlockBytes,
PVRSRV_HAP_KERNEL_ONLY
| (ui32Flags & PVRSRV_HAP_CACHETYPE_MASK),
IMG_NULL);
if(!pvCpuVAddr)
{
PVR_DPF((PVR_DBG_ERROR, "ZeroBuf: OSMapPhysToLin while zeroing non-contiguous memory FAILED"));
return IMG_FALSE;
}
OSMemSet(pvCpuVAddr, 0, ui32BlockBytes);
OSUnMapPhysToLin(pvCpuVAddr,
ui32BlockBytes,
PVRSRV_HAP_KERNEL_ONLY
| (ui32Flags & PVRSRV_HAP_CACHETYPE_MASK),
IMG_NULL);
ui32BytesRemaining -= ui32BlockBytes;
ui32CurrentOffset += ui32BlockBytes;
}
}
return IMG_TRUE;
}
void MMU_Finalise(struct MMU_CONTEXT *psMMUContext)
{
u32 *pui32Tmp, i;
struct SYS_DATA *psSysData;
struct MMU_CONTEXT **ppsMMUContext;
if (SysAcquireData(&psSysData) != PVRSRV_OK) {
PVR_DPF(PVR_DBG_ERROR,
"MMU_Finalise: ERROR call to SysAcquireData failed");
return;
}
PDUMPCOMMENT("Free page directory");
PDUMPFREEPAGETABLE(psMMUContext->pvPDCpuVAddr);
pui32Tmp = (u32 *) psMMUContext->pvPDCpuVAddr;
for (i = 0; i < SGX_MMU_PD_SIZE; i++)
pui32Tmp[i] = 0;
if (psMMUContext->psDeviceNode->psLocalDevMemArena == NULL) {
OSFreePages(PVRSRV_HAP_WRITECOMBINE | PVRSRV_HAP_KERNEL_ONLY,
SGX_MMU_PAGE_SIZE,
psMMUContext->pvPDCpuVAddr,
psMMUContext->hPDOSMemHandle);
} else {
struct IMG_SYS_PHYADDR sSysPAddr;
struct IMG_CPU_PHYADDR sCpuPAddr;
sCpuPAddr = OSMapLinToCPUPhys(psMMUContext->pvPDCpuVAddr);
sSysPAddr = SysCpuPAddrToSysPAddr(sCpuPAddr);
OSUnMapPhysToLin((void __iomem __force *)
psMMUContext->pvPDCpuVAddr,
SGX_MMU_PAGE_SIZE,
PVRSRV_HAP_WRITECOMBINE |
PVRSRV_HAP_KERNEL_ONLY,
psMMUContext->hPDOSMemHandle);
RA_Free(psMMUContext->psDeviceNode->psLocalDevMemArena,
sSysPAddr.uiAddr, IMG_FALSE);
}
PVR_DPF(PVR_DBG_MESSAGE, "MMU_Finalise");
ppsMMUContext =
(struct MMU_CONTEXT **) &psMMUContext->psDevInfo->pvMMUContextList;
while (*ppsMMUContext) {
if (*ppsMMUContext == psMMUContext) {
*ppsMMUContext = psMMUContext->psNext;
break;
}
ppsMMUContext = &((*ppsMMUContext)->psNext);
}
OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(struct MMU_CONTEXT),
psMMUContext, NULL);
}
/*!
******************************************************************************
@Function AcquireGPTimer
@Description Acquire a GP timer
@Return PVRSRV_ERROR
******************************************************************************/
static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
#if defined(PVR_OMAP4_TIMING_PRCM)
struct clk *psCLK;
IMG_INT res;
struct clk *sys_ck;
IMG_INT rate;
#endif
PVRSRV_ERROR eError;
IMG_CPU_PHYADDR sTimerRegPhysBase;
IMG_HANDLE hTimerEnable;
IMG_UINT32 *pui32TimerEnable;
PVR_ASSERT(psSysSpecData->sTimerRegPhysBase.uiAddr == 0);
psCLK = clk_get(NULL, "sgx_fck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get SGX Interface Clock"));
return;
}
clk_enable(psCLK);
psCLK = clk_get(NULL, "sgx_ick");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get SGX Interface Clock"));
return;
}
clk_enable(psCLK);
#if defined(PVR_OMAP4_TIMING_PRCM)
psCLK = clk_get(NULL, "gpt6_fck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock"));
goto ExitError;
}
psSysSpecData->psGPT11_FCK = psCLK;
psCLK = clk_get(NULL, "gpt6_ick");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock"));
goto ExitError;
}
psSysSpecData->psGPT11_ICK = psCLK;
sys_ck = clk_get(NULL, "sys_ck");
if (IS_ERR(sys_ck))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get System clock"));
goto ExitError;
}
if(clk_get_parent(psSysSpecData->psGPT11_FCK) != sys_ck)
{
PVR_TRACE(("Setting GPTIMER11 parent to System Clock"));
res = clk_set_parent(psSysSpecData->psGPT11_FCK, sys_ck);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set GPTIMER11 parent clock (%d)", res));
goto ExitError;
}
}
rate = clk_get_rate(psSysSpecData->psGPT11_FCK);
PVR_TRACE(("GPTIMER11 clock is %dMHz", HZ_TO_MHZ(rate)));
res = clk_enable(psSysSpecData->psGPT11_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res));
goto ExitError;
}
res = clk_enable(psSysSpecData->psGPT11_ICK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 interface clock (%d)", res));
goto ExitDisableGPT11FCK;
}
#endif /* defined(PVR_OMAP4_TIMING_PRCM) */
/* Set the timer to non-posted mode */
sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_TSICR_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
if(!(*pui32TimerEnable & 4))
{
PVR_TRACE(("Setting GPTIMER11 mode to posted (currently is non-posted)"));
/* Set posted mode */
*pui32TimerEnable |= 4;
}
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
/* Enable the timer */
sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
/* Enable and set autoreload on overflow */
*pui32TimerEnable = 3;
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
psSysSpecData->sTimerRegPhysBase = sTimerRegPhysBase;
eError = PVRSRV_OK;
goto Exit;
ExitDisableGPT11ICK:
#if defined(PVR_OMAP4_TIMING_PRCM)
clk_disable(psSysSpecData->psGPT11_ICK);
ExitDisableGPT11FCK:
clk_disable(psSysSpecData->psGPT11_FCK);
ExitError:
#endif /* defined(PVR_OMAP4_TIMING_PRCM) */
eError = PVRSRV_ERROR_CLOCK_REQUEST_FAILED;
Exit:
return eError;
}
PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
struct clk *psCLK;
IMG_INT res;
PVRSRV_ERROR eError;
IMG_BOOL bPowerLock;
#if defined(DEBUG) || defined(TIMING)
IMG_INT rate;
struct clk *sys_ck;
IMG_CPU_PHYADDR TimerRegPhysBase;
IMG_HANDLE hTimerEnable;
IMG_UINT32 *pui32TimerEnable;
#endif
PVR_TRACE(("EnableSystemClocks: Enabling System Clocks"));
if (!psSysSpecData->bSysClocksOneTimeInit)
{
bPowerLock = IMG_FALSE;
spin_lock_init(&psSysSpecData->sPowerLock);
atomic_set(&psSysSpecData->sPowerLockCPU, -1);
spin_lock_init(&psSysSpecData->sNotifyLock);
atomic_set(&psSysSpecData->sNotifyLockCPU, -1);
atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
psCLK = clk_get(NULL, "sgx_ck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSsystemClocks: Couldn't get SGX Functional Clock"));
goto ExitError;
}
psSysSpecData->psSGX_FCK = psCLK;
psSysSpecData->bSysClocksOneTimeInit = IMG_TRUE;
}
else
{
bPowerLock = PowerLockWrappedOnCPU(psSysSpecData);
if (bPowerLock)
{
PowerLockUnwrap(psSysSpecData);
}
}
#if defined(CONSTRAINT_NOTIFICATIONS)
psSysSpecData->pVdd2Handle = constraint_get(PVRSRV_MODNAME, &cnstr_id_vdd2);
if (IS_ERR(psSysSpecData->pVdd2Handle))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get VDD2 constraint handle"));
goto ExitError;
}
RegisterConstraintNotifications();
#endif
#if defined(DEBUG) || defined(TIMING)
if(cpu_is_ti816x()) {
psCLK = clk_get(NULL, "gpt6_fck");
} else {
psCLK = clk_get(NULL, "gpt7_fck");
}
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock"));
goto ExitUnRegisterConstraintNotifications;
}
psSysSpecData->psGPT11_FCK = psCLK;
if(cpu_is_ti816x()) {
psCLK = clk_get(NULL, "gpt6_ick");
} else {
psCLK = clk_get(NULL, "gpt7_ick");
}
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock"));
goto ExitUnRegisterConstraintNotifications;
}
psSysSpecData->psGPT11_ICK = psCLK;
rate = clk_get_rate(psSysSpecData->psGPT11_FCK);
PVR_TRACE(("GPTIMER11 clock is %dMHz", HZ_TO_MHZ(rate)));
res = clk_enable(psSysSpecData->psGPT11_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res));
goto ExitUnRegisterConstraintNotifications;
}
res = clk_enable(psSysSpecData->psGPT11_ICK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 interface clock (%d)", res));
goto ExitDisableGPT11FCK;
}
TimerRegPhysBase.uiAddr = SYS_TI81xx_GP7TIMER_TSICR_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
rate = *pui32TimerEnable;
if(!(rate & 4))
{
PVR_TRACE(("Setting GPTIMER11 mode to posted (currently is non-posted)"));
*pui32TimerEnable = rate | 4;
}
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
TimerRegPhysBase.uiAddr = SYS_TI81xx_GP7TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
*pui32TimerEnable = 3;
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
#endif
#if defined(PDUMP) && !defined(NO_HARDWARE) && defined(CONSTRAINT_NOTIFICATIONS)
PVR_TRACE(("EnableSystemClocks: Setting SGX OPP constraint"));
res = constraint_set(psSysSpecData->pVdd2Handle, max_vdd2_opp);
if (res != 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: constraint_set failed (%d)", res));
goto ExitConstraintSetFailed;
}
#endif
eError = PVRSRV_OK;
goto Exit;
#if defined(PDUMP) && !defined(NO_HARDWARE) && defined(CONSTRAINT_NOTIFICATIONS)
ExitConstraintSetFailed:
#endif
#if defined(DEBUG) || defined(TIMING)
ExitDisableGPT11ICK:
clk_disable(psSysSpecData->psGPT11_ICK);
ExitDisableGPT11FCK:
clk_disable(psSysSpecData->psGPT11_FCK);
ExitUnRegisterConstraintNotifications:
#endif
#if defined(CONSTRAINT_NOTIFICATIONS)
UnRegisterConstraintNotifications();
constraint_put(psSysSpecData->pVdd2Handle);
#endif
Exit:
if (bPowerLock)
{
PowerLockWrap(psSysSpecData);
}
ExitError:
eError = PVRSRV_ERROR_DISABLE_CLOCK_FAILURE;
return eError;
}
/*!
******************************************************************************
@Function SysDeinitialise
@Description De-initialises kernel services at 'driver unload' time
@Return PVRSRV_ERROR :
******************************************************************************/
PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA * psSysSpecData;
PVRSRV_ERROR eError;
if (psSysData == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "SysDeinitialise: Called with NULL SYS_DATA pointer. Probably called before."));
return PVRSRV_OK;
}
psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
#if defined(SYS_USING_INTERRUPTS)
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_ENABLE_IRQ))
{
SysDisableInterrupts(psSysData);
}
#endif
#if defined(SYS_USING_INTERRUPTS)
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_ENABLE_LISR))
{
eError = OSUninstallSystemLISR(psSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: OSUninstallSystemLISR failed"));
return eError;
}
}
#endif /* defined(SYS_USING_INTERRUPTS) */
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_ENABLE_MISR))
{
eError = OSUninstallMISR(psSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: OSUninstallMISR failed"));
return eError;
}
}
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_ENABLE_INITDEV))
{
/* de-initialise all services managed devices */
eError = PVRSRVDeinitialiseDevice (gui32SGXDeviceID);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: failed to de-init the device"));
return eError;
}
}
if (gpsSysData->pvSOCRegsBase)
{
OSUnMapPhysToLin(gpsSysData->pvSOCRegsBase,
SYS_ATLAS_REG_SIZE + SYS_PDP_REG_SIZE,
PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
IMG_NULL);
gpsSysData->pvSOCRegsBase = IMG_NULL;
}
/*
Destroy the local memory arena.
*/
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_ENABLE_RA_ARENA))
{
RA_Delete(gpsSysData->apsLocalDevMemArena[0]);
gpsSysData->apsLocalDevMemArena[0] = IMG_NULL;
}
SysDeinitialiseCommon(gpsSysData);
#ifdef __linux__
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_ENABLE_PCINIT))
{
PCIDeInitDev(psSysData);
}
#endif
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_ENABLE_ENVDATA))
{
eError = OSDeInitEnvData(gpsSysData->pvEnvSpecificData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: failed to de-init env structure"));
return eError;
}
}
#if defined(NO_HARDWARE)
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_ENABLE_REG_MEM))
{
OSBaseFreeContigMemory(SYS_SGX_REG_SIZE, gsSGXRegsCPUVAddr, gsSGXDeviceMap.sRegsCpuPBase);
}
#endif
psSysSpecData->ui32SysSpecificData = 0;
gpsSysData = IMG_NULL;
return PVRSRV_OK;
}
IMG_VOID DisableSystemClocks(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
IMG_BOOL bPowerLock;
#if defined(DEBUG) || defined(TIMING)
IMG_CPU_PHYADDR TimerRegPhysBase;
IMG_HANDLE hTimerDisable;
IMG_UINT32 *pui32TimerDisable;
#endif
PVR_TRACE(("DisableSystemClocks: Disabling System Clocks"));
DisableSGXClocks(psSysData);
bPowerLock = PowerLockWrappedOnCPU(psSysSpecData);
if (bPowerLock)
{
PowerLockUnwrap(psSysSpecData);
}
#if defined(PDUMP) && !defined(NO_HARDWARE) && defined(CONSTRAINT_NOTIFICATIONS)
{
int res;
PVR_TRACE(("DisableSystemClocks: Removing SGX OPP constraint"));
res = constraint_remove(psSysSpecData->pVdd2Handle);
if (res != 0)
{
PVR_DPF((PVR_DBG_WARNING, "DisableSystemClocks: constraint_remove failed (%d)", res));
}
}
#endif
#if defined(CONSTRAINT_NOTIFICATIONS)
UnRegisterConstraintNotifications();
#endif
#if defined(DEBUG) || defined(TIMING)
TimerRegPhysBase.uiAddr = SYS_TI81xx_GP7TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerDisable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerDisable);
if (pui32TimerDisable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSystemClocks: OSMapPhysToLin failed"));
}
else
{
*pui32TimerDisable = 0;
OSUnMapPhysToLin(pui32TimerDisable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerDisable);
}
clk_disable(psSysSpecData->psGPT11_ICK);
clk_disable(psSysSpecData->psGPT11_FCK);
#endif
#if defined(CONSTRAINT_NOTIFICATIONS)
constraint_put(psSysSpecData->pVdd2Handle);
#endif
if (bPowerLock)
{
PowerLockWrap(psSysSpecData);
}
}
PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData)
{
PVRSRV_ERROR eError;
#if defined(SYS_USING_INTERRUPTS)
if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LISR))
{
eError = OSUninstallDeviceLISR(psSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: OSUninstallDeviceLISR failed"));
return eError;
}
}
#endif
if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_MISR))
{
eError = OSUninstallMISR(psSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: OSUninstallMISR failed"));
return eError;
}
}
if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_INITDEV))
{
#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT)
PVR_ASSERT(SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_SYSCLOCKS));
eError = EnableSGXClocksWrap(gpsSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: EnableSGXClocks failed"));
return eError;
}
#endif
eError = PVRSRVDeinitialiseDevice (gui32SGXDeviceID);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: failed to de-init the device"));
return eError;
}
}
#if defined(SGX_OCP_REGS_ENABLED)
if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_OCPREGS))
{
OSUnMapPhysToLin(gpvOCPRegsLinAddr,
SYS_OMAP3430_OCP_REGS_SIZE,
PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
IMG_NULL);
}
#endif
if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_SYSCLOCKS))
{
DisableSystemClocks(gpsSysData);
}
if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_ENVDATA))
{
eError = OSDeInitEnvData(gpsSysData->pvEnvSpecificData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: failed to de-init env structure"));
return eError;
}
}
if(gpsSysData->pvSOCTimerRegisterKM)
{
OSUnReservePhys(gpsSysData->pvSOCTimerRegisterKM,
4,
PVRSRV_HAP_MULTI_PROCESS|PVRSRV_HAP_UNCACHED,
gpsSysData->hSOCTimerRegisterOSMemHandle);
}
SysDeinitialiseCommon(gpsSysData);
#if defined(NO_HARDWARE)
if(SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LOCATEDEV))
{
OSBaseFreeContigMemory(SYS_OMAP3430_SGX_REGS_SIZE, gsSGXRegsCPUVAddr, gsSGXDeviceMap.sRegsCpuPBase);
}
#endif
gpsSysSpecificData->ui32SysSpecificData = 0;
gpsSysSpecificData->bSGXInitComplete = IMG_FALSE;
gpsSysData = IMG_NULL;
return PVRSRV_OK;
}
enum PVRSRV_ERROR PVRSRVSaveRestoreLiveSegments(void *hArena, u8 *pbyBuffer,
u32 *puiBufSize, IMG_BOOL bSave)
{
u32 uiBytesSaved = 0;
void *pvLocalMemCPUVAddr;
struct RA_SEGMENT_DETAILS sSegDetails;
if (hArena == NULL)
return PVRSRV_ERROR_INVALID_PARAMS;
sSegDetails.uiSize = 0;
sSegDetails.sCpuPhyAddr.uiAddr = 0;
sSegDetails.hSegment = NULL;
while (RA_GetNextLiveSegment(hArena, &sSegDetails))
if (pbyBuffer == NULL) {
uiBytesSaved +=
sizeof(sSegDetails.uiSize) + sSegDetails.uiSize;
} else {
if ((uiBytesSaved + sizeof(sSegDetails.uiSize) +
sSegDetails.uiSize) > *puiBufSize)
return PVRSRV_ERROR_OUT_OF_MEMORY;
PVR_DPF(PVR_DBG_MESSAGE,
"PVRSRVSaveRestoreLiveSegments: "
"Base %08x size %08x",
sSegDetails.sCpuPhyAddr.uiAddr,
sSegDetails.uiSize);
pvLocalMemCPUVAddr = (void __force *)
OSMapPhysToLin(sSegDetails.sCpuPhyAddr,
sSegDetails.uiSize,
PVRSRV_HAP_KERNEL_ONLY |
PVRSRV_HAP_UNCACHED, NULL);
if (pvLocalMemCPUVAddr == NULL) {
PVR_DPF(PVR_DBG_ERROR,
"PVRSRVSaveRestoreLiveSegments: "
"Failed to map local memory to host");
return PVRSRV_ERROR_OUT_OF_MEMORY;
}
if (bSave) {
OSMemCopy(pbyBuffer, &sSegDetails.uiSize,
sizeof(sSegDetails.uiSize));
pbyBuffer += sizeof(sSegDetails.uiSize);
OSMemCopy(pbyBuffer, pvLocalMemCPUVAddr,
sSegDetails.uiSize);
pbyBuffer += sSegDetails.uiSize;
} else {
u32 uiSize;
OSMemCopy(&uiSize, pbyBuffer,
sizeof(sSegDetails.uiSize));
if (uiSize != sSegDetails.uiSize) {
PVR_DPF(PVR_DBG_ERROR,
"PVRSRVSaveRestoreLiveSegments:"
" Segment size error");
} else {
pbyBuffer += sizeof(sSegDetails.uiSize);
OSMemCopy(pvLocalMemCPUVAddr, pbyBuffer,
sSegDetails.uiSize);
pbyBuffer += sSegDetails.uiSize;
}
}
uiBytesSaved +=
sizeof(sSegDetails.uiSize) + sSegDetails.uiSize;
OSUnMapPhysToLin((void __force __iomem *)
pvLocalMemCPUVAddr,
sSegDetails.uiSize,
PVRSRV_HAP_KERNEL_ONLY |
PVRSRV_HAP_UNCACHED, NULL);
}
if (pbyBuffer == NULL)
*puiBufSize = uiBytesSaved;
return PVRSRV_OK;
}
PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
struct clk *psCLK;
IMG_INT res;
PVRSRV_ERROR eError;
#if defined(DEBUG) || defined(TIMING)
IMG_INT rate;
struct clk *sys_ck;
IMG_CPU_PHYADDR TimerRegPhysBase;
IMG_HANDLE hTimerEnable;
IMG_UINT32 *pui32TimerEnable;
#endif
PVR_TRACE(("EnableSystemClocks: Enabling System Clocks"));
if (!psSysSpecData->bSysClocksOneTimeInit)
{
mutex_init(&psSysSpecData->sPowerLock);
atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
psCLK = clk_get(NULL, SGX_PARENT_CLOCK);
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSsystemClocks: Couldn't get Core Clock"));
goto ExitError;
}
psSysSpecData->psCORE_CK = psCLK;
psCLK = clk_get(NULL, "sgx_fck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSsystemClocks: Couldn't get SGX Functional Clock"));
goto ExitError;
}
psSysSpecData->psSGX_FCK = psCLK;
psCLK = clk_get(NULL, "sgx_ick");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get SGX Interface Clock"));
goto ExitError;
}
psSysSpecData->psSGX_ICK = psCLK;
#if defined(DEBUG)
psCLK = clk_get(NULL, "mpu_ck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get MPU Clock"));
goto ExitError;
}
psSysSpecData->psMPU_CK = psCLK;
#endif
res = clk_set_parent(psSysSpecData->psSGX_FCK, psSysSpecData->psCORE_CK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set SGX parent clock (%d)", res));
goto ExitError;
}
psSysSpecData->bSysClocksOneTimeInit = IMG_TRUE;
}
#if defined(DEBUG) || defined(TIMING)
psCLK = clk_get(NULL, "gpt11_fck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock"));
goto ExitUnRegisterConstraintNotifications;
}
psSysSpecData->psGPT11_FCK = psCLK;
psCLK = clk_get(NULL, "gpt11_ick");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock"));
goto ExitUnRegisterConstraintNotifications;
}
psSysSpecData->psGPT11_ICK = psCLK;
sys_ck = clk_get(NULL, "sys_ck");
if (IS_ERR(sys_ck))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get System clock"));
goto ExitUnRegisterConstraintNotifications;
}
if(clk_get_parent(psSysSpecData->psGPT11_FCK) != sys_ck)
{
PVR_TRACE(("Setting GPTIMER11 parent to System Clock"));
res = clk_set_parent(psSysSpecData->psGPT11_FCK, sys_ck);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set GPTIMER11 parent clock (%d)", res));
goto ExitUnRegisterConstraintNotifications;
}
}
rate = clk_get_rate(psSysSpecData->psGPT11_FCK);
PVR_TRACE(("GPTIMER11 clock is %dMHz", HZ_TO_MHZ(rate)));
res = clk_enable(psSysSpecData->psGPT11_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res));
goto ExitUnRegisterConstraintNotifications;
}
res = clk_enable(psSysSpecData->psGPT11_ICK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 interface clock (%d)", res));
goto ExitDisableGPT11FCK;
}
TimerRegPhysBase.uiAddr = SYS_TI81xx_GP7TIMER_TSICR_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
rate = *pui32TimerEnable;
if(!(rate & 4))
{
PVR_TRACE(("Setting GPTIMER11 mode to posted (currently is non-posted)"));
*pui32TimerEnable = rate | 4;
}
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
TimerRegPhysBase.uiAddr = SYS_TI81xx_GP7TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
*pui32TimerEnable = 3;
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
#endif
eError = PVRSRV_OK;
goto Exit;
#if defined(DEBUG) || defined(TIMING)
ExitDisableGPT11ICK:
clk_disable(psSysSpecData->psGPT11_ICK);
ExitDisableGPT11FCK:
clk_disable(psSysSpecData->psGPT11_FCK);
ExitUnRegisterConstraintNotifications:
#endif
ExitError:
eError = PVRSRV_ERROR_DISABLE_CLOCK_FAILURE;
Exit:
return eError;
}
/*!
******************************************************************************
@Function PVRSRVSaveRestoreLiveSegments
@Input pArena - the arena the segment was originally allocated from.
pbyBuffer - the system memory buffer set to null to get the size needed.
puiBufSize - size of system memory buffer.
bSave - IMG_TRUE if a save is required
@Description
Function to save or restore Resources Live segments
******************************************************************************/
PVRSRV_ERROR IMG_CALLCONV PVRSRVSaveRestoreLiveSegments(IMG_HANDLE hArena, IMG_PBYTE pbyBuffer,
IMG_SIZE_T *puiBufSize, IMG_BOOL bSave)
{
IMG_SIZE_T uiBytesSaved = 0;
IMG_PVOID pvLocalMemCPUVAddr;
RA_SEGMENT_DETAILS sSegDetails;
if (hArena == IMG_NULL)
{
return (PVRSRV_ERROR_INVALID_PARAMS);
}
sSegDetails.uiSize = 0;
sSegDetails.sCpuPhyAddr.uiAddr = 0;
sSegDetails.hSegment = 0;
/* walk the arena segments and write live one to the buffer */
while (RA_GetNextLiveSegment(hArena, &sSegDetails))
{
if (pbyBuffer == IMG_NULL)
{
/* calc buffer required */
uiBytesSaved += sizeof(sSegDetails.uiSize) + sSegDetails.uiSize;
}
else
{
if ((uiBytesSaved + sizeof(sSegDetails.uiSize) + sSegDetails.uiSize) > *puiBufSize)
{
return (PVRSRV_ERROR_OUT_OF_MEMORY);
}
PVR_DPF((
PVR_DBG_MESSAGE,
"PVRSRVSaveRestoreLiveSegments: Base " CPUPADDR_FMT " size %" SIZE_T_FMT_LEN "x",
sSegDetails.sCpuPhyAddr.uiAddr,
sSegDetails.uiSize));
/* Map the device's local memory area onto the host. */
pvLocalMemCPUVAddr = OSMapPhysToLin(sSegDetails.sCpuPhyAddr,
sSegDetails.uiSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
if (pvLocalMemCPUVAddr == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVSaveRestoreLiveSegments: Failed to map local memory to host"));
return (PVRSRV_ERROR_OUT_OF_MEMORY);
}
if (bSave)
{
/* write segment size then segment data */
OSMemCopy(pbyBuffer, &sSegDetails.uiSize, sizeof(sSegDetails.uiSize));
pbyBuffer += sizeof(sSegDetails.uiSize);
OSMemCopy(pbyBuffer, pvLocalMemCPUVAddr, sSegDetails.uiSize);
pbyBuffer += sSegDetails.uiSize;
}
else
{
IMG_UINT32 uiSize;
/* reag segment size and validate */
OSMemCopy(&uiSize, pbyBuffer, sizeof(sSegDetails.uiSize));
if (uiSize != sSegDetails.uiSize)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVSaveRestoreLiveSegments: Segment size error"));
}
else
{
pbyBuffer += sizeof(sSegDetails.uiSize);
OSMemCopy(pvLocalMemCPUVAddr, pbyBuffer, sSegDetails.uiSize);
pbyBuffer += sSegDetails.uiSize;
}
}
uiBytesSaved += sizeof(sSegDetails.uiSize) + sSegDetails.uiSize;
OSUnMapPhysToLin(pvLocalMemCPUVAddr,
sSegDetails.uiSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
}
}
if (pbyBuffer == IMG_NULL)
{
*puiBufSize = uiBytesSaved;
}
return (PVRSRV_OK);
}
PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData)
{
PVRSRV_ERROR eError;
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
#if (defined(SYS_USING_INTERRUPTS) && !defined(SUPPORT_DRI_DRM_EXT))
if (SYS_SPECIFIC_DATA_TEST(&gsSysSpecificData, SYS_SPECIFIC_DATA_IRQ_ENABLED))
{
SysDisableInterrupts(psSysData);
}
#endif
#if defined(SYS_USING_INTERRUPTS) && !defined(SUPPORT_DRI_DRM_EXT)
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_LISR_INSTALLED))
{
eError = OSUninstallSystemLISR(psSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: OSUninstallSystemLISR failed"));
return eError;
}
}
#endif
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_MISR_INSTALLED))
{
eError = OSUninstallMISR(psSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: OSUninstallMISR failed"));
return eError;
}
}
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_SGX_INITIALISED))
{
eError = PVRSRVDeinitialiseDevice(gui32SGXDeviceID);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: failed to de-init the device"));
return eError;
}
}
SysFreeVersionString(psSysData);
PCIDeInitDev(psSysData);
eError = OSDeInitEnvData(psSysData->pvEnvSpecificData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: failed to de-init env structure"));
return eError;
}
SysDeinitialiseCommon(gpsSysData);
#if !defined(NO_HARDWARE)
OSUnMapPhysToLin(gsPoulsboRegsCPUVaddr,
POULSBO_REG_SIZE,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
OSUnMapPhysToLin(gsPoulsboDisplayRegsCPUVaddr,
POULSBO_DISPLAY_REG_SIZE,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
#endif
if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_PDUMP_INIT))
{
PDUMPDEINIT();
}
gpsSysData = IMG_NULL;
return PVRSRV_OK;
}
/*
EmuReset
*/
static PVRSRV_ERROR EmuReset(IMG_CPU_PHYADDR sRegsCpuPBase)
{
IMG_CPU_PHYADDR sWrapperRegsCpuPBase;
IMG_VOID *pvWrapperRegs;
IMG_UINT32 ui32MemLatency;
sWrapperRegsCpuPBase.uiAddr = sRegsCpuPBase.uiAddr + EMULATOR_RGX_REG_WRAPPER_OFFSET;
/*
Create a temporary mapping of the wrapper registers in order to reset
the emulator design.
*/
pvWrapperRegs = OSMapPhysToLin(sWrapperRegsCpuPBase,
EMULATOR_RGX_REG_WRAPPER_SIZE,
0);
if (pvWrapperRegs == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR,"EmuReset: Failed to create wrapper register mapping\n"));
return PVRSRV_ERROR_BAD_MAPPING;
}
/*
Set the memory latency. This needs to be done before the soft reset to ensure
it applies to all aspects of the emulator.
*/
ui32MemLatency = EmuMemLatencyGet();
if (ui32MemLatency != 0)
{
PVR_LOG(("EmuReset: Mem latency = 0x%X", ui32MemLatency));
}
OSWriteHWReg32(pvWrapperRegs, EMU_CR_MEMORY_LATENCY, ui32MemLatency);
(void) OSReadHWReg32(pvWrapperRegs, EMU_CR_MEMORY_LATENCY);
/*
Emu reset.
*/
OSWriteHWReg32(pvWrapperRegs, EMU_CR_SOFT_RESET, EMU_CR_SOFT_RESET_SYS_EN|EMU_CR_SOFT_RESET_MEM_EN|EMU_CR_SOFT_RESET_CORE_EN);
/* Flush register write */
(void) OSReadHWReg32(pvWrapperRegs, EMU_CR_SOFT_RESET);
OSWaitus(10);
OSWriteHWReg32(pvWrapperRegs, EMU_CR_SOFT_RESET, 0x0);
/* Flush register write */
(void) OSReadHWReg32(pvWrapperRegs, EMU_CR_SOFT_RESET);
OSWaitus(10);
#if !defined(LMA)
/* If we're UMA then enable bus mastering */
OSWriteHWReg32(pvWrapperRegs, EMU_CR_PCI_MASTER, EMU_CR_PCI_MASTER_MODE_EN);
#else
/* otherwise disable it: the emu regbank is not resetable */
OSWriteHWReg32(pvWrapperRegs, EMU_CR_PCI_MASTER, 0x0);
#endif
/* Flush register write */
(void) OSReadHWReg32(pvWrapperRegs, EMU_CR_PCI_MASTER);
/*
Remove the temporary register mapping.
*/
OSUnMapPhysToLin(pvWrapperRegs, EMULATOR_RGX_REG_WRAPPER_SIZE, 0);
return PVRSRV_OK;
}
/*!
******************************************************************************
@Function SysDeinitialise
@Description De-initialises kernel services at 'driver unload' time
@Return PVRSRV_ERROR
******************************************************************************/
PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData)
{
PVRSRV_ERROR eError;
PVR_UNREFERENCED_PARAMETER(psSysData);
if(gpsSysData->pvSOCTimerRegisterKM)
{
OSUnReservePhys(gpsSysData->pvSOCTimerRegisterKM,
4,
PVRSRV_HAP_MULTI_PROCESS|PVRSRV_HAP_UNCACHED,
gpsSysData->hSOCTimerRegisterOSMemHandle);
}
#if defined(SYS_USING_INTERRUPTS)
if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LISR))
{
eError = OSUninstallDeviceLISR(gpsSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: OSUninstallDeviceLISR failed"));
return eError;
}
}
#endif
if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_MISR))
{
eError = OSUninstallMISR(gpsSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: OSUninstallMISR failed"));
return eError;
}
}
if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_INITDEV))
{
#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT)
PVR_ASSERT(SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_SYSCLOCKS));
/* Reenable SGX clocks whilst SGX is being deinitialised. */
eError = EnableSGXClocksWrap(gpsSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: EnableSGXClocks failed"));
return eError;
}
#endif /* SUPPORT_ACTIVE_POWER_MANAGEMENT */
/* Deinitialise SGX */
eError = PVRSRVDeinitialiseDevice(gui32SGXDeviceID);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: failed to de-init the device"));
return eError;
}
}
/* Disable system clocks. Must happen after last access to hardware */
if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_SYSCLOCKS))
{
DisableSystemClocks(gpsSysData);
}
if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_DVFS_INIT))
{
eError = SysDvfsDeinitialize(gpsSysSpecificData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: Failed to de-init DVFS"));
gpsSysData = IMG_NULL;
return eError;
}
}
if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_PM_RUNTIME))
{
eError = SysPMRuntimeUnregister();
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: Failed to unregister with OSPM!"));
gpsSysData = IMG_NULL;
return eError;
}
}
if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_ENVDATA))
{
eError = OSDeInitEnvData(gpsSysData->pvEnvSpecificData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: failed to de-init env structure"));
return eError;
}
}
SysDeinitialiseCommon(gpsSysData);
#if defined(NO_HARDWARE) || defined(SGX_OCP_REGS_ENABLED)
if(gsSGXRegsCPUVAddr != IMG_NULL)
{
#if defined(NO_HARDWARE)
/* Free hardware resources. */
OSBaseFreeContigMemory(SYS_OMAP3630_SGX_REGS_SIZE, gsSGXRegsCPUVAddr, gsSGXDeviceMap.sRegsCpuPBase);
#else
#if defined(SGX_OCP_REGS_ENABLED)
OSUnMapPhysToLin(gsSGXRegsCPUVAddr,
gsSGXDeviceMap.ui32RegsSize,
PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
IMG_NULL);
gpvOCPRegsLinAddr = IMG_NULL;
#endif
#endif /* defined(NO_HARDWARE) */
gsSGXRegsCPUVAddr = IMG_NULL;
gsSGXDeviceMap.pvRegsCpuVBase = gsSGXRegsCPUVAddr;
}
#endif /* defined(NO_HARDWARE) || defined(SGX_OCP_REGS_ENABLED) */
gpsSysSpecificData->ui32SysSpecificData = 0;
gpsSysSpecificData->bSGXInitComplete = IMG_FALSE;
gpsSysData = IMG_NULL;
return PVRSRV_OK;
}
/***********************************************************************//**
* Unmap the CPU virtual memory from the registers
*
* @returns PVRSRV_OK for success, or failure code
**************************************************************************/
static PVRSRV_ERROR SysUnmapRegisters(void)
{
PVRSRV_DEVICE_NODE *psDeviceNodeList;
psDeviceNodeList = gpsSysData->psDeviceNodeList;
while (psDeviceNodeList)
{
switch (psDeviceNodeList->sDevId.eDeviceType)
{
case PVRSRV_DEVICE_TYPE_SGX:
{
PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *)
psDeviceNodeList->pvDevice;
#if !defined(NO_HARDWARE)
/* Unmap Regs */
if (psDevInfo->pvRegsBaseKM)
{
OSUnMapPhysToLin(psDevInfo->pvRegsBaseKM,
gsSGXDeviceMap.ui32RegsSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_PM_UNMAP_SGX_REGS);
}
#endif
psDevInfo->pvRegsBaseKM = IMG_NULL;
psDevInfo->ui32RegSize = 0;
psDevInfo->sRegsPhysBase.uiAddr = 0;
break;
}
#ifdef SUPPORT_MSVDX
case PVRSRV_DEVICE_TYPE_MSVDX:
{
PVRSRV_MSVDXDEV_INFO *psDevInfo = (PVRSRV_MSVDXDEV_INFO *)
psDeviceNodeList->pvDevice;
#if !defined(NO_HARDWARE)
if (psDevInfo->pvRegsBaseKM)
{
OSUnMapPhysToLin(psDevInfo->pvRegsBaseKM,
psDevInfo->ui32RegSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_PM_UNMAP_MSVDX_REGS);
}
#endif
psDevInfo->pvRegsBaseKM = IMG_NULL;
psDevInfo->ui32RegSize = 0;
psDevInfo->sRegsPhysBase.uiAddr = 0;
break;
}
#endif /* SUPPORT_MSVDX */
default:
/* Ignore unknowns */
break;
}
psDeviceNodeList = psDeviceNodeList->psNext;
}
#if defined(NO_HARDWARE)
#if defined(SUPPORT_MSVDX)
if (SYS_SPECIFIC_DATA_TEST(&gsSysSpecificData, SYS_SPECIFIC_DATA_DUMMY_MSVDX_REGS))
{
PVR_ASSERT(gsMSVDXDeviceMap);
OSBaseFreeContigMemory(MSVDX_REG_SIZE,
gsMSVDXDeviceMap.sRegsCpuVBase,
gsMSVDXDeviceMap.sRegsCpuPBase);
SYS_SPECIFIC_DATA_CLEAR(&gsSysSpecificData, SYS_SPECIFIC_DATA_DUMMY_MSVDX_REGS);
}
#endif /* defined(SUPPORT_MSVDX) */
if (SYS_SPECIFIC_DATA_TEST(&gsSysSpecificData, SYS_SPECIFIC_DATA_DUMMY_SGX_REGS))
{
OSBaseFreeContigMemory(SYS_SGX_REG_SIZE,
gsSGXDeviceMap.pvRegsCpuVBase,
gsSGXDeviceMap.sRegsCpuPBase);
SYS_SPECIFIC_DATA_CLEAR(&gsSysSpecificData, SYS_SPECIFIC_DATA_DUMMY_SGX_REGS);
}
#endif /* defined(NO_HARDWARE) */
#if !defined(NO_HARDWARE)
if (SYS_SPECIFIC_DATA_TEST(&gsSysSpecificData, SYS_SPECIFIC_DATA_SOC_REGS_MAPPED))
{
OSUnMapPhysToLin(gsSOCDeviceMap.sRegsCpuVBase,
SYS_SOC_REG_SIZE,
PVRSRV_HAP_KERNEL_ONLY | PVRSRV_HAP_UNCACHED,
IMG_NULL);
SYS_SPECIFIC_DATA_CLEAR(&gsSysSpecificData, SYS_SPECIFIC_DATA_SOC_REGS_MAPPED);
}
#endif
return PVRSRV_OK;
}
