////////////////////////////////////////////////////
// 功能: codec 寄存器写入
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
static void codec_reg_write(unsigned char addr, unsigned char data)
{
unsigned int temp;
temp = (addr << RGADW_ADDR_BIT) | (data << RGADW_DATA_BIT);
AIC_RW_CODEC_START();
OUTREG32(AIC_RGADW, temp);
OUTREG32(AIC_RGADW, (temp | AIC_RGADW_RGWR));
AIC_RW_CODEC_STOP();
}
DPI_STATUS DPI_Init(BOOL isDpiPoweredOn)
{
DPI_REG_CNTL cntl;
if (isDpiPoweredOn) {
_BackupDPIRegisters();
// s_isDpiPowerOn = TRUE;
} else {
_ResetBackupedDPIRegisterValues();
// DPI_PowerOn();
}
DPI_PowerOn();
// Always enable frame shift protection and recovery
cntl = DPI_REG->CNTL;
cntl.FS_PROT_EN = 1;
cntl.FS_RC_EN = 1;
// Enable adaptive FIFO high/low threshold control
cntl.ADP_EN = 1;
OUTREG32(&DPI_REG->CNTL, AS_UINT32(&cntl));
// Config ultra high threshold water mark
{
DPI_REG_FIFO_TH th = DPI_REG->FIFO_TH;
th.LOW = 64;
th.HIGH = 128;
OUTREG32(&DPI_REG->FIFO_TH, AS_UINT32(&th));
DPI_REG->FIFO_INC = 8;
}
#if ENABLE_DPI_INTERRUPT
if (request_irq(MT6573_DPI_IRQ_LINE,
_DPI_InterruptHandler, 0, MTKFB_DRIVER, NULL) < 0)
{
printk("[DPI][ERROR] fail to request DPI irq\n");
return DPI_STATUS_ERROR;
}
{
DPI_REG_INTERRUPT enInt = DPI_REG->INT_ENABLE;
enInt.FIFO_EMPTY = 1;
enInt.VSYNC = 1;
OUTREG32(&DPI_REG->INT_ENABLE, AS_UINT32(&enInt));
}
#endif
return DPI_STATUS_OK;
}
void TVC_ConfigSize(unsigned int src_width, unsigned int src_height, unsigned int tar_width, unsigned int tar_height)
{
_SIZE tarSize = {0};
TV_INFO("src %d, %d, tar %d, %d\n", src_width, src_height, tar_width, tar_height);
//src size
if (_tvcContext.srcSize.width != src_width ||
_tvcContext.srcSize.height != src_height)
{
_tvcContext.srcSize.width = src_width;
_tvcContext.srcSize.height = src_height;
_tvcContext.srcFormatSizeDirty = TRUE;
}
// Config Source Size
OUTREG32(&TVC_REG->SRC_WIDTH, _tvcContext.srcSize.width);
OUTREG32(&TVC_REG->SRC_HEIGHT, _tvcContext.srcSize.height);
// Config Line Pitch
{
TVC_REG_LINE_OFFSET OFFSET = TVC_REG->LINE_OFFSET;
OFFSET.LINE_OFFSET = (TVC_YUV420_BLK == _tvcContext.srcFormat ||
TVC_YUV420_PLANAR == _tvcContext.srcFormat) ?
(_tvcContext.srcSize.width * 1) :
(_tvcContext.srcSize.width * 2);
OUTREG32(&TVC_REG->LINE_OFFSET, AS_UINT32(&OFFSET));
}
//tar size
tarSize.width = tar_width;
tarSize.height = tar_height;
_SetTarSize(tar_width, tar_height);
_tvcContext.tarSize = tarSize;
_SetResizCoeff(_tvcContext.srcSize, tarSize);
_ConfigFullDisplayRegion();
{
TVC_REG_UPDATE update = TVC_REG->REG_UPDATE;
update.REG_RDY = 1;
OUTREG32(&TVC_REG->REG_UPDATE, AS_UINT32(&update));
}
}
int Init_PerformanceCounter(void)
{
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TCU);
OUTREG16(A_TCU_TECR, TCU_OSTCL);
OUTREG32(A_OST_CSR, TCU_CLK_EXTAL | TCU_CLK_PRESCALE_CLK4);
OUTREG32(A_OST_DR, 0xFFFFFFFF);
OUTREG32(A_OST_CNT, 0);
SETREG32(A_TCU_TESR, TCU_OSTEN);
return ((OSC_CLOCK / 4 ) / 1000000);
}
TVC_STATUS TVC_SetSrcYUVAddr(UINT32 Y, UINT32 U, UINT32 V)
{
// check if all buffer addresses are 8-byte aligned
ASSERT((Y & 0x7) == 0);
ASSERT((U & 0x7) == 0);
ASSERT((V & 0x7) == 0);
OUTREG32(&TVC_REG->SRC_Y_ADDR, Y);
OUTREG32(&TVC_REG->SRC_U_ADDR, U);
OUTREG32(&TVC_REG->SRC_V_ADDR, V);
return TVC_STATUS_OK;
}
void JZ_InitIdleTimer(void (*handler)(unsigned int))
{
while(IdleTimer_Flag);
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TCU);
OUTREG16(A_TCU_TECR, TCU_TIMER(TCU_IDLE_TIMER_CHN));
OUTREG16(A_TCU_TCSR(TCU_IDLE_TIMER_CHN), TCU_CLK_EXTAL | TCU_CLK_PRESCALE_CLK256);
OUTREG16(A_TCU_TDFR(TCU_IDLE_TIMER_CHN), 0xffff);
OUTREG16(A_TCU_TDHR(TCU_IDLE_TIMER_CHN), 0xffff);
OUTREG16(A_TCU_TCNT(TCU_IDLE_TIMER_CHN), 0x0000);
OUTREG32(A_TCU_TFCR, TCU_INTR_FLAG(TCU_IDLE_TIMER_CHN));
OUTREG32(A_TCU_TMCR, TCU_INTR_FLAG(TCU_IDLE_TIMER_CHN));
request_irq(EIRQ_TCU2_BASE + TCU_IDLE_TIMER_CHN, handler, 0);
}
DPI_STATUS DPI1_EnableClk()
{
DPI_REG_EN en = DPI1_REG->DPI_EN;
en.EN = 1;
OUTREG32(&DPI1_REG->DPI_EN, AS_UINT32(&en));
//release mutex0
//#ifndef BUILD_UBOOT
#if 0
OUTREG32(DISP_MUTEX_BASE + 0x24, 0);
while((INREG32(DISP_MUTEX_BASE + 0x24)&0x02)!=0){} // polling until mutex lock complete
#endif
return DPI_STATUS_OK;
}
DPI_STATUS DPI_ConfigHsync(DPI_POLARITY polarity, UINT32 pulseWidth, UINT32 backPorch,
UINT32 frontPorch)
{
DPI_REG_TGEN_HPORCH hporch = DPI_REG->TGEN_HPORCH;
hporch.HBP = backPorch;
hporch.HFP = frontPorch;
OUTREG32(&DPI_REG->TGEN_HWIDTH, AS_UINT32(&pulseWidth));
OUTREG32(&DPI_REG->TGEN_HPORCH, AS_UINT32(&hporch));
return DPI_STATUS_OK;
}
DPI_STATUS DPI_ConfigVsync(DPI_POLARITY polarity, UINT32 pulseWidth, UINT32 backPorch,
UINT32 frontPorch)
{
DPI_REG_TGEN_VPORCH vporch = DPI_REG->TGEN_VPORCH;
vporch.VBP = backPorch;
vporch.VFP = frontPorch;
OUTREG32(&DPI_REG->TGEN_VWIDTH, AS_UINT32(&pulseWidth));
OUTREG32(&DPI_REG->TGEN_VPORCH, AS_UINT32(&vporch));
return DPI_STATUS_OK;
}
void dma_nowait_cpyinit()
{
CLRREG32(A_CPM_CLKGR, ( 1 << 12 ));
SETREG32(A_DMA_DMAC(DMA_CPY_CHANNEL / 6),DMAC_DMA_EN);
OUTREG32(A_DMA_DCKE(DMA_CPY_CHANNEL / 6),(1 << (DMA_CPY_CHANNEL % 6)));//Open channel clock
CLRREG32(A_DMA_DMAC(DMA_CPY_CHANNEL / 6), (DMAC_HALT | DMAC_ADDR_ERR));//Ensure DMAC.AR = 0,DMAC.HLT = 0
CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_AR | DCS_HLT | DCS_TT | DCS_INV); // Ensure DCSn.AR = 0, DCSn.HLT = 0, DCSn.TT = 0, DCSn.INV = 0
OUTREG32(A_DMA_DTC(DMA_CPY_CHANNEL), 0);//DTCn = 0
CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_CTE);
SETREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_NDES);
}
unsigned int gpio_intr_init(GPIO_INTR_TRIGGER_TYPE gitt, unsigned int pin)
{
unsigned int base, bit;
if ((pin < NUM_GPIO) && (gitt < GITT_MAX))
{
base = GPIO_BASE_U_VIRTUAL + pin / 32 * 0x100;
bit = 1 << (pin % 32);
OUTREG32(base + GPIO_PXPIN_OFFSET, bit);
if ((gitt == GITT_F_EDGE) || (gitt == GITT_R_EDGE))
OUTREG32(base + GPIO_PXTRGS_OFFSET, bit); // Edge Trigger
else
OUTREG32(base + GPIO_PXTRGC_OFFSET, bit); // Level Trigger
OUTREG32(base + GPIO_PXFUNC_OFFSET, bit);
OUTREG32(base + GPIO_PXSELS_OFFSET, bit);
if ((gitt == GITT_R_EDGE) || (gitt == GITT_H_LEVEL))
OUTREG32(base + GPIO_PXDIRS_OFFSET, bit); // Rising Edge or High Level
else
OUTREG32(base + GPIO_PXDIRC_OFFSET, bit); // Falling Edge or Low Level
OUTREG32(base + GPIO_PXFLGC_OFFSET, bit);
return (1);
}
else
return (0);
}
void dma_copy_nowait(void *tar,void *src,int size)
{
int timeout = 0x1000000;
while ((!(INREG32(A_DMA_DCS(DMA_CPY_CHANNEL)) & DCS_TT)) && (timeout--));
CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_CTE);
OUTREG32(A_DMA_DSA(DMA_CPY_CHANNEL), PHYSADDR((unsigned long)src));
OUTREG32(A_DMA_DTA(DMA_CPY_CHANNEL), PHYSADDR((unsigned long)tar));
OUTREG32(A_DMA_DTC(DMA_CPY_CHANNEL), size / 32);
OUTREG32(A_DMA_DRT(DMA_CPY_CHANNEL), DRT_AUTO);
OUTREG32(A_DMA_DCM(DMA_CPY_CHANNEL), (DCM_SAI| DCM_DAI | DCM_SP_32BIT | DCM_DP_32BIT | DCM_TSZ_32BYTE));
CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL),(DCS_TT));
SETREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_CTE | DCS_NDES);
}
DSI_STATUS DSI_handle_TE(void)
{
unsigned int data_array;
//data_array=0x00351504;
//DSI_set_cmdq(&data_array, 1, 1);
//lcm_mdelay(10);
// RACT
//data_array=1;
//OUTREG32(&DSI_REG->DSI_RACK, data_array);
// TE + BTA
data_array=0x24;
DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] DSI_handle_TE TE + BTA !! \n");
OUTREG32(&DSI_CMDQ_REG->data0, data_array);
//DSI_CMDQ_REG->data0.byte0=0x24;
//DSI_CMDQ_REG->data0.byte1=0;
//DSI_CMDQ_REG->data0.byte2=0;
//DSI_CMDQ_REG->data0.byte3=0;
DSI_REG->DSI_CMDQ_SIZE.CMDQ_SIZE=1;
DSI_REG->DSI_START.DSI_START=0;
DSI_REG->DSI_START.DSI_START=1;
// wait TE Trigger status
// printk("[DISP] wait TE Trigger status !! \n");
// do
// {
lcm_mdelay(10);
data_array=INREG32(&DSI_REG->DSI_INTSTA);
DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] DSI INT state : %x !! \n", data_array);
data_array=INREG32(&DSI_REG->DSI_TRIG_STA);
DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] DSI TRIG TE status check : %x !! \n", data_array);
// } while(!(data_array&0x4));
// RACT
DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] DSI Set RACT !! \n");
data_array=1;
OUTREG32(&DSI_REG->DSI_RACK, data_array);
return DSI_STATUS_OK;
}
void pwm_set_duty(unsigned int chn, unsigned int percent)
{
unsigned int full_cycles;
static unsigned int old_percent=1;
if (percent == 108)
{
OUTREG16(A_TCU_TESR, TCU_TIMER(chn));
SETREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(chn));
return;
}
if (percent > 100)
{
printf("The percent of PWM should be within 100\n");
return;
}
if (percent == 0)
{
CLRREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(chn));
OUTREG16(A_TCU_TECR, TCU_TIMER(chn));
if(old_percent!=0)
{
__gpio_as_output(4*32+20+chn);
__gpio_clear_pin(4*32+20+chn);
}
old_percent=0;
}
else
{
if(old_percent==0)
{
OUTREG32(A_GPIO_PXFUNS(4), 1 << (20 + chn));
OUTREG32(A_GPIO_PXSELC(4), 1 << (20 + chn));
OUTREG32(A_GPIO_PXPES(4), 1 << (20 + chn));
}
full_cycles = INREG16(A_TCU_TDFR(chn));
CLRREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
OUTREG16(A_TCU_TDHR(chn), full_cycles - (full_cycles * percent) / 110);
OUTREG16(A_TCU_TCNT(chn), 0x0000);
OUTREG16(A_TCU_TESR, TCU_TIMER(chn));
SETREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
old_percent=percent;
}
}
//------------------------------------------------------------------------------
//
// Function: ConfigureNextProfilerCount
//
// Updates the profiler count (prepares the timer for the next timer event).
//
static void ConfigureNextProfilerCount(DWORD dwCountInterval)
{
DWORD dwTimerTemp;
if (!g_pProfilerISR) return;
// Change number of timer ticks in the period.
//
OUTREG32(&g_pPWMRegs->TCNTB2, dwCountInterval);
dwTimerTemp = INREG32(&g_pPWMRegs->TCON) & (~(0xf << 12));
OUTREG32(&g_pPWMRegs->TCON, dwTimerTemp | (2 << 12)); // Update TCVNTB2 and stop.
OUTREG32(&g_pPWMRegs->TCON, dwTimerTemp | (1 << 12)); // One-shot mode and start.
}
////////////////////////////////////////////////////
// 功能: 延迟N个豪秒
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
static void dma_start(unsigned int channel, unsigned int srcAddr, unsigned int dstAddr, unsigned int count, unsigned char mode)
{
#ifdef KPRINTF_DEF
kprintf("dma channle = %d\n",channel);
kprintf("source = %x, destion = %x, count = %x\n",srcAddr,dstAddr,count*16);
#endif
OUTREG32(A_DMA_DSA(channel), srcAddr); // DMA数据地址
OUTREG32(A_DMA_DTA(channel), dstAddr); // DMA目标地址
OUTREG32(A_DMA_DTC(channel), count / 16); // 传送DMA的数据组数，当前设置1组为16个数据
SETREG32(A_DMA_DCS(channel), DCS_CTE); // 开始DMA数据传送
//判断是否允许DMA中断
if( mode )
InterruptUnmask(IRQ_DMA_0 + channel, 0); // 允许DMA结束后，自动产生中断
}
//////////
// Function Name : OTGDevice_InitCore
// Function Desctiption : This function initializes OTG Link Core.
// Input : NONE
// Output : NONE
// Version :
void OTGDevice_InitCore(void)
{
OUTREG32(GAHBCFG, MODE_SLAVE|BURST_SINGLE|GBL_INT_UNMASK);
OUTREG32(GUSBCFG, 0<<15 // PHY Low Power Clock sel
|1<<14 // Non-Periodic TxFIFO Rewind Enable
|0x5<<10 // Turnaround time
|0<<9|0<<8 // [0:HNP disable, 1:HNP enable][ 0:SRP disable, 1:SRP enable] H1= 1,1
|0<<7 // Ulpi DDR sel
|0<<6 // 0: high speed utmi+, 1: full speed serial
|0<<4 // 0: utmi+, 1:ulpi
|1<<3 // phy i/f 0:8bit, 1:16bit
|0x7<<0 // HS/FS Timeout*
);
}
U32 PDrvCryptoUpdateDES(PUBLIC_CRYPTO_DES_DES3_CONTEXT * pDesDes3Ctx,
U8 * pSrc,
U8 * pDest,
U32 nbBlocks,
U32 dmaUse)
{
U32 nbr_of_blocks;
U8 * pProcessSrc;
U8 * pProcessDest;
U32 vTemp;
pProcessSrc = pSrc;
pProcessDest = pDest;
if ((dmaUse == PUBLIC_CRYPTO_DMA_USE_POLLING) || (dmaUse == PUBLIC_CRYPTO_DMA_USE_IRQ)) {
return PDrvCryptoUpdateDESWithDMA(pDesDes3Ctx, pSrc, pDest, nbBlocks, dmaUse);
}
for (nbr_of_blocks = 0; nbr_of_blocks < nbBlocks ; nbr_of_blocks++) {
/* (2) : We wait for the input ready */
if (scxPublicCryptoWaitForReadyBit((VU32 *) &g_pDESReg_t->DES_CTRL, DES_CTRL_INPUT_READY_BIT) != PUBLIC_CRYPTO_OPERATION_SUCCESS) {
return PUBLIC_CRYPTO_ERR_TIMEOUT;
}
/* (3) : We copy the 8 bytes of data src->reg */
vTemp = (U32) BYTES_TO_LONG(pProcessSrc);
OUTREG32(&g_pDESReg_t->DES_DATA_L, vTemp);
pProcessSrc += 4;
vTemp = (U32) BYTES_TO_LONG(pProcessSrc);
OUTREG32(&g_pDESReg_t->DES_DATA_H, vTemp);
pProcessSrc += 4;
/* (4) : We wait for the output ready */
if (scxPublicCryptoWaitForReadyBit((VU32 *) &g_pDESReg_t->DES_CTRL, DES_CTRL_OUTPUT_READY_BIT) != PUBLIC_CRYPTO_OPERATION_SUCCESS) {
return PUBLIC_CRYPTO_ERR_TIMEOUT;
}
/* (5) : We copy the 8 bytes of data reg->dest */
vTemp = INREG32(&g_pDESReg_t->DES_DATA_L);
LONG_TO_BYTE(pProcessDest, vTemp);
pProcessDest += 4;
vTemp = INREG32(&g_pDESReg_t->DES_DATA_H);
LONG_TO_BYTE(pProcessDest, vTemp);
pProcessDest += 4;
}
return PUBLIC_CRYPTO_OPERATION_SUCCESS;
}
void LcdPdd_LCD_Initialize(void){
unsigned int val = 0;
val = INREG32(0x4a009120);//CM_DSS_DSS_CLKCTRL
val = val & ~(0x0502);
// Setup the DSS1 clock divider - disable DSS1 clock, change divider, enable DSS clock
OUTREG32(0x4a009120, val);//CM_DSS_DSS_CLKCTRL
udelay(10000);
SETREG32(0x4a00815c, 8<<0);//CM_DIV_M5_DPLL_PER
udelay(10000);
//printf("CM_CLKSEL_DSS= %x\n",INREG32(CM_CLKSEL_DSS));
val = INREG32(0x4a009120) ;//CM_DSS_DSS_CLKCTRL
val = val | 0x0502;
OUTREG32(0x4a009120, 0x00000502);
udelay(10000);
// LCD control xxxx xxxx xxxx 0000 0000 0010 0000 1001
OUTREG32(0x48041238, DISPC_CONTROL_TFTDATALINES_24 | DISPC_CONTROL_STNTFT);//DISPC_CONTROL2
// Default Color
OUTREG32(0x480413ac, 0x00000000);//DISPC_DEFAULT_COLOR2
// LCD control xxxx xxxx xxxx 0000 0000 0010 0000 1001
SETREG32(0x48041238, 0<<12);//DISPC_CONTROL2 OVERLAYOPTIMIZATION
// Default Transparency Color
OUTREG32(0x480413b0, 0);//DISPC_TRANS_COLOR2
SETREG32(0x48041044, 0x4<<0);//DISPC_CONFIG1 LOAD_MODE: Frame data only loaded every frame
////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Signal configuration
// OUTREG32(0x48041408,DISPC_POL_FREQ_ONOFF);//DISPC_POL_FREQ2
OUTREG32(0x48041408,0x00003000);//DISPC_POL_FREQ2
udelay(10000);
// Configure the divisor
OUTREG32(0x4804140c,DISPC_DIVISOR_R(LCD_PIXCLKDIV,LCD_LOGCLKDIV));//DISPC_DIVISOR2 (PCD 4,LCD 1)
// Configure the panel size
OUTREG32(0x480413cc,DISPC_SIZE_LCD_R(LCD_HEIGHT,LCD_WIDTH));//DISPC_SIZE_LCD2 (1024,600)
// Timing logic for HSYNC signal
OUTREG32(0x48041400,DISPC_TIMING(LCD_HSW-1,LCD_HFP-1,LCD_HBP-1));//DISPC_TIMING_H2
// Timing logic for VSYNC signal
OUTREG32(0x48041404,DISPC_TIMING(LCD_VSW-1,LCD_VFP,LCD_VBP));//DISPC_TIMING_V2
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
}
void DSI_clk_HS_mode(bool enter)
{
DSI_PHY_LCCON_REG tmp_reg1 = DSI_REG->DSI_PHY_LCCON;
if(enter && !DSI_clk_HS_state()) {
tmp_reg1.LC_HS_TX_EN=1;
OUTREG32(&DSI_REG->DSI_PHY_LCCON, AS_UINT32(&tmp_reg1));
//lcm_mdelay(1);
}
else if (!enter && DSI_clk_HS_state()) {
tmp_reg1.LC_HS_TX_EN=0;
OUTREG32(&DSI_REG->DSI_PHY_LCCON, AS_UINT32(&tmp_reg1));
//lcm_mdelay(1);
}
}
static void idle_timerhandle(unsigned int arg)
{
OUTREG32(A_TCU_TFCR, TCU_INTR_FLAG(TCU_IDLE_TIMER_CHN));
JZ_StopTimerEx(TCU_IDLE_TIMER_CHN);
IdleTimer_Flag=0;
free_irq(EIRQ_TCU2_BASE + TCU_IDLE_TIMER_CHN);
}
//----------------------------------------------------------------------------
void StopAssistTimer()
{
OUTREG16(A_TCU_TECR, TCU_TIMER(TCU_IDLE_TIMER_CHN));
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(TCU_IDLE_TIMER_CHN));
OUTREG16(A_TCU_TCNT(TCU_IDLE_TIMER_CHN), 0x0000);
free_irq(EIRQ_TCU2_BASE + TCU_IDLE_TIMER_CHN);
}
static TVC_STATUS _SetDisplayRegion(UINT32 startPixel, UINT32 startLine,
UINT32 stopPixel, UINT32 stopLine)
{
TVC_REG_POINT START = TVC_REG->START_POINT;
TVC_REG_POINT STOP = TVC_REG->STOP_POINT;
START.PIXEL = startPixel;
START.LINE = startLine;
STOP.PIXEL = stopPixel;
STOP.LINE = stopLine;
OUTREG32(&TVC_REG->START_POINT, AS_UINT32(&START));
OUTREG32(&TVC_REG->STOP_POINT, AS_UINT32(&STOP));
return TVC_STATUS_OK;
}
////////////////////////////////////////////////////
// 功能: 关闭声音设备
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
void CloseMediaDevice(char channel)
{
int arg;
int time;
arg = ((channel == 0) ? RECORD_CHANNEL : PLAYBACK_CHANNEL );
//等待DMA结束
time = 0;
while( INREG32(A_DMA_DTC(arg)) )
{
#ifdef KPRINTF_DEF
kprintf("close media device : count = %x\n",INREG32(A_DMA_DTC(arg)));
#endif
sTimerSleep(10, NULL);
//加入延迟处理，防止死锁
time++;
if( time > 10 )
{
kdebug(mod_media, PRINT_WARNING, "close media device timer out\n");
break;
}
}
//stop dma
CLRREG32(A_DMA_DCS(arg), DCS_AR | DCS_HLT | DCS_CTE | DCS_CT);
//close aic
CLRREG32(AIC_CR, AIC_CR_ERPL);
SETREG32(AIC_CR, AIC_CR_FLUSH_FIFO);
OUTREG32(AIC_SR, 0x00000000);
#ifndef CODEC_ALWAYS_OPEN
CloseMediaCodecDevice();
#endif
}
////////////////////////////////////////////////////
// 功能: 音频初始化
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
static void jz_audio_reset(void)
{
CLRREG32(AIC_CR, AIC_CR_ERPL | AIC_CR_EREC);
SETREG32(AIC_CR, AIC_CR_FLUSH_FIFO);
OUTREG32(AIC_SR, 0x00000000);
}
//----------------------------------------------------------------------------
static void delayupdate(unsigned int *addr)
{ int rest,t,i,flag=0,counter2 = 0;
//JZ_StopTimerEx(TCU_IDLE_TIMER_CHN);
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(TCU_IDLE_TIMER_CHN));
OUTREG16(A_TCU_TECR, TCU_TIMER(TCU_IDLE_TIMER_CHN));
rest = INREG16(A_TCU_TCNT(TCU_IDLE_TIMER_CHN))/(OSC_CLOCK / 256000);
if(g_counter>0)
{
counter2 = g_counter-rest ;
g_counter = MIN(rest,*addr);
}
else
g_counter=*addr;
for(i=0;i<NUM;i++)
{
if(( counter[i]== 0 ) && ( flag== 1 ))
{
counter[i]=addr;
flag = 0 ;
}
else
{
t = *counter[i];
t-= counter2;
*counter[i] = MAX(0,t);
}
}
JZ_StartIdleTimer(g_counter, idle_timerhandle2);
}
TVE_STATUS TVE_Disable(void)
{
TVE_REG_MODE mode = TVE_REG->MODE;
mode.ENCON = 0;
OUTREG32(&TVE_REG->MODE, AS_UINT32(&mode));
/* TVDAC disable
TVDAC control is moved to MIXEDSYS
*/
//OUTREG32(VTV_CON0, 0x0);
//OUTREG32(MIXEDSYS0_BASE + 0xBC0, 0x0);
//OUTREG32(MIXEDSYS0_BASE + 0xBC4, 0x0);
OUTREG32(0xF0007600,0x1012);//Disable TV DAC
return TVE_STATUS_OK;
}
int efuseWrite(UINT32 group, UINT32* pBuf, UINT32 num)
{
int i;
SETREG32(EFUSEC_CFG, EFUSEC_APB);
SETBITVALUE32(EFUSEC_COUNT, EFUSE_COUNT_MASK, EFUSE_COUNT_CFG);
SETBITVALUE32(EFUSEC_PGM_COUNT, EFUSE_PGM_COUNT_MASK, PGM_COUNT_CFG);
SETREG32(EFUSEC_CFG, EFUSEC_PRE_PG);
if (!TestBitValue(EFUSEC_STATUS, EFUSEC_PRE_PG_FIN, EFUSEC_PRE_PG_FIN))
{
return ERROR;
}
for (i = 0; i < num; i++)
{
SETBITVALUE32(EFUSE_GROUP, EFUSE_GP_MASK, group + i);
OUTREG32(EFUSE_PG_VALUE, *(pBuf + i));
SETREG32(EFUSEC_CFG, EFUSEC_PG_EN);
if (!TestBitValue(EFUSEC_STATUS, EFUSEC_PG_STATUS, EFUSEC_PG_STATUS))
{
return ERROR;
}
}
CLRREG32(EFUSEC_CFG, EFUSEC_PRE_PG);
return OK;
}
void JZ_StopTicker(void)
{
printf("WARMING: System Timer will STOP!!!\n");
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(TCU_SYSTEM_TIMER_CHN));
OUTREG16(A_TCU_TECR, TCU_TIMER(TCU_SYSTEM_TIMER_CHN));
}
void Stop_PerformanceCounter(void)
{
printf("WARMING: Performance Counter will STOP!!!\n");
OUTREG32(A_TCU_TMSR, TCU_OSTMST);
OUTREG16(A_TCU_TECR, TCU_OSTCL);
}
