static void
fd3_draw(struct fd_context *ctx, const struct pipe_draw_info *info)
{
struct fd_ringbuffer *ring = ctx->ring;
unsigned dirty = ctx->dirty;
fd3_emit_state(ctx, dirty);
if (dirty & FD_DIRTY_VTXBUF)
emit_vertexbufs(ctx);
OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
OUT_WFI (ring);
OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
OUT_RING(ring, info->min_index); /* VFD_INDEX_MIN */
OUT_RING(ring, info->max_index); /* VFD_INDEX_MAX */
OUT_RING(ring, info->start_instance); /* VFD_INSTANCEID_OFFSET */
OUT_RING(ring, info->start); /* VFD_INDEX_OFFSET */
OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
info->restart_index : 0xffffffff);
fd_draw_emit(ctx, info);
}
static void
emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
struct pipe_surface *psurf)
{
struct fd_ringbuffer *ring = batch->gmem;
struct fd_resource *rsc = fd_resource(psurf->texture);
uint32_t swap = fmt2swap(psurf->format);
struct fd_resource_slice *slice =
fd_resource_slice(rsc, psurf->u.tex.level);
uint32_t offset =
fd_resource_offset(rsc, psurf->u.tex.level, psurf->u.tex.first_layer);
assert((slice->pitch & 31) == 0);
assert((offset & 0xfff) == 0);
if (!rsc->valid)
return;
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) |
A2XX_RB_COLOR_INFO_BASE(base) |
A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)));
OUT_PKT3(ring, CP_SET_CONSTANT, 5);
OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
OUT_RING(ring, 0x00000000); /* RB_COPY_CONTROL */
OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_COPY_DEST_BASE */
OUT_RING(ring, slice->pitch >> 5); /* RB_COPY_DEST_PITCH */
OUT_RING(ring, /* RB_COPY_DEST_INFO */
A2XX_RB_COPY_DEST_INFO_FORMAT(fd2_pipe2color(psurf->format)) |
A2XX_RB_COPY_DEST_INFO_LINEAR |
A2XX_RB_COPY_DEST_INFO_SWAP(swap) |
A2XX_RB_COPY_DEST_INFO_WRITE_RED |
A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
if (!is_a20x(batch->ctx->screen)) {
OUT_WFI (ring);
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
OUT_RING(ring, 3); /* VGT_MAX_VTX_INDX */
OUT_RING(ring, 0); /* VGT_MIN_VTX_INDX */
}
fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL);
}
static void
emit_gmem2mem_surf(struct fd_context *ctx, uint32_t base,
struct pipe_surface *psurf)
{
struct fd_ringbuffer *ring = ctx->ring;
struct fd_resource *rsc = fd_resource(psurf->texture);
uint32_t swap = fmt2swap(psurf->format);
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) |
A2XX_RB_COLOR_INFO_BASE(base) |
A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)));
OUT_PKT3(ring, CP_SET_CONSTANT, 5);
OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
OUT_RING(ring, 0x00000000); /* RB_COPY_CONTROL */
OUT_RELOCW(ring, rsc->bo, 0, 0, 0); /* RB_COPY_DEST_BASE */
OUT_RING(ring, rsc->slices[0].pitch >> 5); /* RB_COPY_DEST_PITCH */
OUT_RING(ring, /* RB_COPY_DEST_INFO */
A2XX_RB_COPY_DEST_INFO_FORMAT(fd2_pipe2color(psurf->format)) |
A2XX_RB_COPY_DEST_INFO_LINEAR |
A2XX_RB_COPY_DEST_INFO_SWAP(swap) |
A2XX_RB_COPY_DEST_INFO_WRITE_RED |
A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
OUT_WFI (ring);
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
OUT_RING(ring, 3); /* VGT_MAX_VTX_INDX */
OUT_RING(ring, 0); /* VGT_MIN_VTX_INDX */
fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
DI_SRC_SEL_AUTO_INDEX, 3, INDEX_SIZE_IGN, 0, 0, NULL);
}
static void
fd2_draw(struct fd_context *ctx, const struct pipe_draw_info *info)
{
struct fd_ringbuffer *ring = ctx->ring;
if (ctx->dirty & FD_DIRTY_VTXBUF)
emit_vertexbufs(ctx);
fd2_emit_state(ctx, ctx->dirty);
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
OUT_RING(ring, info->start);
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
OUT_RING(ring, 0x0000003b);
OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
OUT_WFI (ring);
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
OUT_RING(ring, info->max_index); /* VGT_MAX_VTX_INDX */
OUT_RING(ring, info->min_index); /* VGT_MIN_VTX_INDX */
fd_draw_emit(ctx, ring, IGNORE_VISIBILITY, info);
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_UNKNOWN_2010));
OUT_RING(ring, 0x00000000);
emit_cacheflush(ring);
}
